From: Bin Meng <bin.meng@processmission.com>
To: QEMU <qemu-devel@nongnu.org>
Cc: Conor Dooley <conor@kernel.org>, Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sebastian Huber <sebastian.huber@embedded-brains.de>,
qemu-riscv@nongnu.org
Subject: [PATCH v2 06/24] tests/qtest: Add PolarFire SoC L2CC coverage
Date: Fri, 4 Sep 2026 23:57:25 +0800 [thread overview]
Message-ID: <20260904155758.3833179-7-bin.meng@processmission.com> (raw)
In-Reply-To: <20260904155758.3833179-1-bin.meng@processmission.com>
Add a dedicated qtest binary for L2CC register and memory-topology
behavior.
Exercise Config, WayEnable, and every WayMask register, including
reset, monotonic writes, and unimplemented-register logging. Verify
that WayEnable resizes the guest-visible L2-LIM region while L2 Zero
remains fixed at the modeled 2 MiB size.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
---
(no changes since v1)
MAINTAINERS | 1 +
tests/qtest/mchp_pfsoc_l2cc_test.c | 221 +++++++++++++++++++++++++++++
tests/qtest/meson.build | 2 +
3 files changed, 224 insertions(+)
create mode 100644 tests/qtest/mchp_pfsoc_l2cc_test.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d7615b2c2c..8b7319d3d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1803,6 +1803,7 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_l2cc.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+F: tests/qtest/mchp_pfsoc_l2cc_test.c
Shakti C class SoC
L: qemu-riscv@nongnu.org
diff --git a/tests/qtest/mchp_pfsoc_l2cc_test.c b/tests/qtest/mchp_pfsoc_l2cc_test.c
new file mode 100644
index 0000000000..3401ce4300
--- /dev/null
+++ b/tests/qtest/mchp_pfsoc_l2cc_test.c
@@ -0,0 +1,221 @@
+/*
+ * QTest testcase for the Microchip PolarFire SoC L2 cache controller
+ *
+ * Copyright (c) 2026 Process Mission
+ *
+ * Author:
+ * Bin Meng <bin.meng@processmission.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "libqtest.h"
+
+#define L2CC_BASE 0x02010000
+#define L2CC_CONFIG 0x000
+#define L2CC_CONFIG_VALUE 0x06091004
+#define L2CC_WAY_ENABLE 0x008
+#define L2CC_ECC_INJECT 0x040
+#define L2CC_FLUSH64 0x200
+#define L2CC_WAY_MASK_BASE 0x800
+#define L2CC_WAY_MASK_COUNT 15
+#define L2CC_WAY_MASK(n) (L2CC_WAY_MASK_BASE + 8 * (n))
+#define L2CC_MASTER15 L2CC_WAY_MASK(L2CC_WAY_MASK_COUNT)
+#define L2CC_WAY_ENABLE_RESET 0
+#define L2CC_WAY_MASK_RESET UINT64_MAX
+
+#define L2_LIM_BASE 0x08000000
+#define L2_WAY_SIZE (128 * KiB)
+#define L2_LIM_RESET_WAYS 15
+#define L2_ZERO_BASE 0x0a000000
+#define L2_ZERO_SIZE (2 * MiB)
+
+static QTestState *mchp_pfsoc_l2cc_start(const char *firmware)
+{
+ return qtest_initf("-machine microchip-icicle-kit -smp 5 -m 2G "
+ "-bios \"%s\"", firmware);
+}
+
+static char *mchp_pfsoc_l2cc_create_firmware(void)
+{
+ static const uint8_t firmware[] = {
+ 0x13, 0x00, 0x00, 0x00,
+ 0x6f, 0x00, 0x00, 0x00,
+ };
+ char *path;
+ int fd;
+ ssize_t written;
+
+ fd = g_file_open_tmp("mchp_pfsoc_l2cc_XXXXXX", &path, NULL);
+ g_assert_cmpint(fd, >=, 0);
+
+ written = write(fd, firmware, sizeof(firmware));
+ g_assert_cmpint(written, ==, sizeof(firmware));
+ close(fd);
+
+ return path;
+}
+
+static uint64_t l2cc_way_mask_test_value(unsigned int master)
+{
+ return UINT64_C(0xfedcba9876543201) + master;
+}
+
+static void test_l2cc_registers(void)
+{
+ g_autofree char *firmware = mchp_pfsoc_l2cc_create_firmware();
+ QTestState *qts = mchp_pfsoc_l2cc_start(firmware);
+ unsigned int i;
+
+ unlink(firmware);
+
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+ qtest_writel(qts, L2CC_BASE + L2CC_CONFIG, UINT32_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xd);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xd);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 3);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xd);
+ qtest_writeq(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xf);
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xf);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xe);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xf);
+
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ qtest_writeq(qts, L2CC_BASE + L2CC_WAY_MASK(i),
+ l2cc_way_mask_test_value(i));
+ }
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ l2cc_way_mask_test_value(i));
+ }
+
+ qtest_system_reset(qts);
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ }
+
+ qtest_quit(qts);
+}
+
+static void test_l2lim_topology(void)
+{
+ g_autofree char *firmware = mchp_pfsoc_l2cc_create_firmware();
+ uint32_t original[L2_LIM_RESET_WAYS];
+ const uint32_t poison = 0xdeadc0de;
+ const uint64_t zero_last = L2_ZERO_BASE + L2_ZERO_SIZE - 4;
+ QTestState *qts = mchp_pfsoc_l2cc_start(firmware);
+ unsigned int i;
+
+ unlink(firmware);
+
+ /* Check the fixed aperture, not the RAM stand-in's eviction behavior */
+ qtest_writel(qts, zero_last, 0xa55a9669);
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0xa55a9669);
+
+ for (i = 1; i <= L2_LIM_RESET_WAYS; i++) {
+ uint64_t l2lim_size = (L2_LIM_RESET_WAYS - i) * L2_WAY_SIZE;
+ uint64_t hidden = L2_LIM_BASE + l2lim_size;
+ uint32_t tail = 0x96000000 | i;
+
+ original[i - 1] = 0x69000000 | i;
+ qtest_writel(qts, hidden, original[i - 1]);
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, original[i - 1]);
+
+ if (l2lim_size) {
+ qtest_writel(qts, hidden - 4, tail);
+ g_assert_cmphex(qtest_readl(qts, hidden - 4), ==, tail);
+ }
+
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, i);
+ g_assert_cmphex(qtest_readb(qts,
+ L2CC_BASE + L2CC_WAY_ENABLE), ==, i);
+ if (l2lim_size) {
+ g_assert_cmphex(qtest_readl(qts, hidden - 4), ==, tail);
+ }
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, 0);
+ qtest_writel(qts, hidden, poison);
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0xa55a9669);
+ }
+
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, UINT8_MAX);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ UINT8_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2_LIM_BASE), ==, 0);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 3);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ UINT8_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2_LIM_BASE), ==, 0);
+
+ qtest_system_reset(qts);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ for (i = 1; i <= L2_LIM_RESET_WAYS; i++) {
+ uint64_t restored = L2_LIM_BASE +
+ (L2_LIM_RESET_WAYS - i) * L2_WAY_SIZE;
+
+ g_assert_cmphex(qtest_readl(qts, restored), ==, original[i - 1]);
+ }
+
+ qtest_quit(qts);
+}
+
+static void test_l2cc_unimplemented(void)
+{
+ g_autofree char *firmware = mchp_pfsoc_l2cc_create_firmware();
+ g_autofree char *log_path = NULL;
+ g_autofree char *log = NULL;
+ QTestState *qts;
+ int fd;
+
+ fd = g_file_open_tmp("mchp_pfsoc_l2cc_unimp_XXXXXX", &log_path, NULL);
+ g_assert_cmpint(fd, >=, 0);
+ close(fd);
+
+ qts = qtest_initf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G -bios \"%s\" "
+ "-d unimp -D \"%s\"", firmware, log_path);
+ unlink(firmware);
+
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_ECC_INJECT), ==, 0);
+ qtest_writeq(qts, L2CC_BASE + L2CC_FLUSH64, 0x1234);
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_MASTER15), ==, 0);
+ qtest_quit(qts);
+
+ g_assert_true(g_file_get_contents(log_path, &log, NULL, NULL));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device read (size 4, offset 0x40)"));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device write (size 8, value 0x1234, offset 0x200)"));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device read (size 8, offset 0x878)"));
+ unlink(log_path);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ qtest_add_func("/mchp_pfsoc_l2cc/registers", test_l2cc_registers);
+ qtest_add_func("/mchp_pfsoc_l2cc/l2lim_topology",
+ test_l2lim_topology);
+ qtest_add_func("/mchp_pfsoc_l2cc/unimplemented",
+ test_l2cc_unimplemented);
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 17870e339b..e7fea8c180 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -303,6 +303,8 @@ qtests_riscv32 = \
qtests_riscv64 = ['riscv-csr-test'] + \
(unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_MICROCHIP_PFSOC') ?
+ ['mchp_pfsoc_l2cc_test'] : []) + \
(config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and
config_all_devices.has_key('CONFIG_RISCV_IOMMU') ?
['iommu-riscv-test'] : []) + \
--
2.53.0
next prev parent reply other threads:[~2026-09-04 16:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 15:57 [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-09-04 15:57 ` [PATCH v2 01/24] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-09-04 15:57 ` [PATCH v2 02/24] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-09-04 15:57 ` [PATCH v2 03/24] hw/misc: pfsoc: Support DDR training with newer HSS Bin Meng
2026-09-04 15:57 ` [PATCH v2 04/24] hw/misc: pfsoc: Model L2 cache controller registers Bin Meng
2026-09-04 15:57 ` [PATCH v2 05/24] hw/riscv: pfsoc: Couple L2CC to L2-LIM Bin Meng
2026-09-04 15:57 ` Bin Meng [this message]
2026-09-04 15:57 ` [PATCH v2 07/24] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-09-04 15:57 ` [PATCH v2 08/24] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer Bin Meng
2026-09-04 15:57 ` [PATCH v2 09/24] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-09-04 15:57 ` [PATCH v2 10/24] hw/sd: cadence: Add 64-bit system bus property Bin Meng
2026-09-04 15:57 ` [PATCH v2 11/24] hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support Bin Meng
2026-09-04 15:57 ` [PATCH v2 12/24] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-09-04 15:57 ` [PATCH v2 13/24] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-09-04 15:57 ` [PATCH v2 14/24] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-09-04 15:57 ` [PATCH v2 15/24] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-09-04 15:57 ` [PATCH v2 16/24] hw/misc: pfsoc: Honor PolarFire service notification requests Bin Meng
2026-09-04 15:57 ` [PATCH v2 17/24] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-09-04 15:57 ` [PATCH v2 18/24] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-09-04 15:57 ` [PATCH v2 19/24] hw/riscv: pfsoc: Fix Icicle Kit hart count at five Bin Meng
2026-09-04 15:57 ` [PATCH v2 20/24] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-09-04 15:57 ` [PATCH v2 21/24] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-09-04 15:57 ` [PATCH v2 22/24] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-09-04 15:57 ` [PATCH v2 23/24] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-09-04 15:57 ` [PATCH v2 24/24] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer Bin Meng
2026-09-04 16:11 ` [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Philippe Mathieu-Daudé
2026-09-07 13:29 ` Conor Dooley
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