Re: [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot

["Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>]

On 4/9/26 17:57, Bin Meng wrote:

> Bin Meng (23):
>    hw/riscv: pfsoc: Correct the L2LIM maximum mapped size
>    hw/riscv: pfsoc: Map the L2 zero device window
>    hw/misc: pfsoc: Support DDR training with newer HSS
>    hw/misc: pfsoc: Model L2 cache controller registers
>    hw/riscv: pfsoc: Couple L2CC to L2-LIM
>    tests/qtest: Add PolarFire SoC L2CC coverage
>    hw/sd: sdhci: Run ADMA independently of MMIO
>    hw/sd: sd: Keep high-capacity memory blocks at 512 bytes
>    hw/sd: cadence: Add 64-bit system bus property

FYI I tagged this series (in particular the SD/HCI patches)
to review but won't be able to until Sept 21. Not a blocker
although if Alistair think the series is ready.

>    hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support
>    hw/misc: pfsoc: Model PolarFire SoC serial number service
>    hw/rtc: Add PolarFire SoC RTC model
>    hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit
>    tests/qtest: Add PolarFire SoC RTC coverage
>    hw/misc: pfsoc: Honor PolarFire service notification requests
>    hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases
>    hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB
>    hw/riscv: pfsoc: Fix Icicle Kit hart count at five
>    docs/system/riscv: Document Icicle Kit HSS boot
>    docs/system/riscv: pfsoc: Document CLINT topology for direct Linux
>      boot
>    tests/functional/riscv64: Add Icicle Kit firmware boot test
>    MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer
>    MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer