* [PATCH 0/4] Add preliminary support for MSM8917
@ 2026-09-10 9:41 Reza Kurniawan
2026-09-10 9:41 ` [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init " Reza Kurniawan
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Reza Kurniawan @ 2026-09-10 9:41 UTC (permalink / raw)
To: u-boot
Cc: Reza Kurniawan, Casey Connolly, Ilias Apalodimas, Lukasz Majewski,
Neil Armstrong, Sumit Garg, Tom Rini, u-boot-qcom
This patch series adds preliminary support for booting MSM8917. It adds two
new drivers (GCC and pinctrl driver). A change is also done to the core
qcom clock code to account for the poll register offset difference between
this platform and the existing ones.
Reza Kurniawan (4):
mach-snapdragon: Carve out reserved memory at init for MSM8917
pinctrl: qcom: Add pinctrl driver for MSM8917
clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit
clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917
arch/arm/mach-snapdragon/mem_map.c | 3 +-
configs/qcom_defconfig | 1 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-msm8917.c | 196 ++++++++
drivers/clk/qcom/clock-qcom.c | 24 +-
drivers/clk/qcom/clock-qcom.h | 1 +
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8917.c | 642 +++++++++++++++++++++++++
10 files changed, 873 insertions(+), 12 deletions(-)
create mode 100644 drivers/clk/qcom/clock-msm8917.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8917.c
--
2.55.0
base-commit: d4152edb50356338af994d1c0483f65b717b4c15
branch: msm8917
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init for MSM8917
2026-09-10 9:41 [PATCH 0/4] Add preliminary support for MSM8917 Reza Kurniawan
@ 2026-09-10 9:41 ` Reza Kurniawan
2026-09-11 5:48 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 2/4] pinctrl: qcom: Add pinctrl driver " Reza Kurniawan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Reza Kurniawan @ 2026-09-10 9:41 UTC (permalink / raw)
To: u-boot
Cc: Reza Kurniawan, Casey Connolly, Ilias Apalodimas, Neil Armstrong,
Sumit Garg, Tom Rini, u-boot-qcom
Certain regions of memory in MSM8917 are marked as 'no-map'. These
regions may cause security violation when included in the standard mapping.
Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
---
arch/arm/mach-snapdragon/mem_map.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-snapdragon/mem_map.c b/arch/arm/mach-snapdragon/mem_map.c
index f64ec0c67..eb0242ef8 100644
--- a/arch/arm/mach-snapdragon/mem_map.c
+++ b/arch/arm/mach-snapdragon/mem_map.c
@@ -216,7 +216,8 @@ void enable_caches(void)
* reserved regions as inacessible (PTE_TYPE_FAULT)
*/
if (qcom_memmap_source == QCOM_MEMMAP_SOURCE_SMEM ||
- fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0) {
+ fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0 ||
+ fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,msm8917") == 0) {
carveout_start = get_timer(0);
/* Takes ~20-50ms on SDM845 */
configure_reserved_memory();
--
2.55.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] pinctrl: qcom: Add pinctrl driver for MSM8917
2026-09-10 9:41 [PATCH 0/4] Add preliminary support for MSM8917 Reza Kurniawan
2026-09-10 9:41 ` [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init " Reza Kurniawan
@ 2026-09-10 9:41 ` Reza Kurniawan
2026-09-11 6:05 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit Reza Kurniawan
2026-09-10 9:41 ` [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917 Reza Kurniawan
3 siblings, 1 reply; 9+ messages in thread
From: Reza Kurniawan @ 2026-09-10 9:41 UTC (permalink / raw)
To: u-boot
Cc: Reza Kurniawan, Casey Connolly, Neil Armstrong, Sumit Garg,
Tom Rini, u-boot-qcom
Add pinctrl driver to configure pin parameters and managing GPIOs
necessary for certain peripherals.
Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8917.c | 642 +++++++++++++++++++++++++
3 files changed, 651 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8917.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 7dd3782c1..10737b5e2 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -62,6 +62,14 @@ config PINCTRL_QCOM_MILOS
Say Y here to enable support for pinctrl on the Snapdragon Milos SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_MSM8917
+ bool "Qualcomm MSM8917 Pinctrl"
+ default y if PINCTRL_QCOM_GENERIC
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon MSM8917 SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_QCM2290
bool "Qualcomm QCM2290 Pinctrl"
default y if PINCTRL_QCOM_GENERIC
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index a7a9ad035..df445ef09 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o
obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
+obj-$(CONFIG_PINCTRL_QCOM_MSM8917) += pinctrl-msm8917.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c
new file mode 100644
index 000000000..78edd653a
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c
@@ -0,0 +1,642 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm MSM8917 pinctrl
+ *
+ * (C) Copyright 2026 Reza Kurniawan <imkyufie@gmail.com>
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\
+ [id] = { \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+enum msm8917_functions {
+ msm_mux_accel_int,
+ msm_mux_adsp_ext,
+ msm_mux_alsp_int,
+ msm_mux_atest_bbrx0,
+ msm_mux_atest_bbrx1,
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_combodac_to_gpio_native,
+ msm_mux_atest_gpsadc_dtest0_native,
+ msm_mux_atest_gpsadc_dtest1_native,
+ msm_mux_atest_tsens,
+ msm_mux_atest_wlan0,
+ msm_mux_atest_wlan1,
+ msm_mux_audio_ref,
+ msm_mux_audio_reset,
+ msm_mux_bimc_dte0,
+ msm_mux_bimc_dte1,
+ msm_mux_blsp6_spi,
+ msm_mux_blsp8_spi,
+ msm_mux_blsp_i2c1,
+ msm_mux_blsp_i2c2,
+ msm_mux_blsp_i2c3,
+ msm_mux_blsp_i2c4,
+ msm_mux_blsp_i2c5,
+ msm_mux_blsp_i2c6,
+ msm_mux_blsp_i2c7,
+ msm_mux_blsp_i2c8,
+ msm_mux_blsp_spi1,
+ msm_mux_blsp_spi2,
+ msm_mux_blsp_spi3,
+ msm_mux_blsp_spi4,
+ msm_mux_blsp_spi5,
+ msm_mux_blsp_spi6,
+ msm_mux_blsp_spi7,
+ msm_mux_blsp_spi8,
+ msm_mux_blsp_uart1,
+ msm_mux_blsp_uart2,
+ msm_mux_blsp_uart3,
+ msm_mux_blsp_uart4,
+ msm_mux_blsp_uart5,
+ msm_mux_blsp_uart6,
+ msm_mux_blsp_uart7,
+ msm_mux_blsp_uart8,
+ msm_mux_cam0_ldo,
+ msm_mux_cam1_rst,
+ msm_mux_cam1_standby,
+ msm_mux_cam2_rst,
+ msm_mux_cam2_standby,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cdc_pdm0,
+ msm_mux_codec_int1,
+ msm_mux_codec_int2,
+ msm_mux_codec_mad,
+ msm_mux_coex_uart,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_dmic0_clk,
+ msm_mux_dmic0_data,
+ msm_mux_ebi_cdc,
+ msm_mux_ebi_ch0,
+ msm_mux_ext_lpass,
+ msm_mux_forced_usb,
+ msm_mux_fp_gpio,
+ msm_mux_fp_int,
+ msm_mux_gcc_gp1_clk_a,
+ msm_mux_gcc_gp1_clk_b,
+ msm_mux_gcc_gp2_clk_a,
+ msm_mux_gcc_gp2_clk_b,
+ msm_mux_gcc_gp3_clk_a,
+ msm_mux_gcc_gp3_clk_b,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_gsm0_tx,
+ msm_mux_key_focus,
+ msm_mux_key_snapshot,
+ msm_mux_key_volp,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_lpass_slimbus,
+ msm_mux_lpass_slimbus0,
+ msm_mux_lpass_slimbus1,
+ msm_mux_m_voc,
+ msm_mux_mag_int,
+ msm_mux_mdp_vsync,
+ msm_mux_mipi_dsi0,
+ msm_mux_modem_tsync,
+ msm_mux_nav_pps,
+ msm_mux_nav_pps_in_a,
+ msm_mux_nav_pps_in_b,
+ msm_mux_nav_tsync,
+ msm_mux_nfc_pwr,
+ msm_mux_ov_ldo,
+ msm_mux_pa_indicator,
+ msm_mux_pbs0,
+ msm_mux_pbs1,
+ msm_mux_pbs2,
+ msm_mux_pri_mi2s,
+ msm_mux_pri_mi2s_mclk_a,
+ msm_mux_pri_mi2s_mclk_b,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_prng_rosc,
+ msm_mux_pwr_crypto_enabled_a,
+ msm_mux_pwr_crypto_enabled_b,
+ msm_mux_pwr_modem_enabled_a,
+ msm_mux_pwr_modem_enabled_b,
+ msm_mux_pwr_nav_enabled_a,
+ msm_mux_pwr_nav_enabled_b,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_sd_write,
+ msm_mux_sdcard_det,
+ msm_mux_sec_mi2s,
+ msm_mux_sec_mi2s_mclk_a,
+ msm_mux_sec_mi2s_mclk_b,
+ msm_mux_sensor_rst,
+ msm_mux_smb_int,
+ msm_mux_ssbi_wtr1,
+ msm_mux_ts_resout,
+ msm_mux_ts_sample,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_data,
+ msm_mux_uim2_present,
+ msm_mux_uim2_reset,
+ msm_mux_uim_batt,
+ msm_mux_us_emitter,
+ msm_mux_us_euro,
+ msm_mux_wcss_bt,
+ msm_mux_wcss_fm,
+ msm_mux_wcss_wlan,
+ msm_mux_wcss_wlan0,
+ msm_mux_wcss_wlan1,
+ msm_mux_wcss_wlan2,
+ msm_mux_webcam_rst,
+ msm_mux_webcam_standby,
+ msm_mux_wsa_io,
+ msm_mux_wsa_irq,
+ msm_mux_wsa_reset,
+ msm_mux__,
+};
+
+#define MSM_PIN_FUNCTION(fname) \
+ [msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm8917_pinctrl_functions[] = {
+ MSM_PIN_FUNCTION(accel_int),
+ MSM_PIN_FUNCTION(adsp_ext),
+ MSM_PIN_FUNCTION(alsp_int),
+ MSM_PIN_FUNCTION(atest_bbrx0),
+ MSM_PIN_FUNCTION(atest_bbrx1),
+ MSM_PIN_FUNCTION(atest_char),
+ MSM_PIN_FUNCTION(atest_char0),
+ MSM_PIN_FUNCTION(atest_char1),
+ MSM_PIN_FUNCTION(atest_char2),
+ MSM_PIN_FUNCTION(atest_char3),
+ MSM_PIN_FUNCTION(atest_combodac_to_gpio_native),
+ MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native),
+ MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native),
+ MSM_PIN_FUNCTION(atest_tsens),
+ MSM_PIN_FUNCTION(atest_wlan0),
+ MSM_PIN_FUNCTION(atest_wlan1),
+ MSM_PIN_FUNCTION(audio_ref),
+ MSM_PIN_FUNCTION(audio_reset),
+ MSM_PIN_FUNCTION(bimc_dte0),
+ MSM_PIN_FUNCTION(bimc_dte1),
+ MSM_PIN_FUNCTION(blsp6_spi),
+ MSM_PIN_FUNCTION(blsp8_spi),
+ MSM_PIN_FUNCTION(blsp_i2c1),
+ MSM_PIN_FUNCTION(blsp_i2c2),
+ MSM_PIN_FUNCTION(blsp_i2c3),
+ MSM_PIN_FUNCTION(blsp_i2c4),
+ MSM_PIN_FUNCTION(blsp_i2c5),
+ MSM_PIN_FUNCTION(blsp_i2c6),
+ MSM_PIN_FUNCTION(blsp_i2c7),
+ MSM_PIN_FUNCTION(blsp_i2c8),
+ MSM_PIN_FUNCTION(blsp_spi1),
+ MSM_PIN_FUNCTION(blsp_spi2),
+ MSM_PIN_FUNCTION(blsp_spi3),
+ MSM_PIN_FUNCTION(blsp_spi4),
+ MSM_PIN_FUNCTION(blsp_spi5),
+ MSM_PIN_FUNCTION(blsp_spi6),
+ MSM_PIN_FUNCTION(blsp_spi7),
+ MSM_PIN_FUNCTION(blsp_spi8),
+ MSM_PIN_FUNCTION(blsp_uart1),
+ MSM_PIN_FUNCTION(blsp_uart2),
+ MSM_PIN_FUNCTION(blsp_uart3),
+ MSM_PIN_FUNCTION(blsp_uart4),
+ MSM_PIN_FUNCTION(blsp_uart5),
+ MSM_PIN_FUNCTION(blsp_uart6),
+ MSM_PIN_FUNCTION(blsp_uart7),
+ MSM_PIN_FUNCTION(blsp_uart8),
+ MSM_PIN_FUNCTION(cam0_ldo),
+ MSM_PIN_FUNCTION(cam1_rst),
+ MSM_PIN_FUNCTION(cam1_standby),
+ MSM_PIN_FUNCTION(cam2_rst),
+ MSM_PIN_FUNCTION(cam2_standby),
+ MSM_PIN_FUNCTION(cam_mclk),
+ MSM_PIN_FUNCTION(cci_async),
+ MSM_PIN_FUNCTION(cci_i2c),
+ MSM_PIN_FUNCTION(cci_timer0),
+ MSM_PIN_FUNCTION(cci_timer1),
+ MSM_PIN_FUNCTION(cdc_pdm0),
+ MSM_PIN_FUNCTION(codec_int1),
+ MSM_PIN_FUNCTION(codec_int2),
+ MSM_PIN_FUNCTION(codec_mad),
+ MSM_PIN_FUNCTION(coex_uart),
+ MSM_PIN_FUNCTION(cri_trng),
+ MSM_PIN_FUNCTION(cri_trng0),
+ MSM_PIN_FUNCTION(cri_trng1),
+ MSM_PIN_FUNCTION(dbg_out),
+ MSM_PIN_FUNCTION(dmic0_clk),
+ MSM_PIN_FUNCTION(dmic0_data),
+ MSM_PIN_FUNCTION(ebi_cdc),
+ MSM_PIN_FUNCTION(ebi_ch0),
+ MSM_PIN_FUNCTION(ext_lpass),
+ MSM_PIN_FUNCTION(forced_usb),
+ MSM_PIN_FUNCTION(fp_gpio),
+ MSM_PIN_FUNCTION(fp_int),
+ MSM_PIN_FUNCTION(gcc_gp1_clk_a),
+ MSM_PIN_FUNCTION(gcc_gp1_clk_b),
+ MSM_PIN_FUNCTION(gcc_gp2_clk_a),
+ MSM_PIN_FUNCTION(gcc_gp2_clk_b),
+ MSM_PIN_FUNCTION(gcc_gp3_clk_a),
+ MSM_PIN_FUNCTION(gcc_gp3_clk_b),
+ MSM_PIN_FUNCTION(gcc_plltest),
+ MSM_PIN_FUNCTION(gcc_tlmm),
+ MSM_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(gsm0_tx),
+ MSM_PIN_FUNCTION(key_focus),
+ MSM_PIN_FUNCTION(key_snapshot),
+ MSM_PIN_FUNCTION(key_volp),
+ MSM_PIN_FUNCTION(ldo_en),
+ MSM_PIN_FUNCTION(ldo_update),
+ MSM_PIN_FUNCTION(lpass_slimbus),
+ MSM_PIN_FUNCTION(lpass_slimbus0),
+ MSM_PIN_FUNCTION(lpass_slimbus1),
+ MSM_PIN_FUNCTION(m_voc),
+ MSM_PIN_FUNCTION(mag_int),
+ MSM_PIN_FUNCTION(mdp_vsync),
+ MSM_PIN_FUNCTION(mipi_dsi0),
+ MSM_PIN_FUNCTION(modem_tsync),
+ MSM_PIN_FUNCTION(nav_pps),
+ MSM_PIN_FUNCTION(nav_pps_in_a),
+ MSM_PIN_FUNCTION(nav_pps_in_b),
+ MSM_PIN_FUNCTION(nav_tsync),
+ MSM_PIN_FUNCTION(nfc_pwr),
+ MSM_PIN_FUNCTION(ov_ldo),
+ MSM_PIN_FUNCTION(pa_indicator),
+ MSM_PIN_FUNCTION(pbs0),
+ MSM_PIN_FUNCTION(pbs1),
+ MSM_PIN_FUNCTION(pbs2),
+ MSM_PIN_FUNCTION(pri_mi2s),
+ MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
+ MSM_PIN_FUNCTION(pri_mi2s_mclk_b),
+ MSM_PIN_FUNCTION(pri_mi2s_ws),
+ MSM_PIN_FUNCTION(prng_rosc),
+ MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
+ MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
+ MSM_PIN_FUNCTION(pwr_modem_enabled_a),
+ MSM_PIN_FUNCTION(pwr_modem_enabled_b),
+ MSM_PIN_FUNCTION(pwr_nav_enabled_a),
+ MSM_PIN_FUNCTION(pwr_nav_enabled_b),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
+ MSM_PIN_FUNCTION(qdss_traceclk_a),
+ MSM_PIN_FUNCTION(qdss_traceclk_b),
+ MSM_PIN_FUNCTION(qdss_tracectl_a),
+ MSM_PIN_FUNCTION(qdss_tracectl_b),
+ MSM_PIN_FUNCTION(qdss_tracedata_a),
+ MSM_PIN_FUNCTION(qdss_tracedata_b),
+ MSM_PIN_FUNCTION(sd_write),
+ MSM_PIN_FUNCTION(sdcard_det),
+ MSM_PIN_FUNCTION(sec_mi2s),
+ MSM_PIN_FUNCTION(sec_mi2s_mclk_a),
+ MSM_PIN_FUNCTION(sec_mi2s_mclk_b),
+ MSM_PIN_FUNCTION(sensor_rst),
+ MSM_PIN_FUNCTION(smb_int),
+ MSM_PIN_FUNCTION(ssbi_wtr1),
+ MSM_PIN_FUNCTION(ts_resout),
+ MSM_PIN_FUNCTION(ts_sample),
+ MSM_PIN_FUNCTION(uim1_clk),
+ MSM_PIN_FUNCTION(uim1_data),
+ MSM_PIN_FUNCTION(uim1_present),
+ MSM_PIN_FUNCTION(uim1_reset),
+ MSM_PIN_FUNCTION(uim2_clk),
+ MSM_PIN_FUNCTION(uim2_data),
+ MSM_PIN_FUNCTION(uim2_present),
+ MSM_PIN_FUNCTION(uim2_reset),
+ MSM_PIN_FUNCTION(uim_batt),
+ MSM_PIN_FUNCTION(us_emitter),
+ MSM_PIN_FUNCTION(us_euro),
+ MSM_PIN_FUNCTION(wcss_bt),
+ MSM_PIN_FUNCTION(wcss_fm),
+ MSM_PIN_FUNCTION(wcss_wlan),
+ MSM_PIN_FUNCTION(wcss_wlan0),
+ MSM_PIN_FUNCTION(wcss_wlan1),
+ MSM_PIN_FUNCTION(wcss_wlan2),
+ MSM_PIN_FUNCTION(webcam_rst),
+ MSM_PIN_FUNCTION(webcam_standby),
+ MSM_PIN_FUNCTION(wsa_io),
+ MSM_PIN_FUNCTION(wsa_irq),
+ MSM_PIN_FUNCTION(wsa_reset),
+};
+
+static const msm_pin_function msm8917_pin_functions[] = {
+ PINGROUP(0, blsp_spi1, blsp_uart1, qdss_tracedata_b, _, _, _, _,
+ _, _),
+ PINGROUP(1, blsp_spi1, blsp_uart1, adsp_ext, _, _, _, _, _,
+ qdss_tracedata_b),
+ PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, prng_rosc, _, _, _,
+ _, _),
+ PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _),
+ PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _,
+ atest_combodac_to_gpio_native, _, _, _, _),
+ PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _),
+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b,
+ qdss_tracedata_b, _, _, _, _),
+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, pbs2, _,
+ qdss_tracedata_b, _, atest_gpsadc_dtest0_native, _),
+ PINGROUP(8, blsp_spi3, blsp_uart3, pbs0, _, _, _, _, _, _),
+ PINGROUP(9, blsp_spi3, blsp_uart3, pbs1, pwr_modem_enabled_b, _, _,
+ _, _, _),
+ PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp2_clk_b, _, _,
+ _, _, _),
+ PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp3_clk_b, _, _,
+ _, _, _),
+ PINGROUP(12, blsp_spi4, blsp_uart4, sec_mi2s, pwr_nav_enabled_b, _,
+ _, _, _, _),
+ PINGROUP(13, blsp_spi4, blsp_uart4, sec_mi2s, pwr_crypto_enabled_b, _,
+ _, _, _, _),
+ PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
+ PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
+ PINGROUP(16, blsp_spi5, blsp_uart5, _, _, _, _, qdss_traceclk_a,
+ _, atest_bbrx1),
+ PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _,
+ atest_bbrx0, _, _, _),
+ PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracectl_a, _,
+ atest_gpsadc_dtest1_native, _, _, _),
+ PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _,
+ _, _, _, _),
+ PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, _, _, _,
+ qdss_tracectl_b),
+ PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, _, _,
+ qdss_cti_trig_in_b0),
+ PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _,
+ atest_wlan0, _, _, _),
+ PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _,
+ atest_wlan1, _, _, _),
+ PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _),
+ PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, _, _, _,
+ _, _, _),
+ PINGROUP(26, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _, _),
+ PINGROUP(27, cam_mclk, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(28, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _,
+ atest_combodac_to_gpio_native),
+ PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, _, _,
+ qdss_tracedata_a, _),
+ PINGROUP(30, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(31, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(32, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(33, cci_timer0, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(34, cci_timer1, _, _, _, _, _, _, _, qdss_tracedata_a),
+ PINGROUP(35, pwr_nav_enabled_a, _, _, _, _, _, _, _,
+ qdss_tracedata_a),
+ PINGROUP(36, pwr_crypto_enabled_a, _, _, _, _, _, _, _,
+ qdss_tracedata_a),
+ PINGROUP(37, _, _, _, _, _, qdss_cti_trig_out_b1, _, _, _),
+ PINGROUP(38, _, qdss_tracedata_a, _, _, _, _, _, _, _),
+ PINGROUP(39, cci_async, _, _, _, _, _, qdss_tracedata_a, _,
+ atest_combodac_to_gpio_native),
+ PINGROUP(40, _, _, _, _, qdss_tracedata_a, _,
+ atest_combodac_to_gpio_native, _, _),
+ PINGROUP(41, sd_write, _, _, _, _, _, _, _,
+ atest_combodac_to_gpio_native),
+ PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _,
+ atest_combodac_to_gpio_native, _, _, _, _, _),
+ PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _,
+ atest_combodac_to_gpio_native, _, _, _, _, _),
+ PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _,
+ atest_combodac_to_gpio_native, _, _, _, _, _),
+ PINGROUP(45, _, _, atest_combodac_to_gpio_native, _, _, _, _, _,
+ _),
+ PINGROUP(46, _, _, atest_combodac_to_gpio_native, _, _, _, _, _,
+ _),
+ PINGROUP(47, blsp6_spi, _, qdss_tracedata_b, _,
+ atest_combodac_to_gpio_native, _, _, _, _),
+ PINGROUP(48, _, qdss_cti_trig_in_b1, _,
+ atest_combodac_to_gpio_native, _, _, _, _, _),
+ PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _),
+ PINGROUP(50, qdss_tracedata_a, _, _, _, _, _, _, _, _),
+ PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _),
+ PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _),
+ PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _),
+ PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _),
+ PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _),
+ PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _),
+ PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _),
+ PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _),
+ PINGROUP(59, _, _, _, _, _, _, _, _, _),
+ PINGROUP(60, _, _, _, _, _, _, _, _, _),
+ PINGROUP(61, _, _, _, _, _, _, _, _, _),
+ PINGROUP(62, _, _, _, _, _, _, _, _, _),
+ PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _),
+ PINGROUP(64, _, _, _, _, _, _, _, _, _),
+ PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _),
+ PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _,
+ _, _, _),
+ PINGROUP(67, atest_char1, ebi_cdc, _, atest_combodac_to_gpio_native,
+ _, _, _, _, _),
+ PINGROUP(68, atest_char0, _, _, _, _, _, _, _, _),
+ PINGROUP(69, audio_ref, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _,
+ _, _),
+ PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _),
+ PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _),
+ PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _),
+ PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _),
+ PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _),
+ PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _),
+ PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _),
+ PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _),
+ PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _),
+ PINGROUP(82, wcss_fm, cri_trng, _, _, _, _, _, _, _),
+ PINGROUP(83, wcss_bt, cri_trng1, _, _, _, _, _, _, _),
+ PINGROUP(84, wcss_bt, cri_trng0, _, _, _, _, _, _, _),
+ PINGROUP(85, pri_mi2s, blsp_spi7, blsp_uart7, _, _, _, _, _, _),
+ PINGROUP(86, pri_mi2s, blsp_spi7, blsp_uart7, qdss_tracedata_b, _, _,
+ _, _, _),
+ PINGROUP(87, pri_mi2s_ws, blsp_spi7, blsp_uart7, blsp_i2c7,
+ qdss_tracedata_b, gcc_tlmm, _, _, _),
+ PINGROUP(88, pri_mi2s, blsp_spi7, blsp_uart7, blsp_i2c7, _, _, _,
+ _, _),
+ PINGROUP(89, dmic0_clk, _, _, _, _, _, _, _, _),
+ PINGROUP(90, dmic0_data, _, _, _, _, _, _, _, _),
+ PINGROUP(91, _, _, _, _, _, qdss_cti_trig_in_a1, _, _, _),
+ PINGROUP(92, _, _, _, _, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(93, _, _, _, _, _, _, _, _, _),
+ PINGROUP(94, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _),
+ PINGROUP(95, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _),
+ PINGROUP(96, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _),
+ PINGROUP(97, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _),
+ PINGROUP(98, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _,
+ _, _),
+ PINGROUP(99, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _,
+ _, _),
+ PINGROUP(100, _, _, _, _, _, _, _, _, _),
+ PINGROUP(101, _, _, _, _, _, _, _, _, _),
+ PINGROUP(102, _, _, _, _, _, _, _, _, _),
+ PINGROUP(103, _, _, _, _, _, _, _, _, _),
+ PINGROUP(104, _, _, _, _, _, _, _, _, _),
+ PINGROUP(105, _, _, _, _, _, _, _, _, _),
+ PINGROUP(106, _, _, _, _, _, _, _, _, _),
+ PINGROUP(107, _, _, _, _, _, _, _, _, _),
+ PINGROUP(108, _, _, _, _, _, _, _, _, _),
+ PINGROUP(109, _, _, _, _, _, _, _, _, _),
+ PINGROUP(110, _, _, _, _, _, _, _, _, _),
+ PINGROUP(111, _, _, _, _, _, _, _, _, _),
+ PINGROUP(112, _, _, _, _, _, _, _, _, _),
+ PINGROUP(113, _, _, _, _, _, _, _, _, _),
+ PINGROUP(114, _, _, _, _, _, _, _, _, _),
+ PINGROUP(115, _, _, nav_pps_in_a, _, atest_combodac_to_gpio_native,
+ _, _, _, _),
+ PINGROUP(116, _, pa_indicator, _, _, _, _, _, _, _),
+ PINGROUP(117, _, modem_tsync, nav_tsync, nav_pps_in_b, nav_pps, _,
+ _, _, _),
+ PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _),
+ PINGROUP(119, gsm0_tx, _, ebi_cdc, _, _, _, _, _, _),
+ PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _),
+ PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _),
+ PINGROUP(122, _, ssbi_wtr1, _, _, bimc_dte1, _, _, _, _),
+ PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _),
+ PINGROUP(124, coex_uart, _, _, _, _, _, _, _, _),
+ PINGROUP(125, _, _, _, _, _, _, _, _, _),
+ PINGROUP(126, _, _, _, _, _, _, _, _, _),
+ PINGROUP(127, coex_uart, _, _, _, _, _, _, _, _),
+ PINGROUP(128, _, _, _, _, _, _, _, _, _),
+ PINGROUP(129, _, _, _, _, _, _, _, _, _),
+ PINGROUP(130, blsp8_spi, _, _, _, _, _, _, _, _),
+ PINGROUP(131, _, _, _, _, _, _, _, _, _),
+ PINGROUP(132, qdss_cti_trig_out_a0, _, _, _, _, _, _, _, _),
+ PINGROUP(133, qdss_cti_trig_out_a1, _, _, _, _, _, _, _, _)
+};
+
+static const struct msm_special_pin_data msm8917_special_pins_data[] = {
+ SDC_PINGROUP("sdc1_clk", 0x10a000, 13, 6),
+ SDC_PINGROUP("sdc1_cmd", 0x10a000, 11, 3),
+ SDC_PINGROUP("sdc1_data", 0x10a000, 9, 0),
+ SDC_PINGROUP("sdc1_rclk", 0x10a000, 15, 0),
+ SDC_PINGROUP("sdc2_clk", 0x109000, 14, 6),
+ SDC_PINGROUP("sdc2_cmd", 0x109000, 11, 3),
+ SDC_PINGROUP("sdc2_data", 0x109000, 9, 0),
+ SDC_PINGROUP("qdsd_clk", 0x19c000, 3, 0),
+ SDC_PINGROUP("qdsd_cmd", 0x19c000, 8, 5),
+ SDC_PINGROUP("qdsd_data0", 0x19c000, 13, 10),
+ SDC_PINGROUP("qdsd_data1", 0x19c000, 18, 15),
+ SDC_PINGROUP("qdsd_data2", 0x19c000, 23, 20),
+ SDC_PINGROUP("qdsd_data3", 0x19c000, 28, 25),
+};
+
+#define N_GPIO ARRAY_SIZE(msm8917_pin_functions)
+#define N_SPECIAL ARRAY_SIZE(msm8917_special_pins_data)
+
+static int msm8917_get_function_mux(unsigned int pin, unsigned int selector)
+{
+ unsigned int i;
+ const msm_pin_function *func;
+
+ if (pin >= N_GPIO)
+ return -EINVAL;
+
+ func = msm8917_pin_functions + pin;
+
+ for (i = 0; i < 10; i++)
+ if ((*func)[i] == selector)
+ return i;
+
+ pr_err("Can't find requested function for pin %u\n", pin);
+
+ return -EINVAL;
+}
+
+static const char *msm8917_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm8917_pinctrl_functions[selector].name;
+}
+
+static const char *msm8917_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector >= N_GPIO)
+ return msm8917_special_pins_data[selector - N_GPIO].name;
+
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static const struct msm_pinctrl_data msm8917_data = {
+ .pin_data = {
+ .pin_count = N_GPIO + N_SPECIAL,
+ .special_pins_start = N_GPIO,
+ .special_pins_data = msm8917_special_pins_data,
+ },
+ .functions_count = ARRAY_SIZE(msm8917_pinctrl_functions),
+ .get_function_name = msm8917_get_function_name,
+ .get_function_mux = msm8917_get_function_mux,
+ .get_pin_name = msm8917_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ {
+ .compatible = "qcom,msm8917-pinctrl",
+ .data = (ulong)&msm8917_data
+ },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_msm8917) = {
+ .name = "pinctrl_msm8917",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.55.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit
2026-09-10 9:41 [PATCH 0/4] Add preliminary support for MSM8917 Reza Kurniawan
2026-09-10 9:41 ` [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init " Reza Kurniawan
2026-09-10 9:41 ` [PATCH 2/4] pinctrl: qcom: Add pinctrl driver " Reza Kurniawan
@ 2026-09-10 9:41 ` Reza Kurniawan
2026-09-11 6:18 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917 Reza Kurniawan
3 siblings, 1 reply; 9+ messages in thread
From: Reza Kurniawan @ 2026-09-10 9:41 UTC (permalink / raw)
To: u-boot
Cc: Reza Kurniawan, Casey Connolly, Lukasz Majewski, Neil Armstrong,
Sumit Garg, Tom Rini, u-boot-qcom
Some SoCs such as MSM8917 poll its GDSC power domains by reading GDSCR
directly, as opposed to GDSCR + CFG_GDSCR_OFFSET.
Add a poll_gdscr flag to struct qcom_power_map to facilitate those SoCs.
Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
---
drivers/clk/qcom/clock-qcom.c | 24 +++++++++++++-----------
drivers/clk/qcom/clock-qcom.h | 1 +
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 6b46d9db7..754ff4ff4 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -505,9 +505,9 @@ U_BOOT_DRIVER(qcom_reset) = {
static int qcom_power_set(struct power_domain *pwr, bool on)
{
struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
- void __iomem *base = dev_get_priv(pwr->dev);
+ void __iomem *base = dev_get_priv(pwr->dev), *poll_addr;
const struct qcom_power_map *map;
- u32 value;
+ u32 value, mask;
int ret;
if (pwr->id >= data->num_power_domains)
@@ -527,19 +527,21 @@ static int qcom_power_set(struct power_domain *pwr, bool on)
writel(value, base + map->reg);
- if (on)
- ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
+ poll_addr = base + map->reg;
+ if (map->poll_gdscr) {
+ /* Some SOCs such as MSM8917 poll at GDSCR */
+ ret = readl_poll_timeout(poll_addr,
value,
- (value & GDSC_POWER_UP_COMPLETE) ||
- (value & GDSC_PWR_ON_MASK),
+ (!!(value & GDSC_PWR_ON_MASK) == on),
GDSC_STATUS_POLL_TIMEOUT_US);
-
- else
- ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
+ } else {
+ mask = on ? GDSC_POWER_UP_COMPLETE : GDSC_POWER_DOWN_COMPLETE;
+ ret = readl_poll_timeout(poll_addr + CFG_GDSCR_OFFSET,
value,
- (value & GDSC_POWER_DOWN_COMPLETE) ||
- !(value & GDSC_PWR_ON_MASK),
+ (value & mask) ||
+ !!(value & GDSC_PWR_ON_MASK) == on,
GDSC_STATUS_POLL_TIMEOUT_US);
+ }
if (ret == -ETIMEDOUT)
printf("WARNING: GDSC %lu is stuck during power on/off\n",
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 3a4550d85..0b514cc1f 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -76,6 +76,7 @@ struct qcom_reset_map {
struct qcom_power_map {
unsigned int reg;
+ bool poll_gdscr;
};
struct clk;
--
2.55.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917
2026-09-10 9:41 [PATCH 0/4] Add preliminary support for MSM8917 Reza Kurniawan
` (2 preceding siblings ...)
2026-09-10 9:41 ` [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit Reza Kurniawan
@ 2026-09-10 9:41 ` Reza Kurniawan
2026-09-11 6:29 ` Balaji Selvanathan
3 siblings, 1 reply; 9+ messages in thread
From: Reza Kurniawan @ 2026-09-10 9:41 UTC (permalink / raw)
To: u-boot
Cc: Reza Kurniawan, Casey Connolly, Lukasz Majewski, Neil Armstrong,
Sumit Garg, Tom Rini, u-boot-qcom
Add Global Clock Controller (GCC) driver for MSM8917 to manage clocks,
resets, and gdscs. This driver includes the essential clocks and
resets for U-Boot to function.
Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
---
configs/qcom_defconfig | 1 +
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-msm8917.c | 196 +++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
create mode 100644 drivers/clk/qcom/clock-msm8917.c
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 7d4a2b589..59cad58a9 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -57,6 +57,7 @@ CONFIG_CLK_STUB=y
CONFIG_CLK_QCOM_APQ8016=y
CONFIG_CLK_QCOM_APQ8096=y
CONFIG_CLK_QCOM_MILOS=y
+CONFIG_CLK_QCOM_MSM8917=y
CONFIG_CLK_QCOM_QCM2290=y
CONFIG_CLK_QCOM_QCS404=y
CONFIG_CLK_QCOM_QCS615=y
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 95b650831..d8469ad5f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -55,6 +55,14 @@ config CLK_QCOM_MILOS
on the Snapdragon Milos SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_MSM8917
+ bool "Qualcomm MSM8917 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon MSM8917 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_QCM2290
bool "Qualcomm QCM2290 GCC"
select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1adca029b..6478ec322 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o
obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o
+obj-$(CONFIG_CLK_QCOM_MSM8917) += clock-msm8917.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
diff --git a/drivers/clk/qcom/clock-msm8917.c b/drivers/clk/qcom/clock-msm8917.c
new file mode 100644
index 000000000..2cb1fa961
--- /dev/null
+++ b/drivers/clk/qcom/clock-msm8917.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock drivers for Qualcomm MSM8917
+ *
+ * (C) Copyright 2026 Reza Kurniawan <imkyufie@gmail.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/kernel.h>
+#include <dt-bindings/clock/qcom,gcc-msm8917.h>
+
+#include "clock-qcom.h"
+
+#define CFG_CLK_SRC_GPLL4_SDCC1 (2 << 8)
+
+static const struct gate_clk msm8917_clks[] = {
+ GATE_CLK_POLLED(GCC_BLSP1_UART1_APPS_CLK, 0x0203c, BIT(0), 0x0203c),
+ GATE_CLK_POLLED(GCC_BLSP1_UART2_APPS_CLK, 0x0302c, BIT(0), 0x0302c),
+ GATE_CLK_POLLED(GCC_BLSP2_UART1_APPS_CLK, 0x0c03c, BIT(0), 0x0c03c),
+ GATE_CLK_POLLED(GCC_BLSP2_UART2_APPS_CLK, 0x0d02c, BIT(0), 0x0d02c),
+ GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c),
+ GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018),
+ GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c),
+ GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018),
+ GATE_CLK_POLLED(GCC_USB_HS_PHY_CFG_AHB_CLK, 0x41030, BIT(0), 0x41030),
+ GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008),
+ GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004),
+ GATE_CLK_POLLED(GCC_USB2A_PHY_SLEEP_CLK, 0x4102c, BIT(0), 0x4102c)
+};
+
+static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
+ F(3686400, CFG_CLK_SRC_GPLL0, 1, 72, 15625),
+ F(7372800, CFG_CLK_SRC_GPLL0, 1, 144, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0, 1, 288, 15625),
+ F(16000000, CFG_CLK_SRC_GPLL0, 10, 1, 5),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(24000000, CFG_CLK_SRC_GPLL0, 1, 3, 100),
+ F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
+ F(32000000, CFG_CLK_SRC_GPLL0, 1, 1, 25),
+ F(40000000, CFG_CLK_SRC_GPLL0, 1, 1, 20),
+ F(46400000, CFG_CLK_SRC_GPLL0, 1, 29, 500),
+ F(48000000, CFG_CLK_SRC_GPLL0, 1, 3, 50),
+ F(51200000, CFG_CLK_SRC_GPLL0, 1, 8, 125),
+ F(56000000, CFG_CLK_SRC_GPLL0, 1, 7, 100),
+ F(58982400, CFG_CLK_SRC_GPLL0, 1, 1152, 15625),
+ F(60000000, CFG_CLK_SRC_GPLL0, 1, 3, 40),
+ F(64000000, CFG_CLK_SRC_GPLL0, 1, 2, 25),
+ { }
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+ F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4),
+ F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
+ F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
+ F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(192000000, CFG_CLK_SRC_GPLL4_SDCC1, 6, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+ F(384000000, CFG_CLK_SRC_GPLL4_SDCC1, 3, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+ F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4),
+ F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
+ F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
+ F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
+ F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
+ F(133330000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ F(177780000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ { }
+};
+
+static int msm8917_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv;
+
+ priv = dev_get_priv(clk->dev);
+ return qcom_gate_clk_en(priv, clk->id);
+}
+
+static ulong msm8917_uart_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+ u32 cmd_rcgr;
+
+ switch (clk->id) {
+ case GCC_BLSP1_UART1_APPS_CLK:
+ cmd_rcgr = 0x02044;
+ break;
+ case GCC_BLSP1_UART2_APPS_CLK:
+ cmd_rcgr = 0x03034;
+ break;
+ case GCC_BLSP2_UART1_APPS_CLK:
+ cmd_rcgr = 0x0c044;
+ break;
+ case GCC_BLSP2_UART2_APPS_CLK:
+ cmd_rcgr = 0x0d034;
+ break;
+ default:
+ return 0;
+ }
+
+ freq = qcom_find_freq(ftbl_blsp_uart_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, cmd_rcgr,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+
+ return freq->freq;
+}
+
+static ulong msm8917_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_BLSP1_UART1_APPS_CLK:
+ case GCC_BLSP1_UART2_APPS_CLK:
+ case GCC_BLSP2_UART1_APPS_CLK:
+ case GCC_BLSP2_UART2_APPS_CLK:
+ return msm8917_uart_set_rate(clk, rate);
+ case GCC_SDCC1_APPS_CLK:
+ freq = qcom_find_freq(ftbl_sdcc1_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x42004,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x43004,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB_HS_SYSTEM_CLK:
+ freq = qcom_find_freq(ftbl_usb_hs_system_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x41010,
+ freq->pre_div, freq->m, freq->n, freq->src, 0);
+ return freq->freq;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const struct qcom_reset_map msm8917_resets[] = {
+ [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
+ [GCC_MSS_BCR] = { 0x71000 },
+ [GCC_QUSB2_PHY_BCR] = { 0x4103c },
+ [GCC_USB_HS_BCR] = { 0x41000 },
+ [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
+ [GCC_MDSS_BCR] = { 0x4d074 },
+};
+
+static const struct qcom_power_map msm8917_gdscs[] = {
+ [MDSS_GDSC] = { 0x4d078, true },
+};
+
+static struct msm_clk_data msm8917_gcc_data = {
+ .resets = msm8917_resets,
+ .num_resets = ARRAY_SIZE(msm8917_resets),
+ .clks = msm8917_clks,
+ .num_clks = ARRAY_SIZE(msm8917_clks),
+ .power_domains = msm8917_gdscs,
+ .num_power_domains = ARRAY_SIZE(msm8917_gdscs),
+
+ .enable = msm8917_enable,
+ .set_rate = msm8917_set_rate,
+};
+
+static const struct udevice_id gcc_msm8917_of_match[] = {
+ {
+ .compatible = "qcom,gcc-msm8917",
+ .data = (ulong)&msm8917_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_msm8917) = {
+ .name = "gcc_msm8917",
+ .id = UCLASS_NOP,
+ .of_match = gcc_msm8917_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.55.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init for MSM8917
2026-09-10 9:41 ` [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init " Reza Kurniawan
@ 2026-09-11 5:48 ` Balaji Selvanathan
0 siblings, 0 replies; 9+ messages in thread
From: Balaji Selvanathan @ 2026-09-11 5:48 UTC (permalink / raw)
To: Reza Kurniawan, u-boot
Cc: Casey Connolly, Ilias Apalodimas, Neil Armstrong, Sumit Garg,
Tom Rini, u-boot-qcom
Hi Reza,
Thanks for the series.
On 9/10/2026 3:11 PM, Reza Kurniawan wrote:
> Certain regions of memory in MSM8917 are marked as 'no-map'. These
> regions may cause security violation when included in the standard mapping.
>
> Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>
> ---
>
> arch/arm/mach-snapdragon/mem_map.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-snapdragon/mem_map.c b/arch/arm/mach-snapdragon/mem_map.c
> index f64ec0c67..eb0242ef8 100644
> --- a/arch/arm/mach-snapdragon/mem_map.c
> +++ b/arch/arm/mach-snapdragon/mem_map.c
> @@ -216,7 +216,8 @@ void enable_caches(void)
> * reserved regions as inacessible (PTE_TYPE_FAULT)
> */
> if (qcom_memmap_source == QCOM_MEMMAP_SOURCE_SMEM ||
> - fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0) {
> + fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0 ||
> + fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,msm8917") == 0) {
> carveout_start = get_timer(0);
> /* Takes ~20-50ms on SDM845 */
> configure_reserved_memory();
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] pinctrl: qcom: Add pinctrl driver for MSM8917
2026-09-10 9:41 ` [PATCH 2/4] pinctrl: qcom: Add pinctrl driver " Reza Kurniawan
@ 2026-09-11 6:05 ` Balaji Selvanathan
0 siblings, 0 replies; 9+ messages in thread
From: Balaji Selvanathan @ 2026-09-11 6:05 UTC (permalink / raw)
To: Reza Kurniawan, u-boot
Cc: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini, u-boot-qcom
Hi Reza,
On 9/10/2026 3:11 PM, Reza Kurniawan wrote:
> Add pinctrl driver to configure pin parameters and managing GPIOs
> necessary for certain peripherals.
Can you mention the linux commit you ported this from? in following format:
"Taken from Linux commit <short_sha> ("<kernel_commit_summary>")"
> Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
> ---
>
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-msm8917.c | 642 +++++++++++++++++++++++++
> 3 files changed, 651 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8917.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 7dd3782c1..10737b5e2 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -62,6 +62,14 @@ config PINCTRL_QCOM_MILOS
> Say Y here to enable support for pinctrl on the Snapdragon Milos SoC,
> as well as the associated GPIO driver.
>
> +config PINCTRL_QCOM_MSM8917
> + bool "Qualcomm MSM8917 Pinctrl"
> + default y if PINCTRL_QCOM_GENERIC
> + select PINCTRL_QCOM
> + help
> + Say Y here to enable support for pinctrl on the Snapdragon MSM8917 SoC,
> + as well as the associated GPIO driver.
> +
> config PINCTRL_QCOM_QCM2290
> bool "Qualcomm QCM2290 Pinctrl"
> default y if PINCTRL_QCOM_GENERIC
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index a7a9ad035..df445ef09 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o
> obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
> obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
> obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
> +obj-$(CONFIG_PINCTRL_QCOM_MSM8917) += pinctrl-msm8917.o
> obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c
> new file mode 100644
> index 000000000..78edd653a
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c
> @@ -0,0 +1,642 @@
> +// SPDX-License-Identifier: GPL-2.0+
This should be GPL-2.0-only i guess.
> +/*
> + * Qualcomm MSM8917 pinctrl
> + *
> + * (C) Copyright 2026 Reza Kurniawan <imkyufie@gmail.com>
> + *
> + */
> +
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +typedef unsigned int msm_pin_function[10];
> +
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\
> + [id] = { \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9 \
> + }
> +
> +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
> + { \
> + .name = pg_name, \
> + .ctl_reg = ctl, \
> + .io_reg = 0, \
> + .pull_bit = pull, \
> + .drv_bit = drv, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = -1, \
> + }
> +
> +enum msm8917_functions {
> + msm_mux_accel_int,
> + msm_mux_adsp_ext,
> + msm_mux_alsp_int,
> + msm_mux_atest_bbrx0,
> + msm_mux_atest_bbrx1,
> + msm_mux_atest_char,
> + msm_mux_atest_char0,
> + msm_mux_atest_char1,
> + msm_mux_atest_char2,
> + msm_mux_atest_char3,
> + msm_mux_atest_combodac_to_gpio_native,
> + msm_mux_atest_gpsadc_dtest0_native,
> + msm_mux_atest_gpsadc_dtest1_native,
> + msm_mux_atest_tsens,
> + msm_mux_atest_wlan0,
> + msm_mux_atest_wlan1,
> + msm_mux_audio_ref,
> + msm_mux_audio_reset,
> + msm_mux_bimc_dte0,
> + msm_mux_bimc_dte1,
> + msm_mux_blsp6_spi,
> + msm_mux_blsp8_spi,
> + msm_mux_blsp_i2c1,
> + msm_mux_blsp_i2c2,
> + msm_mux_blsp_i2c3,
> + msm_mux_blsp_i2c4,
> + msm_mux_blsp_i2c5,
> + msm_mux_blsp_i2c6,
> + msm_mux_blsp_i2c7,
> + msm_mux_blsp_i2c8,
> + msm_mux_blsp_spi1,
> + msm_mux_blsp_spi2,
> + msm_mux_blsp_spi3,
> + msm_mux_blsp_spi4,
> + msm_mux_blsp_spi5,
> + msm_mux_blsp_spi6,
> + msm_mux_blsp_spi7,
> + msm_mux_blsp_spi8,
> + msm_mux_blsp_uart1,
> + msm_mux_blsp_uart2,
> + msm_mux_blsp_uart3,
> + msm_mux_blsp_uart4,
> + msm_mux_blsp_uart5,
> + msm_mux_blsp_uart6,
> + msm_mux_blsp_uart7,
> + msm_mux_blsp_uart8,
> + msm_mux_cam0_ldo,
> + msm_mux_cam1_rst,
> + msm_mux_cam1_standby,
> + msm_mux_cam2_rst,
> + msm_mux_cam2_standby,
> + msm_mux_cam_mclk,
> + msm_mux_cci_async,
> + msm_mux_cci_i2c,
> + msm_mux_cci_timer0,
> + msm_mux_cci_timer1,
> + msm_mux_cdc_pdm0,
> + msm_mux_codec_int1,
> + msm_mux_codec_int2,
> + msm_mux_codec_mad,
> + msm_mux_coex_uart,
> + msm_mux_cri_trng,
> + msm_mux_cri_trng0,
> + msm_mux_cri_trng1,
> + msm_mux_dbg_out,
> + msm_mux_dmic0_clk,
> + msm_mux_dmic0_data,
> + msm_mux_ebi_cdc,
> + msm_mux_ebi_ch0,
> + msm_mux_ext_lpass,
> + msm_mux_forced_usb,
> + msm_mux_fp_gpio,
> + msm_mux_fp_int,
> + msm_mux_gcc_gp1_clk_a,
> + msm_mux_gcc_gp1_clk_b,
> + msm_mux_gcc_gp2_clk_a,
> + msm_mux_gcc_gp2_clk_b,
> + msm_mux_gcc_gp3_clk_a,
> + msm_mux_gcc_gp3_clk_b,
> + msm_mux_gcc_plltest,
> + msm_mux_gcc_tlmm,
> + msm_mux_gpio,
> + msm_mux_gsm0_tx,
> + msm_mux_key_focus,
> + msm_mux_key_snapshot,
> + msm_mux_key_volp,
> + msm_mux_ldo_en,
> + msm_mux_ldo_update,
> + msm_mux_lpass_slimbus,
> + msm_mux_lpass_slimbus0,
> + msm_mux_lpass_slimbus1,
> + msm_mux_m_voc,
> + msm_mux_mag_int,
> + msm_mux_mdp_vsync,
> + msm_mux_mipi_dsi0,
> + msm_mux_modem_tsync,
> + msm_mux_nav_pps,
> + msm_mux_nav_pps_in_a,
> + msm_mux_nav_pps_in_b,
> + msm_mux_nav_tsync,
> + msm_mux_nfc_pwr,
> + msm_mux_ov_ldo,
> + msm_mux_pa_indicator,
> + msm_mux_pbs0,
> + msm_mux_pbs1,
> + msm_mux_pbs2,
> + msm_mux_pri_mi2s,
> + msm_mux_pri_mi2s_mclk_a,
> + msm_mux_pri_mi2s_mclk_b,
> + msm_mux_pri_mi2s_ws,
> + msm_mux_prng_rosc,
> + msm_mux_pwr_crypto_enabled_a,
> + msm_mux_pwr_crypto_enabled_b,
> + msm_mux_pwr_modem_enabled_a,
> + msm_mux_pwr_modem_enabled_b,
> + msm_mux_pwr_nav_enabled_a,
> + msm_mux_pwr_nav_enabled_b,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_qdss_traceclk_a,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_qdss_tracectl_a,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qdss_tracedata_a,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_sd_write,
> + msm_mux_sdcard_det,
> + msm_mux_sec_mi2s,
> + msm_mux_sec_mi2s_mclk_a,
> + msm_mux_sec_mi2s_mclk_b,
> + msm_mux_sensor_rst,
> + msm_mux_smb_int,
> + msm_mux_ssbi_wtr1,
> + msm_mux_ts_resout,
> + msm_mux_ts_sample,
> + msm_mux_uim1_clk,
> + msm_mux_uim1_data,
> + msm_mux_uim1_present,
> + msm_mux_uim1_reset,
> + msm_mux_uim2_clk,
> + msm_mux_uim2_data,
> + msm_mux_uim2_present,
> + msm_mux_uim2_reset,
> + msm_mux_uim_batt,
> + msm_mux_us_emitter,
> + msm_mux_us_euro,
> + msm_mux_wcss_bt,
> + msm_mux_wcss_fm,
> + msm_mux_wcss_wlan,
> + msm_mux_wcss_wlan0,
> + msm_mux_wcss_wlan1,
> + msm_mux_wcss_wlan2,
> + msm_mux_webcam_rst,
> + msm_mux_webcam_standby,
> + msm_mux_wsa_io,
> + msm_mux_wsa_irq,
> + msm_mux_wsa_reset,
> + msm_mux__,
> +};
> +
> +#define MSM_PIN_FUNCTION(fname) \
> + [msm_mux_##fname] = {#fname, msm_mux_##fname}
> +
> +static const struct pinctrl_function msm8917_pinctrl_functions[] = {
> + MSM_PIN_FUNCTION(accel_int),
> + MSM_PIN_FUNCTION(adsp_ext),
> + MSM_PIN_FUNCTION(alsp_int),
> + MSM_PIN_FUNCTION(atest_bbrx0),
> + MSM_PIN_FUNCTION(atest_bbrx1),
> + MSM_PIN_FUNCTION(atest_char),
> + MSM_PIN_FUNCTION(atest_char0),
> + MSM_PIN_FUNCTION(atest_char1),
> + MSM_PIN_FUNCTION(atest_char2),
> + MSM_PIN_FUNCTION(atest_char3),
> + MSM_PIN_FUNCTION(atest_combodac_to_gpio_native),
> + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native),
> + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native),
> + MSM_PIN_FUNCTION(atest_tsens),
> + MSM_PIN_FUNCTION(atest_wlan0),
> + MSM_PIN_FUNCTION(atest_wlan1),
> + MSM_PIN_FUNCTION(audio_ref),
> + MSM_PIN_FUNCTION(audio_reset),
> + MSM_PIN_FUNCTION(bimc_dte0),
> + MSM_PIN_FUNCTION(bimc_dte1),
> + MSM_PIN_FUNCTION(blsp6_spi),
> + MSM_PIN_FUNCTION(blsp8_spi),
> + MSM_PIN_FUNCTION(blsp_i2c1),
> + MSM_PIN_FUNCTION(blsp_i2c2),
> + MSM_PIN_FUNCTION(blsp_i2c3),
> + MSM_PIN_FUNCTION(blsp_i2c4),
> + MSM_PIN_FUNCTION(blsp_i2c5),
> + MSM_PIN_FUNCTION(blsp_i2c6),
> + MSM_PIN_FUNCTION(blsp_i2c7),
> + MSM_PIN_FUNCTION(blsp_i2c8),
> + MSM_PIN_FUNCTION(blsp_spi1),
> + MSM_PIN_FUNCTION(blsp_spi2),
> + MSM_PIN_FUNCTION(blsp_spi3),
> + MSM_PIN_FUNCTION(blsp_spi4),
> + MSM_PIN_FUNCTION(blsp_spi5),
> + MSM_PIN_FUNCTION(blsp_spi6),
> + MSM_PIN_FUNCTION(blsp_spi7),
> + MSM_PIN_FUNCTION(blsp_spi8),
> + MSM_PIN_FUNCTION(blsp_uart1),
> + MSM_PIN_FUNCTION(blsp_uart2),
> + MSM_PIN_FUNCTION(blsp_uart3),
> + MSM_PIN_FUNCTION(blsp_uart4),
> + MSM_PIN_FUNCTION(blsp_uart5),
> + MSM_PIN_FUNCTION(blsp_uart6),
> + MSM_PIN_FUNCTION(blsp_uart7),
> + MSM_PIN_FUNCTION(blsp_uart8),
> + MSM_PIN_FUNCTION(cam0_ldo),
> + MSM_PIN_FUNCTION(cam1_rst),
> + MSM_PIN_FUNCTION(cam1_standby),
> + MSM_PIN_FUNCTION(cam2_rst),
> + MSM_PIN_FUNCTION(cam2_standby),
> + MSM_PIN_FUNCTION(cam_mclk),
> + MSM_PIN_FUNCTION(cci_async),
> + MSM_PIN_FUNCTION(cci_i2c),
> + MSM_PIN_FUNCTION(cci_timer0),
> + MSM_PIN_FUNCTION(cci_timer1),
> + MSM_PIN_FUNCTION(cdc_pdm0),
> + MSM_PIN_FUNCTION(codec_int1),
> + MSM_PIN_FUNCTION(codec_int2),
> + MSM_PIN_FUNCTION(codec_mad),
> + MSM_PIN_FUNCTION(coex_uart),
> + MSM_PIN_FUNCTION(cri_trng),
> + MSM_PIN_FUNCTION(cri_trng0),
> + MSM_PIN_FUNCTION(cri_trng1),
> + MSM_PIN_FUNCTION(dbg_out),
> + MSM_PIN_FUNCTION(dmic0_clk),
> + MSM_PIN_FUNCTION(dmic0_data),
> + MSM_PIN_FUNCTION(ebi_cdc),
> + MSM_PIN_FUNCTION(ebi_ch0),
> + MSM_PIN_FUNCTION(ext_lpass),
> + MSM_PIN_FUNCTION(forced_usb),
> + MSM_PIN_FUNCTION(fp_gpio),
> + MSM_PIN_FUNCTION(fp_int),
> + MSM_PIN_FUNCTION(gcc_gp1_clk_a),
> + MSM_PIN_FUNCTION(gcc_gp1_clk_b),
> + MSM_PIN_FUNCTION(gcc_gp2_clk_a),
> + MSM_PIN_FUNCTION(gcc_gp2_clk_b),
> + MSM_PIN_FUNCTION(gcc_gp3_clk_a),
> + MSM_PIN_FUNCTION(gcc_gp3_clk_b),
> + MSM_PIN_FUNCTION(gcc_plltest),
> + MSM_PIN_FUNCTION(gcc_tlmm),
> + MSM_PIN_FUNCTION(gpio),
> + MSM_PIN_FUNCTION(gsm0_tx),
> + MSM_PIN_FUNCTION(key_focus),
> + MSM_PIN_FUNCTION(key_snapshot),
> + MSM_PIN_FUNCTION(key_volp),
> + MSM_PIN_FUNCTION(ldo_en),
> + MSM_PIN_FUNCTION(ldo_update),
> + MSM_PIN_FUNCTION(lpass_slimbus),
> + MSM_PIN_FUNCTION(lpass_slimbus0),
> + MSM_PIN_FUNCTION(lpass_slimbus1),
> + MSM_PIN_FUNCTION(m_voc),
> + MSM_PIN_FUNCTION(mag_int),
> + MSM_PIN_FUNCTION(mdp_vsync),
> + MSM_PIN_FUNCTION(mipi_dsi0),
> + MSM_PIN_FUNCTION(modem_tsync),
> + MSM_PIN_FUNCTION(nav_pps),
> + MSM_PIN_FUNCTION(nav_pps_in_a),
> + MSM_PIN_FUNCTION(nav_pps_in_b),
> + MSM_PIN_FUNCTION(nav_tsync),
> + MSM_PIN_FUNCTION(nfc_pwr),
> + MSM_PIN_FUNCTION(ov_ldo),
> + MSM_PIN_FUNCTION(pa_indicator),
> + MSM_PIN_FUNCTION(pbs0),
> + MSM_PIN_FUNCTION(pbs1),
> + MSM_PIN_FUNCTION(pbs2),
> + MSM_PIN_FUNCTION(pri_mi2s),
> + MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
> + MSM_PIN_FUNCTION(pri_mi2s_mclk_b),
> + MSM_PIN_FUNCTION(pri_mi2s_ws),
> + MSM_PIN_FUNCTION(prng_rosc),
> + MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
> + MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
> + MSM_PIN_FUNCTION(pwr_modem_enabled_a),
> + MSM_PIN_FUNCTION(pwr_modem_enabled_b),
> + MSM_PIN_FUNCTION(pwr_nav_enabled_a),
> + MSM_PIN_FUNCTION(pwr_nav_enabled_b),
> + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
> + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
> + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
> + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
> + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
> + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
> + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
> + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
> + MSM_PIN_FUNCTION(qdss_traceclk_a),
> + MSM_PIN_FUNCTION(qdss_traceclk_b),
> + MSM_PIN_FUNCTION(qdss_tracectl_a),
> + MSM_PIN_FUNCTION(qdss_tracectl_b),
> + MSM_PIN_FUNCTION(qdss_tracedata_a),
> + MSM_PIN_FUNCTION(qdss_tracedata_b),
> + MSM_PIN_FUNCTION(sd_write),
> + MSM_PIN_FUNCTION(sdcard_det),
> + MSM_PIN_FUNCTION(sec_mi2s),
> + MSM_PIN_FUNCTION(sec_mi2s_mclk_a),
> + MSM_PIN_FUNCTION(sec_mi2s_mclk_b),
> + MSM_PIN_FUNCTION(sensor_rst),
> + MSM_PIN_FUNCTION(smb_int),
> + MSM_PIN_FUNCTION(ssbi_wtr1),
> + MSM_PIN_FUNCTION(ts_resout),
> + MSM_PIN_FUNCTION(ts_sample),
> + MSM_PIN_FUNCTION(uim1_clk),
> + MSM_PIN_FUNCTION(uim1_data),
> + MSM_PIN_FUNCTION(uim1_present),
> + MSM_PIN_FUNCTION(uim1_reset),
> + MSM_PIN_FUNCTION(uim2_clk),
> + MSM_PIN_FUNCTION(uim2_data),
> + MSM_PIN_FUNCTION(uim2_present),
> + MSM_PIN_FUNCTION(uim2_reset),
> + MSM_PIN_FUNCTION(uim_batt),
> + MSM_PIN_FUNCTION(us_emitter),
> + MSM_PIN_FUNCTION(us_euro),
> + MSM_PIN_FUNCTION(wcss_bt),
> + MSM_PIN_FUNCTION(wcss_fm),
> + MSM_PIN_FUNCTION(wcss_wlan),
> + MSM_PIN_FUNCTION(wcss_wlan0),
> + MSM_PIN_FUNCTION(wcss_wlan1),
> + MSM_PIN_FUNCTION(wcss_wlan2),
> + MSM_PIN_FUNCTION(webcam_rst),
> + MSM_PIN_FUNCTION(webcam_standby),
> + MSM_PIN_FUNCTION(wsa_io),
> + MSM_PIN_FUNCTION(wsa_irq),
> + MSM_PIN_FUNCTION(wsa_reset),
> +};
> +
> +static const msm_pin_function msm8917_pin_functions[] = {
> + PINGROUP(0, blsp_spi1, blsp_uart1, qdss_tracedata_b, _, _, _, _,
> + _, _),
> + PINGROUP(1, blsp_spi1, blsp_uart1, adsp_ext, _, _, _, _, _,
> + qdss_tracedata_b),
> + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, prng_rosc, _, _, _,
> + _, _),
> + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _),
> + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _,
> + atest_combodac_to_gpio_native, _, _, _, _),
> + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _),
> + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b,
> + qdss_tracedata_b, _, _, _, _),
> + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, pbs2, _,
> + qdss_tracedata_b, _, atest_gpsadc_dtest0_native, _),
> + PINGROUP(8, blsp_spi3, blsp_uart3, pbs0, _, _, _, _, _, _),
> + PINGROUP(9, blsp_spi3, blsp_uart3, pbs1, pwr_modem_enabled_b, _, _,
> + _, _, _),
> + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp2_clk_b, _, _,
> + _, _, _),
> + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp3_clk_b, _, _,
> + _, _, _),
> + PINGROUP(12, blsp_spi4, blsp_uart4, sec_mi2s, pwr_nav_enabled_b, _,
> + _, _, _, _),
> + PINGROUP(13, blsp_spi4, blsp_uart4, sec_mi2s, pwr_crypto_enabled_b, _,
> + _, _, _, _),
> + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
> + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
> + PINGROUP(16, blsp_spi5, blsp_uart5, _, _, _, _, qdss_traceclk_a,
> + _, atest_bbrx1),
> + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _,
> + atest_bbrx0, _, _, _),
> + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracectl_a, _,
> + atest_gpsadc_dtest1_native, _, _, _),
> + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _,
> + _, _, _, _),
> + PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, _, _, _,
> + qdss_tracectl_b),
> + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, _, _,
> + qdss_cti_trig_in_b0),
> + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _,
> + atest_wlan0, _, _, _),
> + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _,
> + atest_wlan1, _, _, _),
> + PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _),
> + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, _, _, _,
> + _, _, _),
> + PINGROUP(26, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _, _),
> + PINGROUP(27, cam_mclk, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(28, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _,
> + atest_combodac_to_gpio_native),
> + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, _, _,
> + qdss_tracedata_a, _),
> + PINGROUP(30, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(31, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(32, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(33, cci_timer0, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(34, cci_timer1, _, _, _, _, _, _, _, qdss_tracedata_a),
> + PINGROUP(35, pwr_nav_enabled_a, _, _, _, _, _, _, _,
> + qdss_tracedata_a),
> + PINGROUP(36, pwr_crypto_enabled_a, _, _, _, _, _, _, _,
> + qdss_tracedata_a),
> + PINGROUP(37, _, _, _, _, _, qdss_cti_trig_out_b1, _, _, _),
> + PINGROUP(38, _, qdss_tracedata_a, _, _, _, _, _, _, _),
> + PINGROUP(39, cci_async, _, _, _, _, _, qdss_tracedata_a, _,
> + atest_combodac_to_gpio_native),
> + PINGROUP(40, _, _, _, _, qdss_tracedata_a, _,
> + atest_combodac_to_gpio_native, _, _),
> + PINGROUP(41, sd_write, _, _, _, _, _, _, _,
> + atest_combodac_to_gpio_native),
> + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _,
> + atest_combodac_to_gpio_native, _, _, _, _, _),
> + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _,
> + atest_combodac_to_gpio_native, _, _, _, _, _),
> + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _,
> + atest_combodac_to_gpio_native, _, _, _, _, _),
> + PINGROUP(45, _, _, atest_combodac_to_gpio_native, _, _, _, _, _,
> + _),
> + PINGROUP(46, _, _, atest_combodac_to_gpio_native, _, _, _, _, _,
> + _),
> + PINGROUP(47, blsp6_spi, _, qdss_tracedata_b, _,
> + atest_combodac_to_gpio_native, _, _, _, _),
> + PINGROUP(48, _, qdss_cti_trig_in_b1, _,
> + atest_combodac_to_gpio_native, _, _, _, _, _),
> + PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _),
> + PINGROUP(50, qdss_tracedata_a, _, _, _, _, _, _, _, _),
> + PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _),
> + PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _),
> + PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _),
> + PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _),
> + PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _),
> + PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _),
> + PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _),
> + PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _),
> + PINGROUP(59, _, _, _, _, _, _, _, _, _),
> + PINGROUP(60, _, _, _, _, _, _, _, _, _),
> + PINGROUP(61, _, _, _, _, _, _, _, _, _),
> + PINGROUP(62, _, _, _, _, _, _, _, _, _),
> + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _),
> + PINGROUP(64, _, _, _, _, _, _, _, _, _),
> + PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _),
> + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _,
> + _, _, _),
> + PINGROUP(67, atest_char1, ebi_cdc, _, atest_combodac_to_gpio_native,
> + _, _, _, _, _),
> + PINGROUP(68, atest_char0, _, _, _, _, _, _, _, _),
> + PINGROUP(69, audio_ref, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _,
> + _, _),
> + PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _),
> + PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _),
> + PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _),
> + PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _),
> + PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _),
> + PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _),
> + PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _),
> + PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _),
> + PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _),
> + PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _),
> + PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _),
> + PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _),
> + PINGROUP(82, wcss_fm, cri_trng, _, _, _, _, _, _, _),
> + PINGROUP(83, wcss_bt, cri_trng1, _, _, _, _, _, _, _),
> + PINGROUP(84, wcss_bt, cri_trng0, _, _, _, _, _, _, _),
> + PINGROUP(85, pri_mi2s, blsp_spi7, blsp_uart7, _, _, _, _, _, _),
> + PINGROUP(86, pri_mi2s, blsp_spi7, blsp_uart7, qdss_tracedata_b, _, _,
> + _, _, _),
> + PINGROUP(87, pri_mi2s_ws, blsp_spi7, blsp_uart7, blsp_i2c7,
> + qdss_tracedata_b, gcc_tlmm, _, _, _),
> + PINGROUP(88, pri_mi2s, blsp_spi7, blsp_uart7, blsp_i2c7, _, _, _,
> + _, _),
> + PINGROUP(89, dmic0_clk, _, _, _, _, _, _, _, _),
> + PINGROUP(90, dmic0_data, _, _, _, _, _, _, _, _),
> + PINGROUP(91, _, _, _, _, _, qdss_cti_trig_in_a1, _, _, _),
> + PINGROUP(92, _, _, _, _, _, qdss_tracedata_b, _, _, _),
> + PINGROUP(93, _, _, _, _, _, _, _, _, _),
> + PINGROUP(94, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _),
> + PINGROUP(95, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _),
> + PINGROUP(96, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _),
> + PINGROUP(97, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _),
> + PINGROUP(98, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _,
> + _, _),
> + PINGROUP(99, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _,
> + _, _),
> + PINGROUP(100, _, _, _, _, _, _, _, _, _),
> + PINGROUP(101, _, _, _, _, _, _, _, _, _),
> + PINGROUP(102, _, _, _, _, _, _, _, _, _),
> + PINGROUP(103, _, _, _, _, _, _, _, _, _),
> + PINGROUP(104, _, _, _, _, _, _, _, _, _),
> + PINGROUP(105, _, _, _, _, _, _, _, _, _),
> + PINGROUP(106, _, _, _, _, _, _, _, _, _),
> + PINGROUP(107, _, _, _, _, _, _, _, _, _),
> + PINGROUP(108, _, _, _, _, _, _, _, _, _),
> + PINGROUP(109, _, _, _, _, _, _, _, _, _),
> + PINGROUP(110, _, _, _, _, _, _, _, _, _),
> + PINGROUP(111, _, _, _, _, _, _, _, _, _),
> + PINGROUP(112, _, _, _, _, _, _, _, _, _),
> + PINGROUP(113, _, _, _, _, _, _, _, _, _),
> + PINGROUP(114, _, _, _, _, _, _, _, _, _),
> + PINGROUP(115, _, _, nav_pps_in_a, _, atest_combodac_to_gpio_native,
> + _, _, _, _),
> + PINGROUP(116, _, pa_indicator, _, _, _, _, _, _, _),
> + PINGROUP(117, _, modem_tsync, nav_tsync, nav_pps_in_b, nav_pps, _,
> + _, _, _),
> + PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _),
> + PINGROUP(119, gsm0_tx, _, ebi_cdc, _, _, _, _, _, _),
> + PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _),
> + PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _),
> + PINGROUP(122, _, ssbi_wtr1, _, _, bimc_dte1, _, _, _, _),
> + PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _),
> + PINGROUP(124, coex_uart, _, _, _, _, _, _, _, _),
> + PINGROUP(125, _, _, _, _, _, _, _, _, _),
> + PINGROUP(126, _, _, _, _, _, _, _, _, _),
> + PINGROUP(127, coex_uart, _, _, _, _, _, _, _, _),
> + PINGROUP(128, _, _, _, _, _, _, _, _, _),
> + PINGROUP(129, _, _, _, _, _, _, _, _, _),
> + PINGROUP(130, blsp8_spi, _, _, _, _, _, _, _, _),
> + PINGROUP(131, _, _, _, _, _, _, _, _, _),
> + PINGROUP(132, qdss_cti_trig_out_a0, _, _, _, _, _, _, _, _),
> + PINGROUP(133, qdss_cti_trig_out_a1, _, _, _, _, _, _, _, _)
> +};
> +
> +static const struct msm_special_pin_data msm8917_special_pins_data[] = {
> + SDC_PINGROUP("sdc1_clk", 0x10a000, 13, 6),
> + SDC_PINGROUP("sdc1_cmd", 0x10a000, 11, 3),
> + SDC_PINGROUP("sdc1_data", 0x10a000, 9, 0),
> + SDC_PINGROUP("sdc1_rclk", 0x10a000, 15, 0),
> + SDC_PINGROUP("sdc2_clk", 0x109000, 14, 6),
> + SDC_PINGROUP("sdc2_cmd", 0x109000, 11, 3),
> + SDC_PINGROUP("sdc2_data", 0x109000, 9, 0),
> + SDC_PINGROUP("qdsd_clk", 0x19c000, 3, 0),
> + SDC_PINGROUP("qdsd_cmd", 0x19c000, 8, 5),
> + SDC_PINGROUP("qdsd_data0", 0x19c000, 13, 10),
> + SDC_PINGROUP("qdsd_data1", 0x19c000, 18, 15),
> + SDC_PINGROUP("qdsd_data2", 0x19c000, 23, 20),
> + SDC_PINGROUP("qdsd_data3", 0x19c000, 28, 25),
> +};
> +
> +#define N_GPIO ARRAY_SIZE(msm8917_pin_functions)
> +#define N_SPECIAL ARRAY_SIZE(msm8917_special_pins_data)
> +
> +static int msm8917_get_function_mux(unsigned int pin, unsigned int selector)
> +{
> + unsigned int i;
> + const msm_pin_function *func;
> +
> + if (pin >= N_GPIO)
> + return -EINVAL;
> +
> + func = msm8917_pin_functions + pin;
> +
> + for (i = 0; i < 10; i++)
> + if ((*func)[i] == selector)
> + return i;
> +
> + pr_err("Can't find requested function for pin %u\n", pin);
> +
> + return -EINVAL;
> +}
> +
> +static const char *msm8917_get_function_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + return msm8917_pinctrl_functions[selector].name;
> +}
> +
> +static const char *msm8917_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + if (selector >= N_GPIO)
> + return msm8917_special_pins_data[selector - N_GPIO].name;
Can we have an error check in case selector >= N_GPIO + N_SPECIAL?
Regards,
Balaji
> +
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> + return pin_name;
> +}
> +
> +static const struct msm_pinctrl_data msm8917_data = {
> + .pin_data = {
> + .pin_count = N_GPIO + N_SPECIAL,
> + .special_pins_start = N_GPIO,
> + .special_pins_data = msm8917_special_pins_data,
> + },
> + .functions_count = ARRAY_SIZE(msm8917_pinctrl_functions),
> + .get_function_name = msm8917_get_function_name,
> + .get_function_mux = msm8917_get_function_mux,
> + .get_pin_name = msm8917_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> + {
> + .compatible = "qcom,msm8917-pinctrl",
> + .data = (ulong)&msm8917_data
> + },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_msm8917) = {
> + .name = "pinctrl_msm8917",
> + .id = UCLASS_NOP,
> + .of_match = msm_pinctrl_ids,
> + .bind = msm_pinctrl_bind,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit
2026-09-10 9:41 ` [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit Reza Kurniawan
@ 2026-09-11 6:18 ` Balaji Selvanathan
0 siblings, 0 replies; 9+ messages in thread
From: Balaji Selvanathan @ 2026-09-11 6:18 UTC (permalink / raw)
To: Reza Kurniawan, u-boot
Cc: Casey Connolly, Lukasz Majewski, Neil Armstrong, Sumit Garg,
Tom Rini, u-boot-qcom
Hi Reza,
On 9/10/2026 3:11 PM, Reza Kurniawan wrote:
> Some SoCs such as MSM8917 poll its GDSC power domains by reading GDSCR
> directly, as opposed to GDSCR + CFG_GDSCR_OFFSET.
> Add a poll_gdscr flag to struct qcom_power_map to facilitate those SoCs.
>
> Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>
> drivers/clk/qcom/clock-qcom.c | 24 +++++++++++++-----------
> drivers/clk/qcom/clock-qcom.h | 1 +
> 2 files changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 6b46d9db7..754ff4ff4 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -505,9 +505,9 @@ U_BOOT_DRIVER(qcom_reset) = {
> static int qcom_power_set(struct power_domain *pwr, bool on)
> {
> struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
> - void __iomem *base = dev_get_priv(pwr->dev);
> + void __iomem *base = dev_get_priv(pwr->dev), *poll_addr;
> const struct qcom_power_map *map;
> - u32 value;
> + u32 value, mask;
> int ret;
>
> if (pwr->id >= data->num_power_domains)
> @@ -527,19 +527,21 @@ static int qcom_power_set(struct power_domain *pwr, bool on)
>
> writel(value, base + map->reg);
>
> - if (on)
> - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
> + poll_addr = base + map->reg;
> + if (map->poll_gdscr) {
> + /* Some SOCs such as MSM8917 poll at GDSCR */
> + ret = readl_poll_timeout(poll_addr,
> value,
> - (value & GDSC_POWER_UP_COMPLETE) ||
> - (value & GDSC_PWR_ON_MASK),
> + (!!(value & GDSC_PWR_ON_MASK) == on),
> GDSC_STATUS_POLL_TIMEOUT_US);
> -
> - else
> - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
> + } else {
> + mask = on ? GDSC_POWER_UP_COMPLETE : GDSC_POWER_DOWN_COMPLETE;
> + ret = readl_poll_timeout(poll_addr + CFG_GDSCR_OFFSET,
> value,
> - (value & GDSC_POWER_DOWN_COMPLETE) ||
> - !(value & GDSC_PWR_ON_MASK),
> + (value & mask) ||
> + !!(value & GDSC_PWR_ON_MASK) == on,
> GDSC_STATUS_POLL_TIMEOUT_US);
> + }
>
> if (ret == -ETIMEDOUT)
> printf("WARNING: GDSC %lu is stuck during power on/off\n",
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 3a4550d85..0b514cc1f 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -76,6 +76,7 @@ struct qcom_reset_map {
>
> struct qcom_power_map {
> unsigned int reg;
> + bool poll_gdscr;
> };
>
> struct clk;
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917
2026-09-10 9:41 ` [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917 Reza Kurniawan
@ 2026-09-11 6:29 ` Balaji Selvanathan
0 siblings, 0 replies; 9+ messages in thread
From: Balaji Selvanathan @ 2026-09-11 6:29 UTC (permalink / raw)
To: Reza Kurniawan, u-boot
Cc: Casey Connolly, Lukasz Majewski, Neil Armstrong, Sumit Garg,
Tom Rini, u-boot-qcom
Hi Reza,
On 9/10/2026 3:11 PM, Reza Kurniawan wrote:
> Add Global Clock Controller (GCC) driver for MSM8917 to manage clocks,
> resets, and gdscs. This driver includes the essential clocks and
> resets for U-Boot to function.
Same here, pls mention kernel commit.
>
> Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
> ---
>
> configs/qcom_defconfig | 1 +
> drivers/clk/qcom/Kconfig | 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-msm8917.c | 196 +++++++++++++++++++++++++++++++
> 4 files changed, 206 insertions(+)
> create mode 100644 drivers/clk/qcom/clock-msm8917.c
>
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index 7d4a2b589..59cad58a9 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -57,6 +57,7 @@ CONFIG_CLK_STUB=y
> CONFIG_CLK_QCOM_APQ8016=y
> CONFIG_CLK_QCOM_APQ8096=y
> CONFIG_CLK_QCOM_MILOS=y
> +CONFIG_CLK_QCOM_MSM8917=y
> CONFIG_CLK_QCOM_QCM2290=y
> CONFIG_CLK_QCOM_QCS404=y
> CONFIG_CLK_QCOM_QCS615=y
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 95b650831..d8469ad5f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -55,6 +55,14 @@ config CLK_QCOM_MILOS
> on the Snapdragon Milos SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_MSM8917
> + bool "Qualcomm MSM8917 GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon MSM8917 SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> config CLK_QCOM_QCM2290
> bool "Qualcomm QCM2290 GCC"
> select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 1adca029b..6478ec322 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o
> obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
> obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o
> +obj-$(CONFIG_CLK_QCOM_MSM8917) += clock-msm8917.o
> obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
> diff --git a/drivers/clk/qcom/clock-msm8917.c b/drivers/clk/qcom/clock-msm8917.c
> new file mode 100644
> index 000000000..2cb1fa961
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-msm8917.c
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier: GPL-2.0+
This should be GPL-2.0-only i guess
> +/*
> + * Clock drivers for Qualcomm MSM8917
> + *
> + * (C) Copyright 2026 Reza Kurniawan <imkyufie@gmail.com>
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm/device.h>
> +#include <linux/kernel.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8917.h>
> +
> +#include "clock-qcom.h"
> +
> +#define CFG_CLK_SRC_GPLL4_SDCC1 (2 << 8)
> +
> +static const struct gate_clk msm8917_clks[] = {
> + GATE_CLK_POLLED(GCC_BLSP1_UART1_APPS_CLK, 0x0203c, BIT(0), 0x0203c),
> + GATE_CLK_POLLED(GCC_BLSP1_UART2_APPS_CLK, 0x0302c, BIT(0), 0x0302c),
> + GATE_CLK_POLLED(GCC_BLSP2_UART1_APPS_CLK, 0x0c03c, BIT(0), 0x0c03c),
> + GATE_CLK_POLLED(GCC_BLSP2_UART2_APPS_CLK, 0x0d02c, BIT(0), 0x0d02c),
> + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c),
> + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018),
> + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c),
> + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018),
> + GATE_CLK_POLLED(GCC_USB_HS_PHY_CFG_AHB_CLK, 0x41030, BIT(0), 0x41030),
> + GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008),
> + GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004),
> + GATE_CLK_POLLED(GCC_USB2A_PHY_SLEEP_CLK, 0x4102c, BIT(0), 0x4102c)
> +};
> +
> +static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
> + F(3686400, CFG_CLK_SRC_GPLL0, 1, 72, 15625),
> + F(7372800, CFG_CLK_SRC_GPLL0, 1, 144, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0, 1, 288, 15625),
> + F(16000000, CFG_CLK_SRC_GPLL0, 10, 1, 5),
> + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(24000000, CFG_CLK_SRC_GPLL0, 1, 3, 100),
> + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
> + F(32000000, CFG_CLK_SRC_GPLL0, 1, 1, 25),
> + F(40000000, CFG_CLK_SRC_GPLL0, 1, 1, 20),
> + F(46400000, CFG_CLK_SRC_GPLL0, 1, 29, 500),
> + F(48000000, CFG_CLK_SRC_GPLL0, 1, 3, 50),
> + F(51200000, CFG_CLK_SRC_GPLL0, 1, 8, 125),
> + F(56000000, CFG_CLK_SRC_GPLL0, 1, 7, 100),
> + F(58982400, CFG_CLK_SRC_GPLL0, 1, 1152, 15625),
> + F(60000000, CFG_CLK_SRC_GPLL0, 1, 3, 40),
> + F(64000000, CFG_CLK_SRC_GPLL0, 1, 2, 25),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
> + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4),
> + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
> + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0),
> + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
> + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(192000000, CFG_CLK_SRC_GPLL4_SDCC1, 6, 0, 0),
> + F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
> + F(384000000, CFG_CLK_SRC_GPLL4_SDCC1, 3, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
> + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
> + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4),
> + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2),
> + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0),
> + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
> + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
> + F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0),
> + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
> + F(133330000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + F(177780000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + { }
> +};
> +
> +static int msm8917_enable(struct clk *clk)
> +{
> + struct msm_clk_priv *priv;
> +
> + priv = dev_get_priv(clk->dev);
> + return qcom_gate_clk_en(priv, clk->id);
> +}
> +
> +static ulong msm8917_uart_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> + u32 cmd_rcgr;
> +
> + switch (clk->id) {
> + case GCC_BLSP1_UART1_APPS_CLK:
> + cmd_rcgr = 0x02044;
> + break;
> + case GCC_BLSP1_UART2_APPS_CLK:
> + cmd_rcgr = 0x03034;
> + break;
> + case GCC_BLSP2_UART1_APPS_CLK:
> + cmd_rcgr = 0x0c044;
> + break;
> + case GCC_BLSP2_UART2_APPS_CLK:
> + cmd_rcgr = 0x0d034;
> + break;
> + default:
> + return 0;
> + }
> +
> + freq = qcom_find_freq(ftbl_blsp_uart_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, cmd_rcgr,
> + freq->pre_div, freq->m, freq->n, freq->src, 16);
> +
> + return freq->freq;
> +}
> +
> +static ulong msm8917_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + switch (clk->id) {
> + case GCC_BLSP1_UART1_APPS_CLK:
> + case GCC_BLSP1_UART2_APPS_CLK:
> + case GCC_BLSP2_UART1_APPS_CLK:
> + case GCC_BLSP2_UART2_APPS_CLK:
> + return msm8917_uart_set_rate(clk, rate);
> + case GCC_SDCC1_APPS_CLK:
> + freq = qcom_find_freq(ftbl_sdcc1_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x42004,
Can we have macros for the addresses? Same for below.
Regards,
Balaji
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_SDCC2_APPS_CLK:
> + freq = qcom_find_freq(ftbl_sdcc2_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x43004,
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_USB_HS_SYSTEM_CLK:
> + freq = qcom_find_freq(ftbl_usb_hs_system_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x41010,
> + freq->pre_div, freq->m, freq->n, freq->src, 0);
> + return freq->freq;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static const struct qcom_reset_map msm8917_resets[] = {
> + [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
> + [GCC_MSS_BCR] = { 0x71000 },
> + [GCC_QUSB2_PHY_BCR] = { 0x4103c },
> + [GCC_USB_HS_BCR] = { 0x41000 },
> + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
> + [GCC_MDSS_BCR] = { 0x4d074 },
> +};
> +
> +static const struct qcom_power_map msm8917_gdscs[] = {
> + [MDSS_GDSC] = { 0x4d078, true },
> +};
> +
> +static struct msm_clk_data msm8917_gcc_data = {
> + .resets = msm8917_resets,
> + .num_resets = ARRAY_SIZE(msm8917_resets),
> + .clks = msm8917_clks,
> + .num_clks = ARRAY_SIZE(msm8917_clks),
> + .power_domains = msm8917_gdscs,
> + .num_power_domains = ARRAY_SIZE(msm8917_gdscs),
> +
> + .enable = msm8917_enable,
> + .set_rate = msm8917_set_rate,
> +};
> +
> +static const struct udevice_id gcc_msm8917_of_match[] = {
> + {
> + .compatible = "qcom,gcc-msm8917",
> + .data = (ulong)&msm8917_gcc_data,
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(gcc_msm8917) = {
> + .name = "gcc_msm8917",
> + .id = UCLASS_NOP,
> + .of_match = gcc_msm8917_of_match,
> + .bind = qcom_cc_bind,
> + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-09-11 6:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-10 9:41 [PATCH 0/4] Add preliminary support for MSM8917 Reza Kurniawan
2026-09-10 9:41 ` [PATCH 1/4] mach-snapdragon: Carve out reserved memory at init " Reza Kurniawan
2026-09-11 5:48 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 2/4] pinctrl: qcom: Add pinctrl driver " Reza Kurniawan
2026-09-11 6:05 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit Reza Kurniawan
2026-09-11 6:18 ` Balaji Selvanathan
2026-09-10 9:41 ` [PATCH 4/4] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917 Reza Kurniawan
2026-09-11 6:29 ` Balaji Selvanathan
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