From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Paul Walmsley <pjw@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header
Date: Thu, 10 Sep 2026 03:03:56 -0700 [thread overview]
Message-ID: <20260910100357.130134-22-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260910100357.130134-1-changhuang.liang@starfivetech.com>
Add the pad number definitions used by the JHB100 pinctrl device tree
nodes. The pad numbers are a property of the SoC pin controllers and are
only consumed by the StarFive JHB100 device trees.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 1 +
.../dts/starfive/starfive,jhb100-pinctrl.h | 247 ++++++++++++++++++
2 files changed, 248 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 08201752d14a..f1a867babf85 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25903,6 +25903,7 @@ M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/starfive/jhb100*
+F: arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
M: Changhuang Liang <changhuang.liang@starfivetech.com>
diff --git a/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
new file mode 100644
index 000000000000..a645ddc836ff
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+
+/* sys0 pad numbers */
+#define PADNUM_SYS0_GPIO_A0 0
+#define PADNUM_SYS0_GPIO_A1 1
+#define PADNUM_SYS0_GPIO_A2 2
+#define PADNUM_SYS0_GPIO_A3 3
+
+/* sys0h pad numbers */
+#define PADNUM_SYS0H_GPIO_A4 0
+#define PADNUM_SYS0H_GPIO_A5 1
+#define PADNUM_SYS0H_GPIO_A6 2
+#define PADNUM_SYS0H_GPIO_A7 3
+#define PADNUM_SYS0H_GPIO_A8 4
+#define PADNUM_SYS0H_GPIO_A9 5
+#define PADNUM_SYS0H_GPIO_A10 6
+#define PADNUM_SYS0H_GPIO_A11 7
+#define PADNUM_SYS0H_GPIO_A12 8
+#define PADNUM_SYS0H_GPIO_A13 9
+#define PADNUM_SYS0H_GPIO_A14 10
+#define PADNUM_SYS0H_GPIO_A15 11
+
+/* sys1 pad numbers */
+#define PADNUM_SYS1_GPIO_A16 0
+#define PADNUM_SYS1_GPIO_A17 1
+#define PADNUM_SYS1_GPIO_A18 2
+#define PADNUM_SYS1_GPIO_A19 3
+#define PADNUM_SYS1_GPIO_A20 4
+#define PADNUM_SYS1_GPIO_A21 5
+#define PADNUM_SYS1_GPIO_A22 6
+#define PADNUM_SYS1_GPIO_A23 7
+
+/* sys2 pad numbers */
+#define PADNUM_SYS2_GPIO_A24 0
+#define PADNUM_SYS2_GPIO_A25 1
+#define PADNUM_SYS2_GPIO_A26 2
+#define PADNUM_SYS2_GPIO_A27 3
+#define PADNUM_SYS2_GPIO_A28 4
+#define PADNUM_SYS2_GPIO_A29 5
+#define PADNUM_SYS2_GPIO_A30 6
+#define PADNUM_SYS2_GPIO_A31 7
+#define PADNUM_SYS2_GPIO_A32 8
+#define PADNUM_SYS2_GPIO_A33 9
+#define PADNUM_SYS2_GPIO_A34 10
+#define PADNUM_SYS2_GPIO_A35 11
+#define PADNUM_SYS2_GPIO_A36 12
+#define PADNUM_SYS2_GPIO_A37 13
+#define PADNUM_SYS2_GPIO_A38 14
+#define PADNUM_SYS2_GPIO_A39 15
+#define PADNUM_SYS2_GPIO_A40 16
+#define PADNUM_SYS2_GPIO_A41 17
+#define PADNUM_SYS2_GPIO_A42 18
+#define PADNUM_SYS2_GPIO_A43 19
+#define PADNUM_SYS2_GPIO_A44 20
+#define PADNUM_SYS2_GPIO_A45 21
+#define PADNUM_SYS2_GPIO_A46 22
+#define PADNUM_SYS2_GPIO_A47 23
+#define PADNUM_SYS2_GPIO_A48 24
+#define PADNUM_SYS2_GPIO_A49 25
+#define PADNUM_SYS2_GPIO_A50 26
+#define PADNUM_SYS2_GPIO_A51 27
+#define PADNUM_SYS2_GPIO_A52 28
+#define PADNUM_SYS2_GPIO_A53 29
+#define PADNUM_SYS2_GPIO_A54 30
+#define PADNUM_SYS2_GPIO_A55 31
+#define PADNUM_SYS2_GPIO_A56 32
+#define PADNUM_SYS2_GPIO_A57 33
+#define PADNUM_SYS2_GPIO_A58 34
+#define PADNUM_SYS2_GPIO_A59 35
+#define PADNUM_SYS2_GPIO_A60 36
+
+/* per0 pad numbers */
+#define PADNUM_PER0_GPIO_B0 0
+#define PADNUM_PER0_GPIO_B1 1
+#define PADNUM_PER0_GPIO_B2 2
+#define PADNUM_PER0_GPIO_B3 3
+#define PADNUM_PER0_GPIO_B4 4
+#define PADNUM_PER0_GPIO_B5 5
+#define PADNUM_PER0_GPIO_B6 6
+#define PADNUM_PER0_GPIO_B7 7
+#define PADNUM_PER0_GPIO_B8 8
+#define PADNUM_PER0_GPIO_B9 9
+#define PADNUM_PER0_GPIO_B10 10
+#define PADNUM_PER0_GPIO_B11 11
+#define PADNUM_PER0_GPIO_B12 12
+#define PADNUM_PER0_GPIO_B13 13
+#define PADNUM_PER0_GPIO_B14 14
+#define PADNUM_PER0_GPIO_B15 15
+#define PADNUM_PER0_GPIO_B16 16
+#define PADNUM_PER0_GPIO_B17 17
+#define PADNUM_PER0_GPIO_B18 18
+#define PADNUM_PER0_GPIO_B19 19
+#define PADNUM_PER0_GPIO_B20 20
+#define PADNUM_PER0_GPIO_B21 21
+#define PADNUM_PER0_GPIO_B22 22
+#define PADNUM_PER0_GPIO_B23 23
+#define PADNUM_PER0_GPIO_B24 24
+#define PADNUM_PER0_GPIO_B25 25
+#define PADNUM_PER0_GPIO_B26 26
+#define PADNUM_PER0_GPIO_B27 27
+#define PADNUM_PER0_GPIO_B28 28
+#define PADNUM_PER0_GPIO_B29 29
+#define PADNUM_PER0_GPIO_B30 30
+#define PADNUM_PER0_GPIO_B31 31
+#define PADNUM_PER0_GPIO_B32 32
+#define PADNUM_PER0_GPIO_B33 33
+#define PADNUM_PER0_GPIO_B34 34
+#define PADNUM_PER0_GPIO_B35 35
+#define PADNUM_PER0_GPIO_B36 36
+#define PADNUM_PER0_GPIO_B37 37
+#define PADNUM_PER0_GPIO_B38 38
+#define PADNUM_PER0_GPIO_B39 39
+#define PADNUM_PER0_GPIO_B40 40
+#define PADNUM_PER0_GPIO_B41 41
+#define PADNUM_PER0_GPIO_B42 42
+#define PADNUM_PER0_GPIO_B43 43
+#define PADNUM_PER0_GPIO_B44 44
+#define PADNUM_PER0_GPIO_B45 45
+#define PADNUM_PER0_GPIO_B46 46
+#define PADNUM_PER0_GPIO_B47 47
+#define PADNUM_PER0_GPIO_B48 48
+#define PADNUM_PER0_GPIO_B49 49
+#define PADNUM_PER0_GPIO_B50 50
+#define PADNUM_PER0_GPIO_B51 51
+#define PADNUM_PER0_GPIO_B52 52
+#define PADNUM_PER0_GPIO_B53 53
+#define PADNUM_PER0_GPIO_B54 54
+#define PADNUM_PER0_GPIO_B55 55
+#define PADNUM_PER0_GPIO_B56 56
+#define PADNUM_PER0_GPIO_B57 57
+#define PADNUM_PER0_GPIO_B58 58
+#define PADNUM_PER0_GPIO_B59 59
+
+/* per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C28 28
+#define PADNUM_PER1_GPIO_C29 29
+#define PADNUM_PER1_GPIO_C30 30
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C32 32
+#define PADNUM_PER1_GPIO_C33 33
+#define PADNUM_PER1_GPIO_C34 34
+#define PADNUM_PER1_GPIO_C35 35
+
+/* per2 pad numbers */
+#define PADNUM_PER2_GPIO_D0 0
+#define PADNUM_PER2_GPIO_D1 1
+#define PADNUM_PER2_GPIO_D2 2
+#define PADNUM_PER2_GPIO_D3 3
+#define PADNUM_PER2_GPIO_D4 4
+#define PADNUM_PER2_GPIO_D5 5
+#define PADNUM_PER2_GPIO_D6 6
+#define PADNUM_PER2_GPIO_D7 7
+#define PADNUM_PER2_GPIO_D8 8
+#define PADNUM_PER2_GPIO_D9 9
+#define PADNUM_PER2_GPIO_D10 10
+#define PADNUM_PER2_GPIO_D11 11
+#define PADNUM_PER2_GPIO_D12 12
+#define PADNUM_PER2_GPIO_D13 13
+#define PADNUM_PER2_GPIO_D14 14
+#define PADNUM_PER2_GPIO_D15 15
+#define PADNUM_PER2_GPIO_D16 16
+#define PADNUM_PER2_GPIO_D17 17
+#define PADNUM_PER2_GPIO_D18 18
+#define PADNUM_PER2_GPIO_D19 19
+#define PADNUM_PER2_GPIO_D20 20
+#define PADNUM_PER2_GPIO_D21 21
+#define PADNUM_PER2_GPIO_D22 22
+#define PADNUM_PER2_GPIO_D23 23
+#define PADNUM_PER2_GPIO_D24 24
+#define PADNUM_PER2_GPIO_D25 25
+#define PADNUM_PER2_GPIO_D26 26
+#define PADNUM_PER2_GPIO_D27 27
+#define PADNUM_PER2_GPIO_D28 28
+#define PADNUM_PER2_GPIO_D29 29
+#define PADNUM_PER2_GPIO_D30 30
+
+/* per2pok pad numbers */
+#define PADNUM_PER2POK_GPIO_D31 0
+#define PADNUM_PER2POK_GPIO_D32 1
+#define PADNUM_PER2POK_GPIO_D33 2
+#define PADNUM_PER2POK_GPIO_D34 3
+#define PADNUM_PER2POK_GPIO_D35 4
+#define PADNUM_PER2POK_GPIO_D36 5
+#define PADNUM_PER2POK_GPIO_D37 6
+#define PADNUM_PER2POK_GPIO_D38 7
+#define PADNUM_PER2POK_GPIO_D39 8
+#define PADNUM_PER2POK_GPIO_D40 9
+#define PADNUM_PER2POK_GPIO_D41 10
+#define PADNUM_PER2POK_GPIO_D42 11
+#define PADNUM_PER2POK_GPIO_D43 12
+#define PADNUM_PER2POK_GPIO_D44 13
+#define PADNUM_PER2POK_GPIO_D45 14
+#define PADNUM_PER2POK_GPIO_D46 15
+#define PADNUM_PER2POK_GPIO_D47 16
+#define PADNUM_PER2POK_GPIO_D48 17
+
+/* per3 pad numbers */
+#define PADNUM_PER3_GPIO_E0 0
+#define PADNUM_PER3_GPIO_E1 1
+#define PADNUM_PER3_GPIO_E2 2
+#define PADNUM_PER3_GPIO_E3 3
+#define PADNUM_PER3_GPIO_E4 4
+#define PADNUM_PER3_GPIO_E5 5
+#define PADNUM_PER3_GPIO_E6 6
+#define PADNUM_PER3_GPIO_E7 7
+#define PADNUM_PER3_GPIO_E8 8
+#define PADNUM_PER3_GPIO_E9 9
+#define PADNUM_PER3_GPIO_E10 10
+#define PADNUM_PER3_GPIO_E11 11
+
+#endif
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Paul Walmsley <pjw@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header
Date: Thu, 10 Sep 2026 03:03:56 -0700 [thread overview]
Message-ID: <20260910100357.130134-22-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260910100357.130134-1-changhuang.liang@starfivetech.com>
Add the pad number definitions used by the JHB100 pinctrl device tree
nodes. The pad numbers are a property of the SoC pin controllers and are
only consumed by the StarFive JHB100 device trees.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 1 +
.../dts/starfive/starfive,jhb100-pinctrl.h | 247 ++++++++++++++++++
2 files changed, 248 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 08201752d14a..f1a867babf85 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25903,6 +25903,7 @@ M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/starfive/jhb100*
+F: arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
M: Changhuang Liang <changhuang.liang@starfivetech.com>
diff --git a/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
new file mode 100644
index 000000000000..a645ddc836ff
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+
+/* sys0 pad numbers */
+#define PADNUM_SYS0_GPIO_A0 0
+#define PADNUM_SYS0_GPIO_A1 1
+#define PADNUM_SYS0_GPIO_A2 2
+#define PADNUM_SYS0_GPIO_A3 3
+
+/* sys0h pad numbers */
+#define PADNUM_SYS0H_GPIO_A4 0
+#define PADNUM_SYS0H_GPIO_A5 1
+#define PADNUM_SYS0H_GPIO_A6 2
+#define PADNUM_SYS0H_GPIO_A7 3
+#define PADNUM_SYS0H_GPIO_A8 4
+#define PADNUM_SYS0H_GPIO_A9 5
+#define PADNUM_SYS0H_GPIO_A10 6
+#define PADNUM_SYS0H_GPIO_A11 7
+#define PADNUM_SYS0H_GPIO_A12 8
+#define PADNUM_SYS0H_GPIO_A13 9
+#define PADNUM_SYS0H_GPIO_A14 10
+#define PADNUM_SYS0H_GPIO_A15 11
+
+/* sys1 pad numbers */
+#define PADNUM_SYS1_GPIO_A16 0
+#define PADNUM_SYS1_GPIO_A17 1
+#define PADNUM_SYS1_GPIO_A18 2
+#define PADNUM_SYS1_GPIO_A19 3
+#define PADNUM_SYS1_GPIO_A20 4
+#define PADNUM_SYS1_GPIO_A21 5
+#define PADNUM_SYS1_GPIO_A22 6
+#define PADNUM_SYS1_GPIO_A23 7
+
+/* sys2 pad numbers */
+#define PADNUM_SYS2_GPIO_A24 0
+#define PADNUM_SYS2_GPIO_A25 1
+#define PADNUM_SYS2_GPIO_A26 2
+#define PADNUM_SYS2_GPIO_A27 3
+#define PADNUM_SYS2_GPIO_A28 4
+#define PADNUM_SYS2_GPIO_A29 5
+#define PADNUM_SYS2_GPIO_A30 6
+#define PADNUM_SYS2_GPIO_A31 7
+#define PADNUM_SYS2_GPIO_A32 8
+#define PADNUM_SYS2_GPIO_A33 9
+#define PADNUM_SYS2_GPIO_A34 10
+#define PADNUM_SYS2_GPIO_A35 11
+#define PADNUM_SYS2_GPIO_A36 12
+#define PADNUM_SYS2_GPIO_A37 13
+#define PADNUM_SYS2_GPIO_A38 14
+#define PADNUM_SYS2_GPIO_A39 15
+#define PADNUM_SYS2_GPIO_A40 16
+#define PADNUM_SYS2_GPIO_A41 17
+#define PADNUM_SYS2_GPIO_A42 18
+#define PADNUM_SYS2_GPIO_A43 19
+#define PADNUM_SYS2_GPIO_A44 20
+#define PADNUM_SYS2_GPIO_A45 21
+#define PADNUM_SYS2_GPIO_A46 22
+#define PADNUM_SYS2_GPIO_A47 23
+#define PADNUM_SYS2_GPIO_A48 24
+#define PADNUM_SYS2_GPIO_A49 25
+#define PADNUM_SYS2_GPIO_A50 26
+#define PADNUM_SYS2_GPIO_A51 27
+#define PADNUM_SYS2_GPIO_A52 28
+#define PADNUM_SYS2_GPIO_A53 29
+#define PADNUM_SYS2_GPIO_A54 30
+#define PADNUM_SYS2_GPIO_A55 31
+#define PADNUM_SYS2_GPIO_A56 32
+#define PADNUM_SYS2_GPIO_A57 33
+#define PADNUM_SYS2_GPIO_A58 34
+#define PADNUM_SYS2_GPIO_A59 35
+#define PADNUM_SYS2_GPIO_A60 36
+
+/* per0 pad numbers */
+#define PADNUM_PER0_GPIO_B0 0
+#define PADNUM_PER0_GPIO_B1 1
+#define PADNUM_PER0_GPIO_B2 2
+#define PADNUM_PER0_GPIO_B3 3
+#define PADNUM_PER0_GPIO_B4 4
+#define PADNUM_PER0_GPIO_B5 5
+#define PADNUM_PER0_GPIO_B6 6
+#define PADNUM_PER0_GPIO_B7 7
+#define PADNUM_PER0_GPIO_B8 8
+#define PADNUM_PER0_GPIO_B9 9
+#define PADNUM_PER0_GPIO_B10 10
+#define PADNUM_PER0_GPIO_B11 11
+#define PADNUM_PER0_GPIO_B12 12
+#define PADNUM_PER0_GPIO_B13 13
+#define PADNUM_PER0_GPIO_B14 14
+#define PADNUM_PER0_GPIO_B15 15
+#define PADNUM_PER0_GPIO_B16 16
+#define PADNUM_PER0_GPIO_B17 17
+#define PADNUM_PER0_GPIO_B18 18
+#define PADNUM_PER0_GPIO_B19 19
+#define PADNUM_PER0_GPIO_B20 20
+#define PADNUM_PER0_GPIO_B21 21
+#define PADNUM_PER0_GPIO_B22 22
+#define PADNUM_PER0_GPIO_B23 23
+#define PADNUM_PER0_GPIO_B24 24
+#define PADNUM_PER0_GPIO_B25 25
+#define PADNUM_PER0_GPIO_B26 26
+#define PADNUM_PER0_GPIO_B27 27
+#define PADNUM_PER0_GPIO_B28 28
+#define PADNUM_PER0_GPIO_B29 29
+#define PADNUM_PER0_GPIO_B30 30
+#define PADNUM_PER0_GPIO_B31 31
+#define PADNUM_PER0_GPIO_B32 32
+#define PADNUM_PER0_GPIO_B33 33
+#define PADNUM_PER0_GPIO_B34 34
+#define PADNUM_PER0_GPIO_B35 35
+#define PADNUM_PER0_GPIO_B36 36
+#define PADNUM_PER0_GPIO_B37 37
+#define PADNUM_PER0_GPIO_B38 38
+#define PADNUM_PER0_GPIO_B39 39
+#define PADNUM_PER0_GPIO_B40 40
+#define PADNUM_PER0_GPIO_B41 41
+#define PADNUM_PER0_GPIO_B42 42
+#define PADNUM_PER0_GPIO_B43 43
+#define PADNUM_PER0_GPIO_B44 44
+#define PADNUM_PER0_GPIO_B45 45
+#define PADNUM_PER0_GPIO_B46 46
+#define PADNUM_PER0_GPIO_B47 47
+#define PADNUM_PER0_GPIO_B48 48
+#define PADNUM_PER0_GPIO_B49 49
+#define PADNUM_PER0_GPIO_B50 50
+#define PADNUM_PER0_GPIO_B51 51
+#define PADNUM_PER0_GPIO_B52 52
+#define PADNUM_PER0_GPIO_B53 53
+#define PADNUM_PER0_GPIO_B54 54
+#define PADNUM_PER0_GPIO_B55 55
+#define PADNUM_PER0_GPIO_B56 56
+#define PADNUM_PER0_GPIO_B57 57
+#define PADNUM_PER0_GPIO_B58 58
+#define PADNUM_PER0_GPIO_B59 59
+
+/* per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C28 28
+#define PADNUM_PER1_GPIO_C29 29
+#define PADNUM_PER1_GPIO_C30 30
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C32 32
+#define PADNUM_PER1_GPIO_C33 33
+#define PADNUM_PER1_GPIO_C34 34
+#define PADNUM_PER1_GPIO_C35 35
+
+/* per2 pad numbers */
+#define PADNUM_PER2_GPIO_D0 0
+#define PADNUM_PER2_GPIO_D1 1
+#define PADNUM_PER2_GPIO_D2 2
+#define PADNUM_PER2_GPIO_D3 3
+#define PADNUM_PER2_GPIO_D4 4
+#define PADNUM_PER2_GPIO_D5 5
+#define PADNUM_PER2_GPIO_D6 6
+#define PADNUM_PER2_GPIO_D7 7
+#define PADNUM_PER2_GPIO_D8 8
+#define PADNUM_PER2_GPIO_D9 9
+#define PADNUM_PER2_GPIO_D10 10
+#define PADNUM_PER2_GPIO_D11 11
+#define PADNUM_PER2_GPIO_D12 12
+#define PADNUM_PER2_GPIO_D13 13
+#define PADNUM_PER2_GPIO_D14 14
+#define PADNUM_PER2_GPIO_D15 15
+#define PADNUM_PER2_GPIO_D16 16
+#define PADNUM_PER2_GPIO_D17 17
+#define PADNUM_PER2_GPIO_D18 18
+#define PADNUM_PER2_GPIO_D19 19
+#define PADNUM_PER2_GPIO_D20 20
+#define PADNUM_PER2_GPIO_D21 21
+#define PADNUM_PER2_GPIO_D22 22
+#define PADNUM_PER2_GPIO_D23 23
+#define PADNUM_PER2_GPIO_D24 24
+#define PADNUM_PER2_GPIO_D25 25
+#define PADNUM_PER2_GPIO_D26 26
+#define PADNUM_PER2_GPIO_D27 27
+#define PADNUM_PER2_GPIO_D28 28
+#define PADNUM_PER2_GPIO_D29 29
+#define PADNUM_PER2_GPIO_D30 30
+
+/* per2pok pad numbers */
+#define PADNUM_PER2POK_GPIO_D31 0
+#define PADNUM_PER2POK_GPIO_D32 1
+#define PADNUM_PER2POK_GPIO_D33 2
+#define PADNUM_PER2POK_GPIO_D34 3
+#define PADNUM_PER2POK_GPIO_D35 4
+#define PADNUM_PER2POK_GPIO_D36 5
+#define PADNUM_PER2POK_GPIO_D37 6
+#define PADNUM_PER2POK_GPIO_D38 7
+#define PADNUM_PER2POK_GPIO_D39 8
+#define PADNUM_PER2POK_GPIO_D40 9
+#define PADNUM_PER2POK_GPIO_D41 10
+#define PADNUM_PER2POK_GPIO_D42 11
+#define PADNUM_PER2POK_GPIO_D43 12
+#define PADNUM_PER2POK_GPIO_D44 13
+#define PADNUM_PER2POK_GPIO_D45 14
+#define PADNUM_PER2POK_GPIO_D46 15
+#define PADNUM_PER2POK_GPIO_D47 16
+#define PADNUM_PER2POK_GPIO_D48 17
+
+/* per3 pad numbers */
+#define PADNUM_PER3_GPIO_E0 0
+#define PADNUM_PER3_GPIO_E1 1
+#define PADNUM_PER3_GPIO_E2 2
+#define PADNUM_PER3_GPIO_E3 3
+#define PADNUM_PER3_GPIO_E4 4
+#define PADNUM_PER3_GPIO_E5 5
+#define PADNUM_PER3_GPIO_E6 6
+#define PADNUM_PER3_GPIO_E7 7
+#define PADNUM_PER3_GPIO_E8 8
+#define PADNUM_PER3_GPIO_E9 9
+#define PADNUM_PER3_GPIO_E10 10
+#define PADNUM_PER3_GPIO_E11 11
+
+#endif
--
2.25.1
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next prev parent reply other threads:[~2026-09-10 10:04 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 01/22] dt-bindings: pincfg-node: Add property 'input-debounce-ns' Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 02/22] pinctrl: pinconf-generic: " Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 03/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:35 ` Rob Herring (Arm)
2026-09-18 18:35 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 04/22] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 05/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 19:01 ` Rob Herring (Arm)
2026-09-18 19:01 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 06/22] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 07/22] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:39 ` Rob Herring (Arm)
2026-09-18 18:39 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 08/22] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 09/22] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:39 ` Rob Herring
2026-09-18 18:39 ` Rob Herring
2026-09-10 10:03 ` [PATCH v8 10/22] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 11/22] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 19:02 ` Rob Herring (Arm)
2026-09-18 19:02 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 12/22] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 13/22] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:39 ` Rob Herring (Arm)
2026-09-18 18:39 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 14/22] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 15/22] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:40 ` Rob Herring (Arm)
2026-09-18 18:40 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 16/22] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 17/22] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 18:40 ` Rob Herring (Arm)
2026-09-18 18:40 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 18/22] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 19/22] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-18 19:02 ` Rob Herring (Arm)
2026-09-18 19:02 ` Rob Herring (Arm)
2026-09-10 10:03 ` [PATCH v8 20/22] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang [this message]
2026-09-10 10:03 ` [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 22/22] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
2026-09-10 10:03 ` Changhuang Liang
2026-09-30 22:20 ` [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Linus Walleij
2026-09-30 22:20 ` Linus Walleij
2026-09-30 22:34 ` Conor Dooley
2026-09-30 22:34 ` Conor Dooley
2026-10-01 8:36 ` Linus Walleij
2026-10-01 8:36 ` Linus Walleij
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