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From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	olteanv@gmail.com, vkoul@kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
Date: Wed, 16 Sep 2026 06:11:08 +0000	[thread overview]
Message-ID: <20260916061109.1F1121F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-3-0b2195836f30@oss.qualcomm.com>

> Per HPG, the controller now calls phy_init() from
> qcom_pcie_host_init() and phy_reset() from inside its own core reset
> assert/deassert. Making that actually happen here needs phy_ops::init
> and phy_ops::reset implemented, and phy_ops::power_on adjusted to
> match. Split the combined phy_ops::power_on/power_off into
> phy_ops::init/exit/reset/power_on to do that.
> 
> phy_ops::init enables power domains, regulators, and all PHY clocks
> (pipe clock first). phy_ops::reset does the no-CSR reset assert/
> delay/deassert/delay. phy_ops::power_on is left with just the PCS
> status poll. phy_ops::exit mirrors phy_ops::init in reverse;
> phy_ops::power_off is dropped since nothing remains for it to do.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=3


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WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	olteanv@gmail.com, vkoul@kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
Date: Wed, 16 Sep 2026 06:11:08 +0000	[thread overview]
Message-ID: <20260916061109.1F1121F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-3-0b2195836f30@oss.qualcomm.com>

> Per HPG, the controller now calls phy_init() from
> qcom_pcie_host_init() and phy_reset() from inside its own core reset
> assert/deassert. Making that actually happen here needs phy_ops::init
> and phy_ops::reset implemented, and phy_ops::power_on adjusted to
> match. Split the combined phy_ops::power_on/power_off into
> phy_ops::init/exit/reset/power_on to do that.
> 
> phy_ops::init enables power domains, regulators, and all PHY clocks
> (pipe clock first). phy_ops::reset does the no-CSR reset assert/
> delay/deassert/delay. phy_ops::power_on is left with just the PCS
> status poll. phy_ops::exit mirrors phy_ops::init in reverse;
> phy_ops::power_off is dropped since nothing remains for it to do.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=3


  reply	other threads:[~2026-09-16  6:11 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16  6:04 [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Qiang Yu
2026-09-16  6:04 ` Qiang Yu
2026-09-16  6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:12   ` sashiko-bot
2026-09-16  6:12     ` sashiko-bot
2026-09-21  9:14   ` Kathiravan Thirumoorthy
2026-09-21  9:14     ` Kathiravan Thirumoorthy
2026-09-16  6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:14   ` sashiko-bot
2026-09-16  6:14     ` sashiko-bot
2026-10-12 15:29   ` Manivannan Sadhasivam
2026-10-12 15:29     ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:11   ` sashiko-bot [this message]
2026-09-16  6:11     ` sashiko-bot
2026-10-12 15:32   ` Manivannan Sadhasivam
2026-10-12 15:32     ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:17   ` sashiko-bot
2026-09-16  6:17     ` sashiko-bot
2026-10-12 15:33     ` Manivannan Sadhasivam
2026-10-12 15:33       ` Manivannan Sadhasivam
2026-09-21  9:15   ` Kathiravan Thirumoorthy
2026-09-21  9:15     ` Kathiravan Thirumoorthy
2026-10-13 14:26   ` Michael Burch
2026-10-13 14:26     ` Michael Burch
2026-09-16 15:55 ` [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Bjorn Helgaas
2026-09-16 15:55   ` Bjorn Helgaas
2026-09-21 11:16   ` Manivannan Sadhasivam
2026-09-21 11:16     ` Manivannan Sadhasivam

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