From: Manivannan Sadhasivam <mani@kernel.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
Date: Mon, 12 Oct 2026 21:02:24 +0530 [thread overview]
Message-ID: <asz9ApG3h3EJC40t@debian> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-3-0b2195836f30@oss.qualcomm.com>
On Tue, Sep 15, 2026 at 11:04:23PM -0700, Qiang Yu wrote:
> Per HPG, the controller now calls phy_init() from
> qcom_pcie_host_init() and phy_reset() from inside its own core reset
> assert/deassert. Making that actually happen here needs phy_ops::init
> and phy_ops::reset implemented, and phy_ops::power_on adjusted to
> match. Split the combined phy_ops::power_on/power_off into
> phy_ops::init/exit/reset/power_on to do that.
>
> phy_ops::init enables power domains, regulators, and all PHY clocks
> (pipe clock first). phy_ops::reset does the no-CSR reset assert/
> delay/deassert/delay. phy_ops::power_on is left with just the PCS
> status poll. phy_ops::exit mirrors phy_ops::init in reverse;
> phy_ops::power_off is dropped since nothing remains for it to do.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
- Mani
--
மணிவண்ணன் சதாசிவம்
--
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WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <mani@kernel.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
Date: Mon, 12 Oct 2026 21:02:24 +0530 [thread overview]
Message-ID: <asz9ApG3h3EJC40t@debian> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-3-0b2195836f30@oss.qualcomm.com>
On Tue, Sep 15, 2026 at 11:04:23PM -0700, Qiang Yu wrote:
> Per HPG, the controller now calls phy_init() from
> qcom_pcie_host_init() and phy_reset() from inside its own core reset
> assert/deassert. Making that actually happen here needs phy_ops::init
> and phy_ops::reset implemented, and phy_ops::power_on adjusted to
> match. Split the combined phy_ops::power_on/power_off into
> phy_ops::init/exit/reset/power_on to do that.
>
> phy_ops::init enables power domains, regulators, and all PHY clocks
> (pipe clock first). phy_ops::reset does the no-CSR reset assert/
> delay/deassert/delay. phy_ops::power_on is left with just the PCS
> status poll. phy_ops::exit mirrors phy_ops::init in reverse;
> phy_ops::power_off is dropped since nothing remains for it to do.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2026-10-12 15:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 6:04 [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Qiang Yu
2026-09-16 6:04 ` Qiang Yu
2026-09-16 6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-16 6:04 ` Qiang Yu
2026-09-16 6:12 ` sashiko-bot
2026-09-16 6:12 ` sashiko-bot
2026-09-21 9:14 ` Kathiravan Thirumoorthy
2026-09-21 9:14 ` Kathiravan Thirumoorthy
2026-09-16 6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-09-16 6:04 ` Qiang Yu
2026-09-16 6:14 ` sashiko-bot
2026-09-16 6:14 ` sashiko-bot
2026-10-12 15:29 ` Manivannan Sadhasivam
2026-10-12 15:29 ` Manivannan Sadhasivam
2026-09-16 6:04 ` [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on Qiang Yu
2026-09-16 6:04 ` Qiang Yu
2026-09-16 6:11 ` sashiko-bot
2026-09-16 6:11 ` sashiko-bot
2026-10-12 15:32 ` Manivannan Sadhasivam [this message]
2026-10-12 15:32 ` Manivannan Sadhasivam
2026-09-16 6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: " Qiang Yu
2026-09-16 6:04 ` Qiang Yu
2026-09-16 6:17 ` sashiko-bot
2026-09-16 6:17 ` sashiko-bot
2026-10-12 15:33 ` Manivannan Sadhasivam
2026-10-12 15:33 ` Manivannan Sadhasivam
2026-09-21 9:15 ` Kathiravan Thirumoorthy
2026-09-21 9:15 ` Kathiravan Thirumoorthy
2026-10-13 14:26 ` Michael Burch
2026-10-13 14:26 ` Michael Burch
2026-09-16 15:55 ` [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Bjorn Helgaas
2026-09-16 15:55 ` Bjorn Helgaas
2026-09-21 11:16 ` Manivannan Sadhasivam
2026-09-21 11:16 ` Manivannan Sadhasivam
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