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From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: neil.armstrong@linaro.org, linux-pci@vger.kernel.org,
	olteanv@gmail.com, vkoul@kernel.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG
Date: Wed, 16 Sep 2026 06:12:34 +0000	[thread overview]
Message-ID: <20260916061235.093441F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com>

> HPG requires the controller/PHY GDSCs powered up and all controller/PHY
> clocks enabled first, then the controller's reset and the PHY's reset
> toggled together as a group, PARF_DEVICE_TYPE set right after, and the
> rest of the PARF/DBI config left until the PHY is ready.
> 
> Make use of phy_init() and phy_reset(), and change the call flow to:
> 
>   qcom_pcie_host_init():
>     phy_init()             (PHY GDSCs/regulators/clocks up)
>     qcom_pcie_ops::init:
>       enable controller clocks
>       assert controller reset
>       phy_reset()           (toggle the PHY's own reset)
>       deassert controller reset
>       write PARF_DEVICE_TYPE
> [ ... ]
> site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the
> same point relative to that platform's own clock/reset programming, so its
> init sequence doesn't change either.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: neil.armstrong@linaro.org, linux-pci@vger.kernel.org,
	olteanv@gmail.com, vkoul@kernel.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG
Date: Wed, 16 Sep 2026 06:12:34 +0000	[thread overview]
Message-ID: <20260916061235.093441F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com>

> HPG requires the controller/PHY GDSCs powered up and all controller/PHY
> clocks enabled first, then the controller's reset and the PHY's reset
> toggled together as a group, PARF_DEVICE_TYPE set right after, and the
> rest of the PARF/DBI config left until the PHY is ready.
> 
> Make use of phy_init() and phy_reset(), and change the call flow to:
> 
>   qcom_pcie_host_init():
>     phy_init()             (PHY GDSCs/regulators/clocks up)
>     qcom_pcie_ops::init:
>       enable controller clocks
>       assert controller reset
>       phy_reset()           (toggle the PHY's own reset)
>       deassert controller reset
>       write PARF_DEVICE_TYPE
> [ ... ]
> site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the
> same point relative to that platform's own clock/reset programming, so its
> init sequence doesn't change either.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=1


  reply	other threads:[~2026-09-16  6:12 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16  6:04 [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Qiang Yu
2026-09-16  6:04 ` Qiang Yu
2026-09-16  6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:12   ` sashiko-bot [this message]
2026-09-16  6:12     ` sashiko-bot
2026-09-21  9:14   ` Kathiravan Thirumoorthy
2026-09-21  9:14     ` Kathiravan Thirumoorthy
2026-09-16  6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:14   ` sashiko-bot
2026-09-16  6:14     ` sashiko-bot
2026-10-12 15:29   ` Manivannan Sadhasivam
2026-10-12 15:29     ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:11   ` sashiko-bot
2026-09-16  6:11     ` sashiko-bot
2026-10-12 15:32   ` Manivannan Sadhasivam
2026-10-12 15:32     ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: " Qiang Yu
2026-09-16  6:04   ` Qiang Yu
2026-09-16  6:17   ` sashiko-bot
2026-09-16  6:17     ` sashiko-bot
2026-10-12 15:33     ` Manivannan Sadhasivam
2026-10-12 15:33       ` Manivannan Sadhasivam
2026-09-21  9:15   ` Kathiravan Thirumoorthy
2026-09-21  9:15     ` Kathiravan Thirumoorthy
2026-10-13 14:26   ` Michael Burch
2026-10-13 14:26     ` Michael Burch
2026-09-16 15:55 ` [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Bjorn Helgaas
2026-09-16 15:55   ` Bjorn Helgaas
2026-09-21 11:16   ` Manivannan Sadhasivam
2026-09-21 11:16     ` Manivannan Sadhasivam

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