From: Bjorn Helgaas <helgaas@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, heiko@sntech.de, mani@kernel.org,
yue.wang@amlogic.com, pali@kernel.org, neil.armstrong@linaro.org,
robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com,
jbrunet@baylibre.com, martin.blumenstingl@googlemail.com,
cassel@kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org,
Feizhou Yu <yufeizhou201@163.com>
Subject: Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation
Date: Mon, 28 Sep 2026 16:50:07 -0500 [thread overview]
Message-ID: <20260928215007.GA2264960@bhelgaas> (raw)
In-Reply-To: <20260911162537.469018-2-18255117159@163.com>
On Sat, Sep 12, 2026 at 12:25:36AM +0800, Hans Zhang wrote:
> The DWC PCIe register and field macros are inconsistently named and
> often do not match the Synopsys DesignWare PCIe Controller Reference
> Manual. This makes it harder to cross-reference the code with the
> documentation when debugging or maintaining the driver.
> +#define PORT_AFAC_L0S_ELS 24 /* L0s Entrance Latency shift */
> +#define PORT_AFAC_L0S_ELM GENMASK(26, 24) /* L0s Entrance Latency mask */
> +#define PORT_AFAC_L1_ELS 27 /* L1 Entrance Latency shift */
> +#define PORT_AFAC_L1_ELM GENMASK(29, 27) /* L1 Entrance Latency mask */
Surely we don't need both the shift and the mask? Maybe a separate
patch convert to FIELD_PREP()?
> +#define GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24 /* Rate Shadow Select shift */
> +#define GEN3_CTRL_RATE_SHADOW_SEL_MASK GENMASK(25, 24) /* Rate Shadow Select mask */
Ditto.
> +#define MSIX_DOORBELL 0x948
> +#define MSIX_DOORBELL_PF_SHIFT 24
Probably would be better to define a mask so we have the position
*and* the width.
> @@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
> u32 val;
>
> val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
> - PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
> + RAS_DES_EVENT_COUNTER_CONTROL);
> val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
> val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
> val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
> val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
Probably a good chance to convert these to FIELD_PREP() etc. as well,
maybe in a separate patch.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, heiko@sntech.de, mani@kernel.org,
yue.wang@amlogic.com, pali@kernel.org, neil.armstrong@linaro.org,
robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com,
jbrunet@baylibre.com, martin.blumenstingl@googlemail.com,
cassel@kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org,
Feizhou Yu <yufeizhou201@163.com>
Subject: Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation
Date: Mon, 28 Sep 2026 16:50:07 -0500 [thread overview]
Message-ID: <20260928215007.GA2264960@bhelgaas> (raw)
In-Reply-To: <20260911162537.469018-2-18255117159@163.com>
On Sat, Sep 12, 2026 at 12:25:36AM +0800, Hans Zhang wrote:
> The DWC PCIe register and field macros are inconsistently named and
> often do not match the Synopsys DesignWare PCIe Controller Reference
> Manual. This makes it harder to cross-reference the code with the
> documentation when debugging or maintaining the driver.
> +#define PORT_AFAC_L0S_ELS 24 /* L0s Entrance Latency shift */
> +#define PORT_AFAC_L0S_ELM GENMASK(26, 24) /* L0s Entrance Latency mask */
> +#define PORT_AFAC_L1_ELS 27 /* L1 Entrance Latency shift */
> +#define PORT_AFAC_L1_ELM GENMASK(29, 27) /* L1 Entrance Latency mask */
Surely we don't need both the shift and the mask? Maybe a separate
patch convert to FIELD_PREP()?
> +#define GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24 /* Rate Shadow Select shift */
> +#define GEN3_CTRL_RATE_SHADOW_SEL_MASK GENMASK(25, 24) /* Rate Shadow Select mask */
Ditto.
> +#define MSIX_DOORBELL 0x948
> +#define MSIX_DOORBELL_PF_SHIFT 24
Probably would be better to define a mask so we have the position
*and* the width.
> @@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
> u32 val;
>
> val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
> - PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
> + RAS_DES_EVENT_COUNTER_CONTROL);
> val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
> val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
> val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
> val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
Probably a good chance to convert these to FIELD_PREP() etc. as well,
maybe in a separate patch.
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, heiko@sntech.de, mani@kernel.org,
yue.wang@amlogic.com, pali@kernel.org, neil.armstrong@linaro.org,
robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com,
jbrunet@baylibre.com, martin.blumenstingl@googlemail.com,
cassel@kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org,
Feizhou Yu <yufeizhou201@163.com>
Subject: Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation
Date: Mon, 28 Sep 2026 16:50:07 -0500 [thread overview]
Message-ID: <20260928215007.GA2264960@bhelgaas> (raw)
In-Reply-To: <20260911162537.469018-2-18255117159@163.com>
On Sat, Sep 12, 2026 at 12:25:36AM +0800, Hans Zhang wrote:
> The DWC PCIe register and field macros are inconsistently named and
> often do not match the Synopsys DesignWare PCIe Controller Reference
> Manual. This makes it harder to cross-reference the code with the
> documentation when debugging or maintaining the driver.
> +#define PORT_AFAC_L0S_ELS 24 /* L0s Entrance Latency shift */
> +#define PORT_AFAC_L0S_ELM GENMASK(26, 24) /* L0s Entrance Latency mask */
> +#define PORT_AFAC_L1_ELS 27 /* L1 Entrance Latency shift */
> +#define PORT_AFAC_L1_ELM GENMASK(29, 27) /* L1 Entrance Latency mask */
Surely we don't need both the shift and the mask? Maybe a separate
patch convert to FIELD_PREP()?
> +#define GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24 /* Rate Shadow Select shift */
> +#define GEN3_CTRL_RATE_SHADOW_SEL_MASK GENMASK(25, 24) /* Rate Shadow Select mask */
Ditto.
> +#define MSIX_DOORBELL 0x948
> +#define MSIX_DOORBELL_PF_SHIFT 24
Probably would be better to define a mask so we have the position
*and* the width.
> @@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
> u32 val;
>
> val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
> - PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
> + RAS_DES_EVENT_COUNTER_CONTROL);
> val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
> val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
> val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
> val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
Probably a good chance to convert these to FIELD_PREP() etc. as well,
maybe in a separate patch.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2026-09-28 21:50 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 16:25 [PATCH 0/2] PCI: dwc: Clean up DWC PCIe register macros Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:25 ` [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:34 ` sashiko-bot
2026-09-11 16:34 ` sashiko-bot
2026-09-28 21:50 ` Bjorn Helgaas [this message]
2026-09-28 21:50 ` Bjorn Helgaas
2026-09-28 21:50 ` Bjorn Helgaas
2026-09-28 21:51 ` Bjorn Helgaas
2026-09-28 21:51 ` Bjorn Helgaas
2026-09-28 21:51 ` Bjorn Helgaas
2026-09-30 1:27 ` Hans Zhang
2026-09-30 1:27 ` Hans Zhang
2026-09-30 1:27 ` Hans Zhang
2026-09-11 16:25 ` [PATCH 2/2] PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:25 ` Hans Zhang
2026-09-11 16:29 ` sashiko-bot
2026-09-11 16:29 ` sashiko-bot
2026-09-28 3:10 ` [PATCH 0/2] PCI: dwc: Clean up DWC PCIe register macros Manivannan Sadhasivam
2026-09-28 3:10 ` Manivannan Sadhasivam
2026-09-28 3:10 ` Manivannan Sadhasivam
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