[PATCH 0/3] clk: qcom: Add SM8350 camera clock controller

[Vladimir Zapolskiy <vz@kernel.org>]

Add the camera clock controller (CAMCC) for Qualcomm SM8350 SoC, the
clock configuration was taken from camcc-lahaina.c from msm-5.10.

CAM_CC_PLL0 runs at 1200MHz, which requires the SVS_L1 level of the MX
rail, so it is set as the MX performance state in the device tree node.

Vladimir Zapolskiy (3):
  dt-bindings: clock: qcom: Add SM8350 camera clock controller
  clk: qcom: Add SM8350 camera clock controller driver
  arm64: dts: qcom: sm8350: Add camera clock controller

 .../bindings/clock/qcom,sm8350-camcc.yaml     |   69 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi          |   15 +
 drivers/clk/qcom/Kconfig                      |    9 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/camcc-sm8350.c               | 2650 +++++++++++++++++
 include/dt-bindings/clock/qcom,sm8350-camcc.h |  149 +
 6 files changed, 2893 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8350-camcc.yaml
 create mode 100644 drivers/clk/qcom/camcc-sm8350.c
 create mode 100644 include/dt-bindings/clock/qcom,sm8350-camcc.h

-- 
2.51.0