[PATCH v7 0/7] Add PCIe Root Port support for Agilex family of chips

[PATCH v7 0/7] Add PCIe Root Port support for Agilex family of chips

[Matthew Gerlach]

This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.
Version 6 refactors duplicate dts snippets into dtsi's for correctness and
maintainability.

Patch 1:
  Add new compatible strings for the three variants of the Agilex PCIe controller IP.

Patch 2:
  Add new board compatible string for Agilex F-series devkit with PCIe Root Port.

Patch 3:
  Fix fixed-clock schema warnings in socfpga_agilex.dtsi before adding to it.

Patch 4:
  Move bus@80000000 dt node to socfpga_agilex.dtsi.

Patch 5:
  Add base dtsi for PCIe Root Port support of the Agilex family of chips.

Patch 6:
  Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit.

Patch 7:
  Update Altera PCIe controller driver to support the Agilex family of chips.

D M, Sharath Kumar (1):
  PCI: altera: Add Agilex support

Matthew Gerlach (6):
  dt-bindings: PCI: altera: Add binding for Agilex
  dt-bindings: intel: document Agilex PCIe Root Port
  arm64: dts: agilex: Fix fixed-clock schema warnings
  arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi
  arm64: dts: agilex: add dtsi for PCIe Root Port
  arm64: dts: agilex: add dts enabling PCIe Root Port

 .../bindings/arm/intel,socfpga.yaml           |   1 +
 .../bindings/pci/altr,pcie-root-port.yaml     |  10 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  14 +
 .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   |  31 +--
 .../intel/socfpga_agilex_pcie_root_port.dtsi  |  48 ++++
 .../boot/dts/intel/socfpga_agilex_socdk.dts   |   1 +
 .../dts/intel/socfpga_agilex_socdk_nand.dts   |   1 +
 drivers/pci/controller/pcie-altera.c          | 253 +++++++++++++++++-
 10 files changed, 479 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi

-- 
2.34.1

[PATCH v7 1/7] dt-bindings: PCI: altera: Add binding for Agilex

[Matthew Gerlach]

Add the compatible bindings for the three variants of Agilex
PCIe Hard IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../devicetree/bindings/pci/altr,pcie-root-port.yaml   | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
index 52533fccc134..1f93120d8eef 100644
--- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
+++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
@@ -12,9 +12,19 @@ maintainers:
 
 properties:
   compatible:
+    description: Each family of socfpga has its own implementation
+      of the pci controller. altr,pcie-root-port-1.0 is used for the Cyclone5
+      family of chips. The Stratix10 family of chips is supported
+      by altr,pcie-root-port-2.0. The Agilex family of chips has
+      three, non-register compatible, variants of PCIe Hard IP referred to as
+      the f-tile, p-tile, and r-tile, depending on the specific chip instance.
+
     enum:
       - altr,pcie-root-port-1.0
       - altr,pcie-root-port-2.0
+      - altr,pcie-root-port-3.0-f-tile
+      - altr,pcie-root-port-3.0-p-tile
+      - altr,pcie-root-port-3.0-r-tile
 
   reg:
     items:
-- 
2.34.1

[PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port

[Matthew Gerlach]

The Agilex7f devkit can support PCIe End Points with the appropriate
daughter card.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - New patch to series.
---
 Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
index 2ee0c740eb56..0da5810c9510 100644
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
@@ -20,6 +20,7 @@ properties:
               - intel,n5x-socdk
               - intel,socfpga-agilex-n6000
               - intel,socfpga-agilex-socdk
+              - intel,socfpga-agilex7f-socdk-pcie-root-port
           - const: intel,socfpga-agilex
       - description: Agilex5 boards
         items:
-- 
2.34.1

Re: [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port

[Krzysztof Kozlowski]

On Sat, Feb 15, 2025 at 09:53:54AM -0600, Matthew Gerlach wrote:
> The Agilex7f devkit can support PCIe End Points with the appropriate
> daughter card.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> v7:
>  - New patch to series.
> ---
>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> index 2ee0c740eb56..0da5810c9510 100644
> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> @@ -20,6 +20,7 @@ properties:
>                - intel,n5x-socdk
>                - intel,socfpga-agilex-n6000
>                - intel,socfpga-agilex-socdk
> +              - intel,socfpga-agilex7f-socdk-pcie-root-port

Compatible should represent the board, so what is here exactly the
board? 7f? Agilex7f? socdk? Or is it standard agilex-socdk but with some
things attached?

But then, are they attached or you just creat the same board with
different configuration?

Best regards,
Krzysztof

Re: [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port

[matthew.gerlach]

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:54AM -0600, Matthew Gerlach wrote:
>> The Agilex7f devkit can support PCIe End Points with the appropriate
>> daughter card.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v7:
>>  - New patch to series.
>> ---
>>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> index 2ee0c740eb56..0da5810c9510 100644
>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> @@ -20,6 +20,7 @@ properties:
>>                - intel,n5x-socdk
>>                - intel,socfpga-agilex-n6000
>>                - intel,socfpga-agilex-socdk
>> +              - intel,socfpga-agilex7f-socdk-pcie-root-port
>
> Compatible should represent the board, so what is here exactly the
> board? 7f? Agilex7f? socdk? Or is it standard agilex-socdk but with some
> things attached?

The board is the Agilex 7 FPGA F-Series Transceiver-Soc Development Kit:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html

There is not a single, standard agilex-socdk board. There are currently 
three variants. In addition to the F-Series socdk, there are I-Series and 
M-Series devkits:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

>
> But then, are they attached or you just creat the same board with
> different configuration?
The PCIe Root Port does involve a different FPGA configuration, but 
depending on the board, daughter cards and possibly cables are also 
involved.

>
> Best regards,
> Krzysztof
>
>
Thanks for the feedback,
Matthew Gerlach

Re: [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port

[Krzysztof Kozlowski]

On 17/02/2025 16:47, matthew.gerlach@linux.intel.com wrote:
> 
> 
> On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:
> 
>> On Sat, Feb 15, 2025 at 09:53:54AM -0600, Matthew Gerlach wrote:
>>> The Agilex7f devkit can support PCIe End Points with the appropriate
>>> daughter card.
>>>
>>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>> ---
>>> v7:
>>>  - New patch to series.
>>> ---
>>>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>> index 2ee0c740eb56..0da5810c9510 100644
>>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>> @@ -20,6 +20,7 @@ properties:
>>>                - intel,n5x-socdk
>>>                - intel,socfpga-agilex-n6000
>>>                - intel,socfpga-agilex-socdk
>>> +              - intel,socfpga-agilex7f-socdk-pcie-root-port
>>
>> Compatible should represent the board, so what is here exactly the
>> board? 7f? Agilex7f? socdk? Or is it standard agilex-socdk but with some
>> things attached?
> 
> The board is the Agilex 7 FPGA F-Series Transceiver-Soc Development Kit:
> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html

Isn't Agilex7 a SoC? I don't see it in the list of compatibles.

> 
> There is not a single, standard agilex-socdk board. There are currently 
> three variants. In addition to the F-Series socdk, there are I-Series and 
> M-Series devkits:
> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html
> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

Pages above show distinctive names for the boards, so I am confused why
they are not used.



Best regards,
Krzysztof

Re: [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port

[matthew.gerlach]

On Tue, 18 Feb 2025, Krzysztof Kozlowski wrote:

> On 17/02/2025 16:47, matthew.gerlach@linux.intel.com wrote:
>>
>>
>> On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:
>>
>>> On Sat, Feb 15, 2025 at 09:53:54AM -0600, Matthew Gerlach wrote:
>>>> The Agilex7f devkit can support PCIe End Points with the appropriate
>>>> daughter card.
>>>>
>>>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>>> ---
>>>> v7:
>>>>  - New patch to series.
>>>> ---
>>>>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>>>>  1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>>> index 2ee0c740eb56..0da5810c9510 100644
>>>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>>>> @@ -20,6 +20,7 @@ properties:
>>>>                - intel,n5x-socdk
>>>>                - intel,socfpga-agilex-n6000
>>>>                - intel,socfpga-agilex-socdk
>>>> +              - intel,socfpga-agilex7f-socdk-pcie-root-port
>>>
>>> Compatible should represent the board, so what is here exactly the
>>> board? 7f? Agilex7f? socdk? Or is it standard agilex-socdk but with some
>>> things attached?
>>
>> The board is the Agilex 7 FPGA F-Series Transceiver-Soc Development Kit:
>> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html
>
> Isn't Agilex7 a SoC? I don't see it in the list of compatibles.
There are actually 3 different variants of the Agilex7 SoC.
>
>>
>> There is not a single, standard agilex-socdk board. There are currently
>> three variants. In addition to the F-Series socdk, there are I-Series and
>> M-Series devkits:
>> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html
>> https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html
>
> Pages above show distinctive names for the boards, so I am confused why
> they are not used.

Yes, the distinctive names of the boards should be used:
               - intel,socfpga-agilex7f-socdk
               - intel,socfpga-agilex7i-socdk
               - intel,socfpga-agilex7m-socdk
>
>
>
> Best regards,
> Krzysztof
>

Thanks for the feedback,
Matthew Gerlach

[PATCH v7 3/7] arm64: dts: agilex: Fix fixed-clock schema warnings

[Matthew Gerlach]

All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
but the board specific DTS determines which fixed-clocks are actually
used and at what frequency. Fix the schema check warning about fixed-clock
nodes requiring a clock-frequency by disabling all the fixed-clocks in the
DTSI and enabling clocks used by a board in the board specific DTS.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Disable fixed-clock in DTSI instead of setting clock-frequency = <0>;

v6:
 - New patch to series
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi           | 4 ++++
 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts      | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts      | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts | 1 +
 4 files changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 1235ba5a9865..202b4404577e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -114,21 +114,25 @@ clocks {
 		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		cb_intosc_ls_clk: cb-intosc-ls-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		f2s_free_clk: f2s-free-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		osc1: osc1 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		qspi_clk: qspi-clk {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index d22de06e9839..55f825c5245f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -47,6 +47,7 @@ dma-controller@0 {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..3337b19836af 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -88,6 +88,7 @@ &mmc {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 0f9020bd0c52..40be9eb41aab 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -100,6 +100,7 @@ partition@200000 {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
-- 
2.34.1

Re: [PATCH v7 3/7] arm64: dts: agilex: Fix fixed-clock schema warnings

[Krzysztof Kozlowski]

On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,


That's not what I asked / talked about. If the clocks are in SoC, they
cannot be disabled.

If they clocks are not in SoC, they should not be in DTSI.

These were my statements last time and this patch does not comple.
Commit msg does not explain why this should be done differently.

Best regards,
Krzysztof

Re: [PATCH v7 3/7] arm64: dts: agilex: Fix fixed-clock schema warnings

[matthew.gerlach]

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
>> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
>
>
> That's not what I asked / talked about. If the clocks are in SoC, they
> cannot be disabled.

There are two clocks, cb_intoosc_hs_div2_clk and cb_intosc_ls_clk, in the 
SoC with a known frequency. These warnings can be fixed in the DTSI.

>
> If they clocks are not in SoC, they should not be in DTSI.

The two clocks, f2s_free_clk and osc1, are not in the SoC; so they should 
be removed from DTSI.

>
> These were my statements last time and this patch does not comple.
> Commit msg does not explain why this should be done differently.
>
> Best regards,
> Krzysztof
>
>

Thanks for the feedback,
Matthew Gerlach

Re: [PATCH v7 3/7] arm64: dts: agilex: Fix fixed-clock schema warnings

[matthew.gerlach]

On Tue, 18 Feb 2025, matthew.gerlach@linux.intel.com wrote:

>
>
> On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:
>
>> On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
>>> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
>> 
>> 
>> That's not what I asked / talked about. If the clocks are in SoC, they
>> cannot be disabled.
>
> There are two clocks, cb_intoosc_hs_div2_clk and cb_intosc_ls_clk, in the SoC 
> with a known frequency. These warnings can be fixed in the DTSI.
>
>> 
>> If they clocks are not in SoC, they should not be in DTSI.
>
> The two clocks, f2s_free_clk and osc1, are not in the SoC; so they should be 
> removed from DTSI.

Since these clock changes are not directly related to adding PCIe Root 
Port support to Agilex chips, I think they should be in their patch set.

Matthew Gerlach

>
>> 
>> These were my statements last time and this patch does not comple.
>> Commit msg does not explain why this should be done differently.
>> 
>> Best regards,
>> Krzysztof
>> 
>> 
>
> Thanks for the feedback,
> Matthew Gerlach
>

[PATCH v7 4/7] arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi

[Matthew Gerlach]

The bus from HPS to the FPGA is part of the SoC. Move its
device tree node to socfpga_agilex.dtsi to allow it to be
referenced by any board.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Fix sorting of nodes.

v6:
 - New patch to series.
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 10 +++++++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   | 30 +++++++------------
 2 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 202b4404577e..3f4fb9cb312f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -678,5 +678,15 @@ qspi: spi@ff8d2000 {
 
 			status = "disabled";
 		};
+
+		bus80000000: bus@80000000 {
+			compatible = "simple-bus";
+			reg = <0x80000000 0x60000000>,
+			      <0xf9000000 0x00100000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index 55f825c5245f..62d2b3febbdd 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -25,26 +25,22 @@ memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0 0x80000000 0 0>;
 	};
+};
 
-	soc@0 {
-		bus@80000000 {
-			compatible = "simple-bus";
-			reg = <0x80000000 0x60000000>,
-				<0xf9000000 0x00100000>;
-			reg-names = "axi_h2f", "axi_h2f_lw";
-			#address-cells = <2>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+&bus80000000 {
+	ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
 
-			dma-controller@0 {
-				compatible = "intel,hps-copy-engine";
-				reg = <0x00000000 0x00000000 0x00001000>;
-				#dma-cells = <1>;
-			};
-		};
+	dma-controller@0 {
+		compatible = "intel,hps-copy-engine";
+		reg = <0x00000000 0x00000000 0x00001000>;
+		#dma-cells = <1>;
 	};
 };
 
+&fpga_mgr {
+	status = "disabled";
+};
+
 &osc1 {
 	clock-frequency = <25000000>;
 	status = "okay";
@@ -61,7 +57,3 @@ &uart1 {
 &watchdog0 {
 	status = "okay";
 };
-
-&fpga_mgr {
-	status = "disabled";
-};
-- 
2.34.1

[PATCH v7 5/7] arm64: dts: agilex: add dtsi for PCIe Root Port

[Matthew Gerlach]

Add the base device tree for support of the PCIe Root Port
for the Agilex family of chips.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Change value of #interrupt-cells to decimal.

v6:
 - Reference bus80000000 in socfpga_agilex.dtsi
 - Change values of #address-cells, #size-cell, and num-vectors to decimal
 - Fix SPDX header.
 - Fix checkpatch.pl line length warning.
 - Fix "address format error" from dtschema check.

v3:
 - Remove accepted patches from patch set.

v2:
 - Rename node to fix schema check error.
---
 .../intel/socfpga_agilex_pcie_root_port.dtsi  | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
new file mode 100644
index 000000000000..5333bd3fe535
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+&bus80000000 {
+	ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+		 <0x00000000 0x10000000 0x90100000 0x0ff00000>,
+		 <0x00000000 0x20000000 0xa0000000 0x00200000>,
+		 <0x00000001 0x00010000 0xf9010000 0x00008000>,
+		 <0x00000001 0x00018000 0xf9018000 0x00000080>,
+		 <0x00000001 0x00018080 0xf9018080 0x00000010>;
+
+	pcie_0_pcie_aglx: pcie@10000000 {
+		reg = <0x00000000 0x10000000 0x10000000>,
+		      <0x00000001 0x00010000 0x00008000>,
+		      <0x00000000 0x20000000 0x00200000>;
+		reg-names = "Txs", "Cra", "Hip";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		device_type = "pci";
+		bus-range = <0x0000000 0x000000ff>;
+		ranges = <0x82000000 0x00000000 0x00100000 0x00000000
+			  0x10000000 0x00000000 0x0ff00000>;
+		msi-parent = <&pcie_0_msi_irq>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+		interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>,
+				<0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>,
+				<0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>,
+				<0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>;
+		status = "disabled";
+	};
+
+	pcie_0_msi_irq: msi@100018080 {
+		compatible = "altr,msi-1.0";
+		reg = <0x00000001 0x00018080 0x00000010>,
+		      <0x00000001 0x00018000 0x00000080>;
+		reg-names = "csr", "vector_slave";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>;
+		msi-controller;
+		num-vectors = <32>;
+		status = "disabled";
+	};
+};
-- 
2.34.1

[PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port

[Matthew Gerlach]

Add a device tree enabling PCIe Root Port support on an Agilex F-series
Development Kit which has the P-tile variant of the PCIe IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Create and use appropriate board compatibility and use of model.

v6:
 - Fix SPDX header.
 - Make compatible property first.
 - Fix comment line wrapping.
 - Don't include .dts.

v3:
 - Remove accepted patches from patch set.
---
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b..737e81c3c3f7 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -2,6 +2,7 @@
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex_socdk.dtb \
 				socfpga_agilex_socdk_nand.dtb \
+				socfpga_agilex7f_socdk_pcie_root_port.dtb \
 				socfpga_agilex5_socdk.dtb \
 				socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
new file mode 100644
index 000000000000..19b14f88e32d
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+#include "socfpga_agilex_pcie_root_port.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex SoCDK";
+	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <900>; /* 0ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+	clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+	status = "okay";
+};
+
+&pcie_0_msi_irq {
+	status = "okay";
+};
+
+&pcie_0_pcie_aglx {
+	compatible = "altr,pcie-root-port-3.0-p-tile";
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x04200000>;
+			};
+
+			root: partition@4200000 {
+				label = "Root Filesystem - UBIFS";
+				reg = <0x04200000 0x0BE00000>;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
-- 
2.34.1

Re: [PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port

[Krzysztof Kozlowski]

On Sat, Feb 15, 2025 at 09:53:58AM -0600, Matthew Gerlach wrote:
> Add a device tree enabling PCIe Root Port support on an Agilex F-series
> Development Kit which has the P-tile variant of the PCIe IP.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> v7:
>  - Create and use appropriate board compatibility and use of model.
> 
> v6:
>  - Fix SPDX header.
>  - Make compatible property first.
>  - Fix comment line wrapping.
>  - Don't include .dts.
> 
> v3:
>  - Remove accepted patches from patch set.
> ---
>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>  .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
>  2 files changed, 148 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> 
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index d39cfb723f5b..737e81c3c3f7 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -2,6 +2,7 @@
>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>  				socfpga_agilex_socdk.dtb \
>  				socfpga_agilex_socdk_nand.dtb \
> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>  				socfpga_agilex5_socdk.dtb \
>  				socfpga_n5x_socdk.dtb
>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> new file mode 100644
> index 000000000000..19b14f88e32d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> @@ -0,0 +1,147 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2024, Intel Corporation
> + */
> +#include "socfpga_agilex.dtsi"
> +#include "socfpga_agilex_pcie_root_port.dtsi"
> +
> +/ {
> +	model = "SoCFPGA Agilex SoCDK";
> +	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";

So that's different SoC (Agilex F series)? Why isn't this expressed in
compatibles? Is it different or the same board? If different, why
"root-port" in board name? Is this how the product is named?

Best regards,
Krzysztof

Re: [PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port

[matthew.gerlach]

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:58AM -0600, Matthew Gerlach wrote:
>> Add a device tree enabling PCIe Root Port support on an Agilex F-series
>> Development Kit which has the P-tile variant of the PCIe IP.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v7:
>>  - Create and use appropriate board compatibility and use of model.
>>
>> v6:
>>  - Fix SPDX header.
>>  - Make compatible property first.
>>  - Fix comment line wrapping.
>>  - Don't include .dts.
>>
>> v3:
>>  - Remove accepted patches from patch set.
>> ---
>>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>>  .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
>>  2 files changed, 148 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
>> index d39cfb723f5b..737e81c3c3f7 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -2,6 +2,7 @@
>>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>>  				socfpga_agilex_socdk.dtb \
>>  				socfpga_agilex_socdk_nand.dtb \
>> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>>  				socfpga_agilex5_socdk.dtb \
>>  				socfpga_n5x_socdk.dtb
>>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> new file mode 100644
>> index 000000000000..19b14f88e32d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> @@ -0,0 +1,147 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2024, Intel Corporation
>> + */
>> +#include "socfpga_agilex.dtsi"
>> +#include "socfpga_agilex_pcie_root_port.dtsi"
>> +
>> +/ {
>> +	model = "SoCFPGA Agilex SoCDK";
>> +	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";
>
> So that's different SoC (Agilex F series)? Why isn't this expressed in
What was formally known as Agilex is now more precisely referred Agilex 7 
F series, Agilex 7 I series, or Agilex 7 M series. Yes, this should me 
reflected in the compatibles.

> compatibles? Is it different or the same board? If different, why
> "root-port" in board name? Is this how the product is named?

"root-port" refers to a particular board combined with a specific FPGA 
image and possibly a daughter card and cables. I am not sure that FPGA 
image specific DTS or DTSI should be in the kernel tree.

>
> Best regards,
> Krzysztof
>
>

Thanks for the feedback,
Matthew Gerlach

[PATCH v7 7/7] PCI: altera: Add Agilex support

[Matthew Gerlach]

From: "D M, Sharath Kumar" <sharath.kumar.d.m@intel.com>

Add PCIe root port controller support for the Agilex family of chips.
The Agilex PCIe IP has three variants that are mostly sw compatible,
except for a couple register offsets. The P-Tile variant supports
Gen3/Gen4 1x16. The F-Tile variant supports Gen3/Gen4 4x4, 4x8, and 4x16.
The R-Tile variant improves on the F-Tile variant by adding Gen5 support.

To simplify the implementation of pci_ops read/write functions,
ep_{read/write}_cfg() callbacks were added to struct altera_pci_ops
to easily distinguish between hardware variants.

Signed-off-by: D M, Sharath Kumar <sharath.kumar.d.m@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
v6:
 - Removed duplicate Signed-off-by:
 - Add Reviewed-by: Manivannan Sadhasivam.

v5:
 - remove unnecessary !!
 - Improve macro usage to make comment unnecessary.

v4:
 - Add info to commit message.
 - Use {read/write}?_relaxed where appropriate.
 - Use BIT(12) instead of (1 << 12).
 - Clear IRQ before handling it.
 - add interrupt number to unexpected IRQ messge.

v3:
 - Remove accepted patches from patch set.

v2:
 - Match historical style of subject.
 - Remove unrelated changes.
 - Fix indentation.
---
 drivers/pci/controller/pcie-altera.c | 253 ++++++++++++++++++++++++++-
 1 file changed, 244 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
index eb55a7f8573a..42ea9960b9da 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -6,6 +6,7 @@
  * Description: Altera PCIe host controller driver
  */
 
+#include <linux/bitfield.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip/chained_irq.h>
@@ -77,9 +78,25 @@
 #define S10_TLP_FMTTYPE_CFGWR0		0x45
 #define S10_TLP_FMTTYPE_CFGWR1		0x44
 
+#define AGLX_RP_CFG_ADDR(pcie, reg)	(((pcie)->hip_base) + (reg))
+#define AGLX_RP_SECONDARY(pcie)		\
+	readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
+
+#define AGLX_BDF_REG			0x00002004
+#define AGLX_ROOT_PORT_IRQ_STATUS	0x14c
+#define AGLX_ROOT_PORT_IRQ_ENABLE	0x150
+#define CFG_AER				BIT(4)
+
+#define AGLX_CFG_TARGET			GENMASK(13, 12)
+#define AGLX_CFG_TARGET_TYPE0		0
+#define AGLX_CFG_TARGET_TYPE1		1
+#define AGLX_CFG_TARGET_LOCAL_2000	2
+#define AGLX_CFG_TARGET_LOCAL_3000	3
+
 enum altera_pcie_version {
 	ALTERA_PCIE_V1 = 0,
 	ALTERA_PCIE_V2,
+	ALTERA_PCIE_V3,
 };
 
 struct altera_pcie {
@@ -102,6 +119,11 @@ struct altera_pcie_ops {
 			   int size, u32 *value);
 	int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
 			    int where, int size, u32 value);
+	int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno,
+			   unsigned int devfn, int where, int size, u32 *value);
+	int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno,
+			    unsigned int devfn, int where, int size, u32 value);
+	void (*rp_isr)(struct irq_desc *desc);
 };
 
 struct altera_pcie_data {
@@ -112,6 +134,9 @@ struct altera_pcie_data {
 	u32 cfgrd1;
 	u32 cfgwr0;
 	u32 cfgwr1;
+	u32 port_conf_offset;
+	u32 port_irq_status_offset;
+	u32 port_irq_enable_offset;
 };
 
 struct tlp_rp_regpair_t {
@@ -131,6 +156,28 @@ static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
 	return readl_relaxed(pcie->cra_base + reg);
 }
 
+static inline void cra_writew(struct altera_pcie *pcie, const u32 value,
+			      const u32 reg)
+{
+	writew_relaxed(value, pcie->cra_base + reg);
+}
+
+static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg)
+{
+	return readw_relaxed(pcie->cra_base + reg);
+}
+
+static inline void cra_writeb(struct altera_pcie *pcie, const u32 value,
+			      const u32 reg)
+{
+	writeb_relaxed(value, pcie->cra_base + reg);
+}
+
+static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg)
+{
+	return readb_relaxed(pcie->cra_base + reg);
+}
+
 static bool altera_pcie_link_up(struct altera_pcie *pcie)
 {
 	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
@@ -145,6 +192,15 @@ static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
 	return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
 }
 
+static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie,
+				   pcie->pcie_data->cap_offset +
+				   PCI_EXP_LNKSTA);
+
+	return (readw_relaxed(addr) & PCI_EXP_LNKSTA_DLLLA);
+}
+
 /*
  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
@@ -425,6 +481,103 @@ static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
 	return PCIBIOS_SUCCESSFUL;
 }
 
+static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where,
+			    int size, u32 *value)
+{
+	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
+
+	switch (size) {
+	case 1:
+		*value = readb_relaxed(addr);
+		break;
+	case 2:
+		*value = readw_relaxed(addr);
+		break;
+	default:
+		*value = readl_relaxed(addr);
+		break;
+	}
+
+	/* interrupt pin not programmed in hardware, set to INTA */
+	if (where == PCI_INTERRUPT_PIN && size == 1 && !(*value))
+		*value = 0x01;
+	else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))
+		*value |= 0x0100;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int aglx_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
+			     int where, int size, u32 value)
+{
+	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);
+
+	switch (size) {
+	case 1:
+		writeb_relaxed(value, addr);
+		break;
+	case 2:
+		writew_relaxed(value, addr);
+		break;
+	default:
+		writel_relaxed(value, addr);
+		break;
+	}
+
+	/*
+	 * Monitor changes to PCI_PRIMARY_BUS register on root port
+	 * and update local copy of root bus number accordingly.
+	 */
+	if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
+		pcie->root_bus_nr = value & 0xff;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int aglx_ep_write_cfg(struct altera_pcie *pcie, u8 busno,
+			     unsigned int devfn, int where, int size, u32 value)
+{
+	cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
+	if (busno > AGLX_RP_SECONDARY(pcie))
+		where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1);
+
+	switch (size) {
+	case 1:
+		cra_writeb(pcie, value, where);
+		break;
+	case 2:
+		cra_writew(pcie, value, where);
+		break;
+	default:
+		cra_writel(pcie, value, where);
+			break;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int aglx_ep_read_cfg(struct altera_pcie *pcie, u8 busno,
+			    unsigned int devfn, int where, int size, u32 *value)
+{
+	cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);
+	if (busno > AGLX_RP_SECONDARY(pcie))
+		where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1);
+
+	switch (size) {
+	case 1:
+		*value = cra_readb(pcie, where);
+		break;
+	case 2:
+		*value = cra_readw(pcie, where);
+		break;
+	default:
+		*value = cra_readl(pcie, where);
+		break;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 				 unsigned int devfn, int where, int size,
 				 u32 *value)
@@ -437,6 +590,10 @@ static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 		return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
 							 size, value);
 
+	if (pcie->pcie_data->ops->ep_read_cfg)
+		return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, devfn,
+							where, size, value);
+
 	switch (size) {
 	case 1:
 		byte_en = 1 << (where & 3);
@@ -481,6 +638,10 @@ static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
 		return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
 						     where, size, value);
 
+	if (pcie->pcie_data->ops->ep_write_cfg)
+		return pcie->pcie_data->ops->ep_write_cfg(pcie, busno, devfn,
+						     where, size, value);
+
 	switch (size) {
 	case 1:
 		data32 = (value & 0xff) << shift;
@@ -659,7 +820,30 @@ static void altera_pcie_isr(struct irq_desc *desc)
 				dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
 		}
 	}
+	chained_irq_exit(chip, desc);
+}
+
+static void aglx_isr(struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct altera_pcie *pcie;
+	struct device *dev;
+	u32 status;
+	int ret;
+
+	chained_irq_enter(chip, desc);
+	pcie = irq_desc_get_handler_data(desc);
+	dev = &pcie->pdev->dev;
 
+	status = readl(pcie->hip_base + pcie->pcie_data->port_conf_offset +
+		       pcie->pcie_data->port_irq_status_offset);
+	if (status & CFG_AER) {
+		writel(CFG_AER, (pcie->hip_base + pcie->pcie_data->port_conf_offset +
+				 pcie->pcie_data->port_irq_status_offset));
+		ret = generic_handle_domain_irq(pcie->irq_domain, 0);
+		if (ret)
+			dev_err_ratelimited(dev, "unexpected IRQ %d\n", pcie->irq);
+	}
 	chained_irq_exit(chip, desc);
 }
 
@@ -694,9 +878,9 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 	if (IS_ERR(pcie->cra_base))
 		return PTR_ERR(pcie->cra_base);
 
-	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
-		pcie->hip_base =
-			devm_platform_ioremap_resource_byname(pdev, "Hip");
+	if (pcie->pcie_data->version == ALTERA_PCIE_V2 ||
+	    pcie->pcie_data->version == ALTERA_PCIE_V3) {
+		pcie->hip_base = devm_platform_ioremap_resource_byname(pdev, "Hip");
 		if (IS_ERR(pcie->hip_base))
 			return PTR_ERR(pcie->hip_base);
 	}
@@ -706,7 +890,7 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 	if (pcie->irq < 0)
 		return pcie->irq;
 
-	irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
+	irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr, pcie);
 	return 0;
 }
 
@@ -719,6 +903,7 @@ static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
 	.tlp_read_pkt = tlp_read_packet,
 	.tlp_write_pkt = tlp_write_packet,
 	.get_link_status = altera_pcie_link_up,
+	.rp_isr = altera_pcie_isr,
 };
 
 static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
@@ -727,6 +912,16 @@ static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
 	.get_link_status = s10_altera_pcie_link_up,
 	.rp_read_cfg = s10_rp_read_cfg,
 	.rp_write_cfg = s10_rp_write_cfg,
+	.rp_isr = altera_pcie_isr,
+};
+
+static const struct altera_pcie_ops altera_pcie_ops_3_0 = {
+	.rp_read_cfg = aglx_rp_read_cfg,
+	.rp_write_cfg = aglx_rp_write_cfg,
+	.get_link_status = aglx_altera_pcie_link_up,
+	.ep_read_cfg = aglx_ep_read_cfg,
+	.ep_write_cfg = aglx_ep_write_cfg,
+	.rp_isr = aglx_isr,
 };
 
 static const struct altera_pcie_data altera_pcie_1_0_data = {
@@ -749,11 +944,44 @@ static const struct altera_pcie_data altera_pcie_2_0_data = {
 	.cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
 };
 
+static const struct altera_pcie_data altera_pcie_3_0_f_tile_data = {
+	.ops = &altera_pcie_ops_3_0,
+	.version = ALTERA_PCIE_V3,
+	.cap_offset = 0x70,
+	.port_conf_offset = 0x14000,
+	.port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS,
+	.port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE,
+};
+
+static const struct altera_pcie_data altera_pcie_3_0_p_tile_data = {
+	.ops = &altera_pcie_ops_3_0,
+	.version = ALTERA_PCIE_V3,
+	.cap_offset = 0x70,
+	.port_conf_offset = 0x104000,
+	.port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS,
+	.port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE,
+};
+
+static const struct altera_pcie_data altera_pcie_3_0_r_tile_data = {
+	.ops = &altera_pcie_ops_3_0,
+	.version = ALTERA_PCIE_V3,
+	.cap_offset = 0x70,
+	.port_conf_offset = 0x1300,
+	.port_irq_status_offset = 0x0,
+	.port_irq_enable_offset = 0x4,
+};
+
 static const struct of_device_id altera_pcie_of_match[] = {
 	{.compatible = "altr,pcie-root-port-1.0",
 	 .data = &altera_pcie_1_0_data },
 	{.compatible = "altr,pcie-root-port-2.0",
 	 .data = &altera_pcie_2_0_data },
+	{.compatible = "altr,pcie-root-port-3.0-f-tile",
+	 .data = &altera_pcie_3_0_f_tile_data },
+	{.compatible = "altr,pcie-root-port-3.0-p-tile",
+	 .data = &altera_pcie_3_0_p_tile_data },
+	{.compatible = "altr,pcie-root-port-3.0-r-tile",
+	 .data = &altera_pcie_3_0_r_tile_data },
 	{},
 };
 
@@ -791,11 +1019,18 @@ static int altera_pcie_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	/* clear all interrupts */
-	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
-	/* enable all interrupts */
-	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
-	altera_pcie_host_init(pcie);
+	if (pcie->pcie_data->version == ALTERA_PCIE_V1 ||
+	    pcie->pcie_data->version == ALTERA_PCIE_V2) {
+		/* clear all interrupts */
+		cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
+		/* enable all interrupts */
+		cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
+		altera_pcie_host_init(pcie);
+	} else if (pcie->pcie_data->version == ALTERA_PCIE_V3) {
+		writel(CFG_AER,
+		       pcie->hip_base + pcie->pcie_data->port_conf_offset +
+		       pcie->pcie_data->port_irq_enable_offset);
+	}
 
 	bridge->sysdata = pcie;
 	bridge->busnr = pcie->root_bus_nr;
-- 
2.34.1