Re: [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered

["Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>]

On 26-10-2026 11:35 am, Riana Tauro wrote:
> On systems lacking RAS capability, only PCIe errors are reported, via
> AER, not device errors. Non-fatal PCIe errors reported at the Upstream
> Switch Port (USP) have no impact on link or device state, so treat
> them as recovered without requiring a secondary bus reset (SBR).
>
> Fixes: 25913a062cd4 ("drm/xe/xe_ras: Add support for uncorrectable core-compute errors")
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_ras.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index e6a0ee468b17..2b1a7cb01b0d 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -747,7 +747,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
>   	}
>   
>   	if (!xe->info.has_sysctrl)
> -		return XE_RAS_RECOVERY_ACTION_RESET;

Initially we see Non-fatal PCIe errors reporting via USP required SBR, 
however what is rationale behind,  not required SBR now?

Thanks,

-/Mallesh

> +		return XE_RAS_RECOVERY_ACTION_RECOVERED;
>   
>   	BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
>   	/* Default action */