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From: Ana Bobillo <anabobillo3@gmail.com>
To: u-boot@lists.u-boot-project.org
Cc: "Tom Rini" <trini@konsulko.com>,
	"Anatolij Gustschin" <ag.dev.uboot@gmail.com>,
	"Simon Glass" <sjg@chromium.org>,
	"Kever Yang" <kever.yang@rock-chips.com>,
	"Quentin Schulz" <u-boot@0leil.net>,
	"Andre Przywara" <andre.przywara@arm.com>,
	"Thierry Reding" <treding@nvidia.com>,
	"Svyatoslav Ryhel" <clamor95@gmail.com>,
	"Tom Warren" <twarren@nvidia.com>,
	"Patrick Delaunay" <patrick.delaunay@foss.st.com>,
	"Patrice Chotard" <patrice.chotard@foss.st.com>,
	uboot-stm32@st-md-mailman.stormreply.com,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Jonas Schwöbel" <jonasschwoebel@yahoo.de>
Subject: [PATCH 10/11] video: rockchip: edp: Limit the lane count to four
Date: Mon, 09 Nov 2026 17:30:04 +0000	[thread overview]
Message-ID: <2a110264-af9c-4bba-bcef-6efc436f63c8@gmail.com> (raw)
In-Reply-To: <2399d63c-ddd0-44b0-bb81-d5d9d2a8a8b4@gmail.com>

From: Ana Bobillo <anabobillo3@gmail.com>

rk_edp_init_training() takes the lane count from the sink's
MAX_LANE_COUNT DPCD register, masked to 5 bits, and link training uses
it to index the four ln_link_trn_ctl[] registers, the four-entry
train_set[] and the link status read from the sink. A sink reporting
more than four lanes makes rk_edp_set_link_training() write past those
registers into the ones after them, and the training loops read past
train_set[] and the link status buffer.

Limit the lane count to the four lanes the controller has, as the
analogix_dp driver in Linux does.

Fixes: 5852d539eab0 ("rockchip: video: Add a display driver for rockchip eDP")
Signed-off-by: Ana Bobillo <anabobillo3@gmail.com>
---
 drivers/video/rockchip/rk_edp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 0ba68dbce3d..85c201e8809 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -646,6 +646,10 @@ static int rk_edp_init_training(struct rk_edp_priv *edp)
 		return -EPERM;
 	}
 
+	/* The sink may report more lanes than the controller has */
+	if (edp->link_train.lane_count > LANE_CNT4)
+		edp->link_train.lane_count = LANE_CNT4;
+
 	ret = rk_edp_link_power_up(edp);
 	if (ret)
 		return ret;

  parent reply	other threads:[~2026-11-09 17:30 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-09 17:28 [PATCH 00/11] video: Keep EDID modes and DP lane counts within what is reserved Ana Bobillo
2026-11-09 17:28 ` [PATCH 01/11] configs: stm32mp23/stm32mp25: Size the frame buffer for the LVDS panel Ana Bobillo
2026-11-12  8:46   ` Patrice CHOTARD
2026-11-09 17:29 ` [PATCH 02/11] video: Check that the mode fits in the reserved frame buffer Ana Bobillo
2026-11-09 17:29 ` [PATCH 03/11] edid: Leave the timing alone when no mode is valid Ana Bobillo
2026-11-09 18:16   ` Tom Rini
2026-11-09 19:28     ` Ana Bobillo
2026-11-09 17:29 ` [PATCH 04/11] video: display: Skip modes which do not fit in the source frame buffer Ana Bobillo
2026-11-10  8:41   ` Svyatoslav Ryhel
2026-11-09 17:29 ` [PATCH 05/11] video: rockchip: vop: Tell the display the frame buffer size Ana Bobillo
2026-11-09 18:30   ` Tom Rini
2026-11-09 19:28     ` Ana Bobillo
2026-11-09 17:29 ` [PATCH 06/11] video: sunxi: de2: " Ana Bobillo
2026-11-09 18:21   ` Tom Rini
2026-11-09 19:28     ` Ana Bobillo
2026-11-09 19:44       ` Tom Rini
2026-11-09 17:29 ` [PATCH 07/11] video: tegra124: " Ana Bobillo
2026-11-09 17:29 ` [PATCH 08/11] sunxi: display: Skip EDID modes larger than the frame buffer Ana Bobillo
2026-11-09 17:29 ` [PATCH 09/11] video: tegra: hdmi: Skip modes larger than the DC " Ana Bobillo
2026-11-10  8:46   ` Svyatoslav Ryhel
2026-11-09 17:30 ` Ana Bobillo [this message]
2026-11-09 17:30 ` [PATCH 11/11] video: tegra124: dp: Limit the lane count to four Ana Bobillo
2026-11-10  8:51   ` Svyatoslav Ryhel
2026-11-10 18:01 ` [PATCH 00/11] video: Keep EDID modes and DP lane counts within what is reserved Tom Rini
2026-11-10 18:16   ` Ana Bobillo
2026-11-10 18:24     ` Tom Rini

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