[PATCH 11/11] video: tegra124: dp: Limit the lane count to four

[Ana Bobillo <anabobillo3@gmail.com>]

From: Ana Bobillo <anabobillo3@gmail.com>

tegra_dc_dp_init_max_link_cfg() takes the lane count from the sink's
MAX_LANE_COUNT DPCD register, masked to 5 bits, and link training uses
it to fill the four-entry pe[], vs[] and pc[] arrays on the stack. A
sink reporting more than four lanes makes tegra_dp_lt_adjust() write
past them.

Limit the lane count to the four lanes the SOR has.

Fixes: 59dd5aa8fa51 ("tegra: video: Add Embedded DisplayPort driver")
Signed-off-by: Ana Bobillo <anabobillo3@gmail.com>
---
 drivers/video/tegra/tegra124/dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/video/tegra/tegra124/dp.c b/drivers/video/tegra/tegra124/dp.c
index 611bf2f81a6..22e9a4b15f7 100644
--- a/drivers/video/tegra/tegra124/dp.c
+++ b/drivers/video/tegra/tegra124/dp.c
@@ -664,6 +664,9 @@ static int tegra_dc_dp_init_max_link_cfg(
 	if (ret)
 		return ret;
 	link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK;
+	/* The sink may report more lanes than the SOR has */
+	if (link_cfg->max_lane_count > DP_MAX_LANE_COUNT_LANE_4)
+		link_cfg->max_lane_count = DP_MAX_LANE_COUNT_LANE_4;
 	link_cfg->tps3_supported = (dpcd_data &
 			DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0;