[PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Shawn Lin]

The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Hi Heiko,

This patch should be considered only after David's patch[1] is merged,
otherwise it breaks PCIe on RK3566/RK3568 due to clk_disable_unused().

[1] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#ma251be8ca9642eb3f2ffbe6494c905c805418b34

 drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 74eabf9..9556ddf 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -827,6 +827,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 3, GFLAGS),
 	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 4, GFLAGS),
+	GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", 0,
+			RK3568_CLKGATE_CON(12), 5, GFLAGS),
 	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(12), 8, GFLAGS),
 	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
@@ -837,6 +839,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 11, GFLAGS),
 	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 12, GFLAGS),
+	GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", 0,
+			RK3568_CLKGATE_CON(12), 13, GFLAGS),
 	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(13), 0, GFLAGS),
 	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
@@ -847,6 +851,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(13), 3, GFLAGS),
 	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(13), 4, GFLAGS),
+	GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", 0,
+			RK3568_CLKGATE_CON(13), 5, GFLAGS),
 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(11), 0, GFLAGS),
 	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
-- 
2.7.4


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Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Heiko Stuebner]

Hi Shawn,

Am Donnerstag, 5. März 2026, 09:06:51 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> Hi Heiko,
> 
> This patch should be considered only after David's patch[1] is merged,
> otherwise it breaks PCIe on RK3566/RK3568 due to clk_disable_unused().

This would also break compatiblity with old devicetrees.

The devicetree used by the kernel can also be embedded for example
in an already installed u-boot and handed to the kernel from there.
You cannot expect board devicetrees and the kernel image to be updated
in lockstep.

We also sort of guarantee this backwards compatiblity - old DTB with
newer kernel.

The solution is to add a CLK_IGNORE_UNUSED flag (but not CLK_IS_CRITICAL)
to the newly added gate.

This lets the clock stay and keeps the original behavious on old DTBs,
but also allows the PCIe driver in newer kernels to turn off the clock
if it wants to.

Thanks
Heiko

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Heiko Stuebner]

Hi Shawn,

Am Donnerstag, 5. März 2026, 09:06:51 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> Hi Heiko,
> 
> This patch should be considered only after David's patch[1] is merged,
> otherwise it breaks PCIe on RK3566/RK3568 due to clk_disable_unused().

This would also break compatiblity with old devicetrees.

The devicetree used by the kernel can also be embedded for example
in an already installed u-boot and handed to the kernel from there.
You cannot expect board devicetrees and the kernel image to be updated
in lockstep.

We also sort of guarantee this backwards compatiblity - old DTB with
newer kernel.

The solution is to add a CLK_IGNORE_UNUSED flag (but not CLK_IS_CRITICAL)
to the newly added gate.

This lets the clock stay and keeps the original behavious on old DTBs,
but also allows the PCIe driver in newer kernels to turn off the clock
if it wants to.

Thanks
Heiko




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Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Shawn Lin]

Hi Heiko,

在 2026/03/06 星期五 18:52, Heiko Stuebner 写道:
> Hi Shawn,
> 
> Am Donnerstag, 5. März 2026, 09:06:51 Mitteleuropäische Normalzeit schrieb Shawn Lin:
>> The PCIe pipe clocks are currently left as orphan clocks and remain
>> enabled indefinitely, which is suboptimal. Add the missing clock gates
>> so the PCIe driver can explicitly manage them when not in use.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>> Hi Heiko,
>>
>> This patch should be considered only after David's patch[1] is merged,
>> otherwise it breaks PCIe on RK3566/RK3568 due to clk_disable_unused().
> 
> This would also break compatiblity with old devicetrees.
> 
> The devicetree used by the kernel can also be embedded for example
> in an already installed u-boot and handed to the kernel from there.
> You cannot expect board devicetrees and the kernel image to be updated
> in lockstep.

Indeed.

> 
> We also sort of guarantee this backwards compatiblity - old DTB with
> newer kernel.
> 
> The solution is to add a CLK_IGNORE_UNUSED flag (but not CLK_IS_CRITICAL)
> to the newly added gate.
> 

Thanks, will improve it.

> This lets the clock stay and keeps the original behavious on old DTBs,
> but also allows the PCIe driver in newer kernels to turn off the clock
> if it wants to.
> 
> Thanks
> Heiko
> 
> 
> 
> 

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Shawn Lin]

Hi Heiko,

在 2026/03/06 星期五 18:52, Heiko Stuebner 写道:
> Hi Shawn,
> 
> Am Donnerstag, 5. März 2026, 09:06:51 Mitteleuropäische Normalzeit schrieb Shawn Lin:
>> The PCIe pipe clocks are currently left as orphan clocks and remain
>> enabled indefinitely, which is suboptimal. Add the missing clock gates
>> so the PCIe driver can explicitly manage them when not in use.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>> Hi Heiko,
>>
>> This patch should be considered only after David's patch[1] is merged,
>> otherwise it breaks PCIe on RK3566/RK3568 due to clk_disable_unused().
> 
> This would also break compatiblity with old devicetrees.
> 
> The devicetree used by the kernel can also be embedded for example
> in an already installed u-boot and handed to the kernel from there.
> You cannot expect board devicetrees and the kernel image to be updated
> in lockstep.

Indeed.

> 
> We also sort of guarantee this backwards compatiblity - old DTB with
> newer kernel.
> 
> The solution is to add a CLK_IGNORE_UNUSED flag (but not CLK_IS_CRITICAL)
> to the newly added gate.
> 

Thanks, will improve it.

> This lets the clock stay and keeps the original behavious on old DTBs,
> but also allows the PCIe driver in newer kernels to turn off the clock
> if it wants to.
> 
> Thanks
> Heiko
> 
> 
> 
> 

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[PATCH] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

[Alexander Shiyan]

From: Miaoqian Lin <linmq006@gmail.com>

Replace NULL check with IS_ERR_OR_NULL() check after calling
rockchip_clk_register_gate_link() since this function
returns error pointers (ERR_PTR).

Fixes: c62fa612cfa6 ("clk: rockchip: implement linked gate clock support")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://patch.msgid.link/20250805030358.3665878-1-linmq006@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 987c3bc518..d01574c60b 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -566,7 +566,7 @@ void rockchip_clk_register_late_branches(struct device *dev,
 			break;
 		}
 
-		if (!pdev)
+		if (IS_ERR_OR_NULL(pdev))
 			dev_err(dev, "failed to register device for clock %s\n", list->name);
 	}
 }
-- 
2.52.0

[PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Alexander Shiyan]

From: Shawn Lin <shawn.lin@rock-chips.com>

The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use. In order
not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1772799641-32164-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 3b0cfdb865..12b3514afb 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -830,6 +830,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 3, GFLAGS),
 	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 4, GFLAGS),
+	GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(12), 5, GFLAGS),
 	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(12), 8, GFLAGS),
 	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
@@ -840,6 +842,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 11, GFLAGS),
 	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 12, GFLAGS),
+	GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(12), 13, GFLAGS),
 	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(13), 0, GFLAGS),
 	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
@@ -850,6 +854,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(13), 3, GFLAGS),
 	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(13), 4, GFLAGS),
+	GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(13), 5, GFLAGS),
 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(11), 0, GFLAGS),
 	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
-- 
2.52.0

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Sascha Hauer]

On Thu, 28 May 2026 15:15:31 +0300, Alexander Shiyan wrote:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use. In order
> not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.
> 
> 

Applied, thanks!

[1/1] clk: rockchip: rk3568: Add PCIe pipe clock gates
      https://git.pengutronix.de/cgit/barebox/commit/?id=28f3a11c9a73 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Sascha Hauer]

On Thu, 28 May 2026 15:15:31 +0300, Alexander Shiyan wrote:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use. In order
> not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.
> 
> 

Applied, thanks!

[1/1] clk: rockchip: rk3568: Add PCIe pipe clock gates
      https://git.pengutronix.de/cgit/barebox/commit/?id=28f3a11c9a73 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>