From: Jan Beulich <jbeulich@suse.com>
To: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
"Baptiste Le Duc" <baptiste.le-duc@vates.tech>,
"Zheng Zhang" <zhangzheng@iscas.ac.cn>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger@xenproject.org>,
"Stefano Stabellini" <sstabellini@kernel.org>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2 16/39] xen/riscv: extend exception tables with type and data fields
Date: Tue, 8 Sep 2026 15:44:11 +0200 [thread overview]
Message-ID: <39841f44-2b18-4368-a9f8-7c0db307ff6d@suse.com> (raw)
In-Reply-To: <8aef9dfabe1d485abe4c48fd7499e09dbd8e0c27.1787838835.git.oleksii.kurochko@gmail.com>
On 27.08.2026 17:21, Oleksii Kurochko wrote:
> @@ -59,7 +67,49 @@ static void ex_handler_fixup(const struct exception_table_entry *ex,
> regs->sepc = ex_fixup(ex);
> }
>
> -bool fixup_exception(struct cpu_user_regs *regs)
> +#define CHECK_GPR_INDEX(num, name) \
> + BUILD_BUG_ON(offsetof(struct cpu_user_regs, name) \
> + != (num) * sizeof(unsigned long));
Nit: Placement of the !=. Also there should be no semicolon here; it wants
to ...
> +static unsigned long regs_get_gpr(const struct cpu_user_regs *regs,
> + unsigned int num)
> +{
> + /*
> + * The GPR number -> struct index mapping below relies on x0..x31 being
> + * laid out at the start of struct cpu_user_regs in architectural order,
> + * matching the register numbers GPR_LIST() hands to the assembler.
> + */
> + GPR_LIST(CHECK_GPR_INDEX)
... appear here instead, for this to actually look like a statement.
> + ASSERT(num < 32);
> +
> + return ((const unsigned long *)regs)[num];
What about release builds? You'd happily overrun the array there. Maybe
(ab)use array_index_nospec() here?
> +}
> +
> +#undef CHECK_GPR_INDEX
If the sole use of the macro is in a single function, it wants #define-ing
(and #undef-ing) there, not outside of it.
> +static void ex_handler_trap_info(const struct exception_table_entry *ex,
> + struct cpu_user_regs *regs,
> + unsigned long cause)
> +{
> + struct trap_info *trap_info =
> + (struct trap_info *)regs_get_gpr(regs, ex->data);
> +
> + BUG_ON(!trap_info);
This feels extremely weak. As you're fetching from a GPR, the majority of
possible values stored in GPRs is going to be invalid, not just NULL. And
while the accesses below would trap on NULL anyway, whether other bogus
values would trap is pretty hard to predict. If trap_info is expected to
always live on the stack, why not check for that (perhaps also check that
the low few bits are clear)?
> @@ -23,20 +30,36 @@
>
> struct cpu_user_regs;
>
> -#define ASM_EXTABLE(insn, fixup) \
> - ".pushsection .ex_table, \"a\"\n" \
> - ".balign 4\n" \
> - ".word (" #insn " - .)\n" \
> - ".word (" #fixup " - .)\n" \
> +#define ASM_EXTABLE_RAW(insn, fixup, type, data) \
> + ".pushsection .ex_table, \"a\"\n" \
> + ".balign 4\n" \
> + ".word (" insn ") - .\n" \
> + ".word (" fixup ") - .\n" \
> + ".half (" type ")\n" \
> + ".half (" data ")\n" \
> ".popsection\n"
>
> +#define ASM_EXTABLE(insn, fixup) \
> + ASM_EXTABLE_RAW(#insn, #fixup, __stringify(EX_TYPE_FIXUP), "0")
> +
> +#define EX_TRAP_INFO_REG(gpr) \
> + "(.L_gpr_num_" #gpr ")"
This doesn't need to be wrapped across lines, does it?
> +#define ASM_EXTABLE_TRAP_INFO(insn, fixup, data) \
> + DEFINE_ASM_GPR_NUMS \
> + ASM_EXTABLE_RAW(#insn, #fixup, __stringify(EX_TYPE_TRAP_INFO), \
> + EX_TRAP_INFO_REG(data))
There's no visible statement separator between DEFINE_ASM_GPR_NUMS and
ASM_EXTABLE_RAW(), which only works because DEFINE_ASM_GPR_NUMS appends
a separator also at the very end of its expansion. I think that better
would be changed, such that at use sites such as this one a separator
becomes mandatory.
> /*
> - * The exception table consists of pairs of relative offsets: the first
> - * is the relative offset to an instruction that is allowed to fault,
> - * and the second is the relative offset at which the program should
> - * continue. No general-purpose registers are modified by the exception
> - * handling mechanism itself, so it is up to the fixup code to handle
> - * any necessary state cleanup.
> + * Each exception table entry consists of two relative offsets and a
> + * handler description: `insn` is the relative offset to an instruction
> + * that is allowed to fault, `fixup` is the relative offset at which the
> + * program should continue,
"... in case of a fault, ..."
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/gpr-num.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef RISCV_GPR_NUM_H
> +#define RISCV_GPR_NUM_H
> +
> +/*
> + * GPRs by ABI name, together with their register number (x0 .. x31).
> + *
> + * This is the single source of truth for the mapping:
True until here, but ...
> it generates the
> + * .L_gpr_num_<name> assembler symbols
... no, it doesn't. It's ...
> used to turn a register name emitted
> + * by the compiler into a register number, and struct cpu_user_regs is
> + * checked against it at build time (see regs_get_gpr()). Neither list can
> + * therefore be changed without the other.
> + */
> +#define GPR_LIST(x) \
> + x(0, zero) x(1, ra) x(2, sp) x(3, gp) \
> + x(4, tp) x(5, t0) x(6, t1) x(7, t2) \
> + x(8, s0) x(9, s1) x(10, a0) x(11, a1) \
> + x(12, a2) x(13, a3) x(14, a4) x(15, a5) \
> + x(16, a6) x(17, a7) x(18, s2) x(19, s3) \
> + x(20, s4) x(21, s5) x(22, s6) x(23, s7) \
> + x(24, s8) x(25, s9) x(26, s10) x(27, s11) \
> + x(28, t3) x(29, t4) x(30, t5) x(31, t6)
> +
> +#ifdef __ASSEMBLER__
> +
> +#define GPR_NUM_EQU(num, name) .equ .L_gpr_num_##name, num;
> +GPR_LIST(GPR_NUM_EQU)
> +#undef GPR_NUM_EQU
... this construct which does. This is relevant to separate, since
GPR_LIST() is also used elsewhere.
> --- a/xen/arch/riscv/include/asm/processor.h
> +++ b/xen/arch/riscv/include/asm/processor.h
> @@ -12,7 +12,19 @@
>
> #ifndef __ASSEMBLER__
>
> -/* On stack VCPU state */
> +/*
> + * On stack VCPU state.
> + *
> + * x0..x31 must remain at the start of this structure, in architectural
> + * register-number order:
I understand that the order need retaining. But why would it being at the
start of the struct be (overly) relevant? You could use the "zero" field
as the anchor for calculations.
Jan
next prev parent reply other threads:[~2026-09-08 13:44 UTC|newest]
Thread overview: 163+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 15:20 [PATCH v2 00/39] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 01/39] xen/riscv: drop pregs from struct cpu_user_regs Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 6:58 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 02/39] xen/riscv: drop bug.h's duplicate instruction length helpers Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:01 ` Jan Beulich
2026-09-02 10:48 ` Oleksii Kurochko
2026-09-02 13:02 ` Jan Beulich
2026-09-02 13:45 ` Oleksii Kurochko
2026-09-02 14:27 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 03/39] xen/riscv: set the guest's XLEN explicitly in hstatus.VSXL Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:03 ` Jan Beulich
2026-09-01 8:40 ` Oleksii Kurochko
2026-09-01 15:16 ` Jan Beulich
2026-09-01 15:20 ` Jan Beulich
2026-09-02 11:42 ` Oleksii Kurochko
2026-09-02 13:07 ` Jan Beulich
2026-09-02 13:29 ` Oleksii Kurochko
2026-09-02 14:31 ` Jan Beulich
2026-09-02 15:17 ` Oleksii Kurochko
2026-09-02 15:56 ` Oleksii Kurochko
2026-09-02 17:45 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 04/39] xen/riscv: introduce csr_read64() Oleksii Kurochko
2026-08-27 15:36 ` Andrew Cooper
2026-08-31 12:42 ` Oleksii Kurochko
2026-09-01 7:07 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 05/39] xen/riscv: request a G-stage flush on vmenter when VMIDs are disabled Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 8:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 06/39] xen/riscv: use UINT64_MAX to disable the VS-timer Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:12 ` Jan Beulich
2026-09-01 8:47 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 07/39] xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-01 15:53 ` Jan Beulich
2026-09-02 13:22 ` Jan Beulich
2026-09-02 13:52 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 08/39] xen/riscv: introduce device-agnostic MMIO emulation dispatch Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-03 10:28 ` Oleksii Kurochko
2026-09-09 13:24 ` Jan Beulich
2026-09-09 14:04 ` Oleksii Kurochko
2026-09-09 14:32 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 09/39] xen/riscv: implement virtual APLIC MMIO emulation Oleksii Kurochko
2026-09-02 11:51 ` Baptiste Le Duc
2026-09-04 11:58 ` Oleksii Kurochko
2026-09-04 12:03 ` Jan Beulich
2026-09-02 12:31 ` Baptiste Le Duc
2026-09-04 14:02 ` Oleksii Kurochko
2026-09-09 14:26 ` Jan Beulich
2026-09-10 10:37 ` Oleksii Kurochko
2026-09-10 11:14 ` Jan Beulich
2026-09-10 14:24 ` Oleksii Kurochko
2026-09-12 8:50 ` SeungJu Cheon
2026-08-27 15:20 ` [PATCH v2 10/39] xen/riscv: build the target hart index via aplic_hart_field() Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 14:28 ` Oleksii Kurochko
2026-09-09 14:51 ` Jan Beulich
2026-09-09 14:52 ` Jan Beulich
2026-09-10 10:59 ` Oleksii Kurochko
2026-09-10 11:23 ` Jan Beulich
2026-09-10 12:44 ` Oleksii Kurochko
2026-09-10 12:57 ` Jan Beulich
2026-09-11 9:47 ` Oleksii Kurochko
2026-09-10 11:23 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 11/39] xen/riscv: add helper to check APLIC MSI mode Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-09 14:53 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 12/39] xen/riscv: implement vCPU context switching Oleksii Kurochko
2026-09-02 14:42 ` Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 8:33 ` Jan Beulich
2026-09-04 9:54 ` Baptiste Le Duc
2026-09-04 14:55 ` Oleksii Kurochko
2026-09-07 8:17 ` Jan Beulich
2026-09-08 9:06 ` Oleksii Kurochko
2026-09-05 7:25 ` Oleksii Kurochko
2026-09-10 13:29 ` Jan Beulich
2026-09-11 10:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 13/39] xen/riscv: save and restore AIA state on vCPU context switch Oleksii Kurochko
2026-09-04 9:52 ` Baptiste Le Duc
2026-09-04 16:40 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 14/39] xen/riscv: introduce vintc_ctxt_switch_{from,to}() Oleksii Kurochko
2026-09-04 11:25 ` Baptiste Le Duc
2026-09-04 16:54 ` Oleksii Kurochko
2026-09-10 14:54 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 15/39] xen/riscv: add IMSIC vCPU context switch handlers Oleksii Kurochko
2026-09-04 11:33 ` Baptiste Le Duc
2026-09-04 16:56 ` Oleksii Kurochko
2026-09-10 14:57 ` Jan Beulich
2026-09-11 11:19 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 16/39] xen/riscv: extend exception tables with type and data fields Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 6:06 ` Jan Beulich
2026-09-08 8:18 ` Baptiste Le Duc
2026-09-08 9:19 ` Oleksii Kurochko
2026-09-08 16:26 ` Baptiste Le Duc
2026-09-08 13:44 ` Jan Beulich [this message]
2026-09-09 11:20 ` Oleksii Kurochko
2026-09-09 12:22 ` Jan Beulich
2026-09-09 12:42 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 17/39] xen/riscv: decouple INSN_PSEUDO_VS_* from the hypervisor's XLEN Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:34 ` Oleksii Kurochko
2026-09-08 16:04 ` Baptiste Le Duc
2026-09-09 12:57 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 18/39] xen/riscv: add guest page fault handling stub Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:49 ` Oleksii Kurochko
2026-09-08 14:10 ` Jan Beulich
2026-09-09 15:09 ` Oleksii Kurochko
2026-09-10 6:38 ` Jan Beulich
2026-09-11 11:47 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 19/39] xen/riscv: implement trap redirection to a guest Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:01 ` Oleksii Kurochko
2026-09-08 14:58 ` Oleksii Kurochko
2026-09-08 15:05 ` Jan Beulich
2026-09-08 15:47 ` Baptiste Le Duc
2026-09-08 15:58 ` Jan Beulich
2026-09-08 14:16 ` Jan Beulich
2026-09-08 14:16 ` Jan Beulich
2026-09-08 15:25 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 20/39] xen/riscv: detect Shtvala Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:15 ` Oleksii Kurochko
2026-09-08 15:49 ` Baptiste Le Duc
2026-08-27 15:21 ` [PATCH v2 21/39] xen/riscv: resolve the faulting guest physical address Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-11 12:56 ` Oleksii Kurochko
2026-09-10 15:06 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 22/39] xen/riscv: add guest memory read helper Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-10 15:19 ` Jan Beulich
2026-09-11 13:06 ` Oleksii Kurochko
2026-09-11 13:41 ` Oleksii Kurochko
2026-09-11 13:47 ` Jan Beulich
2026-09-11 13:50 ` Oleksii Kurochko
2026-09-10 15:28 ` Jan Beulich
2026-09-11 13:57 ` Oleksii Kurochko
2026-09-11 14:00 ` Jan Beulich
2026-09-11 14:29 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 23/39] xen/riscv: look up the exception table for any trap taken in Xen context Oleksii Kurochko
2026-09-10 15:31 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 24/39] xen/riscv: add helpers for decoding a trapped load or store Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 25/39] xen/riscv: add guest load emulation for trapped MMIO accesses Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 26/39] xen/riscv: add guest store " Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 27/39] xen/riscv: introduce arch_move_irqs() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 28/39] xen/riscv: handle the case when no vCPU migration is needed Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 29/39] xen/riscv: introduce aplic_reconfigure_target() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 30/39] xen/riscv: prepare new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 31/39] xen/riscv: implement APLIC-hart sync barrier for vCPU migration Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 32/39] xen/riscv: remap interrupts to new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 33/39] xen/riscv: dump old interrupt file to memory Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 34/39] xen/riscv: restore register state in the new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 35/39] xen/riscv: add basic VGEIN management for AIA guests Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 36/39] xen/riscv: wake up a descheduled vCPU on a guest external interrupt Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 37/39] xen/riscv: map IMSIC interrupt file for vCPUs Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 38/39] xen/riscv: implement continue_new_vcpu() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 39/39] xen/riscv: introduce IMSIC h/w interrupt file attaching to vcpu Oleksii Kurochko
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