From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
xen-devel@lists.xenproject.org
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
"Baptiste Le Duc" <baptiste.le-duc@vates.tech>,
"Zheng Zhang" <zhangzheng@iscas.ac.cn>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger@xenproject.org>,
"Stefano Stabellini" <sstabellini@kernel.org>
Subject: Re: [PATCH v2 04/39] xen/riscv: introduce csr_read64()
Date: Mon, 31 Aug 2026 14:42:32 +0200 [thread overview]
Message-ID: <91ffbf33-0b54-406f-b91f-1a96afc616d7@gmail.com> (raw)
In-Reply-To: <aded3bc6-6d5c-4c3f-879a-be428a8ad36a@citrix.com>
On 8/27/26 5:36 PM, Andrew Cooper wrote:
> On 27/08/2026 4:20 pm, Oleksii Kurochko wrote:
>> diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h
>> index 888d6a2a86d6..a5cdd6f99c8e 100644
>> --- a/xen/arch/riscv/include/asm/csr.h
>> +++ b/xen/arch/riscv/include/asm/csr.h
>> @@ -39,12 +39,36 @@
>> csr_write(csr, v_); \
>> csr_write(csr ## H, v_ >> 32); \
>> })
>> +
>> +/*
>> + * The two halves are read by separate instructions, so a CSR which hardware
>> + * increments can carry from the low half into the high one in between,
>> + * yielding a value the CSR never held. Re-read the high half and retry the
>> + * sequence if it changed.
>> + */
>> +#define csr_read64(csr) \
>> +({ \
>> + uint32_t hi_, lo_; \
>> + \
>> + do { \
>> + hi_ = csr_read(csr ## H); \
>> + lo_ = csr_read(csr); \
>> + } while ( hi_ != csr_read(csr ## H) ); \
>> + \
>> + ((uint64_t)hi_ << 32) | lo_; \
>> +})
>
> This double reads H in the looping case. You want something more like:
>
> hi = csr_read();
> do {
> old = hi;
> lo = csr_read();
> } while ( (hi = csr_read()) != old );
Good point. I'll apply that.
>
>
> Still, this only matters for volatile CSRs, and is unnecessary in the
> general case. I'd suggest naming it csr_volatile_read64().
Yes, that makes sense. I will rename it to csr_volatile_read64().
> Most CSRs
> can use a simple split access.
I may have misunderstood you here, but wouldn't it still make sense to
have a macro covering the case where a register is 64-bit on RV32 yet
accessed through two CSRs? VSIE and VSIEH, for example.
My plan was to use a single csr_read64() (but while loop then really
isn't needed in this case) call to abstract the access to VSIE, so that
the code looks the same on RV32 and RV64.
Does that make sense, or would it be better to have separate vsie and
vsieh fields instead?
~ Oleksii
next prev parent reply other threads:[~2026-08-31 12:42 UTC|newest]
Thread overview: 163+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 15:20 [PATCH v2 00/39] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 01/39] xen/riscv: drop pregs from struct cpu_user_regs Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 6:58 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 02/39] xen/riscv: drop bug.h's duplicate instruction length helpers Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:01 ` Jan Beulich
2026-09-02 10:48 ` Oleksii Kurochko
2026-09-02 13:02 ` Jan Beulich
2026-09-02 13:45 ` Oleksii Kurochko
2026-09-02 14:27 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 03/39] xen/riscv: set the guest's XLEN explicitly in hstatus.VSXL Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:03 ` Jan Beulich
2026-09-01 8:40 ` Oleksii Kurochko
2026-09-01 15:16 ` Jan Beulich
2026-09-01 15:20 ` Jan Beulich
2026-09-02 11:42 ` Oleksii Kurochko
2026-09-02 13:07 ` Jan Beulich
2026-09-02 13:29 ` Oleksii Kurochko
2026-09-02 14:31 ` Jan Beulich
2026-09-02 15:17 ` Oleksii Kurochko
2026-09-02 15:56 ` Oleksii Kurochko
2026-09-02 17:45 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 04/39] xen/riscv: introduce csr_read64() Oleksii Kurochko
2026-08-27 15:36 ` Andrew Cooper
2026-08-31 12:42 ` Oleksii Kurochko [this message]
2026-09-01 7:07 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 05/39] xen/riscv: request a G-stage flush on vmenter when VMIDs are disabled Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 8:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 06/39] xen/riscv: use UINT64_MAX to disable the VS-timer Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:12 ` Jan Beulich
2026-09-01 8:47 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 07/39] xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-01 15:53 ` Jan Beulich
2026-09-02 13:22 ` Jan Beulich
2026-09-02 13:52 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 08/39] xen/riscv: introduce device-agnostic MMIO emulation dispatch Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-03 10:28 ` Oleksii Kurochko
2026-09-09 13:24 ` Jan Beulich
2026-09-09 14:04 ` Oleksii Kurochko
2026-09-09 14:32 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 09/39] xen/riscv: implement virtual APLIC MMIO emulation Oleksii Kurochko
2026-09-02 11:51 ` Baptiste Le Duc
2026-09-04 11:58 ` Oleksii Kurochko
2026-09-04 12:03 ` Jan Beulich
2026-09-02 12:31 ` Baptiste Le Duc
2026-09-04 14:02 ` Oleksii Kurochko
2026-09-09 14:26 ` Jan Beulich
2026-09-10 10:37 ` Oleksii Kurochko
2026-09-10 11:14 ` Jan Beulich
2026-09-10 14:24 ` Oleksii Kurochko
2026-09-12 8:50 ` SeungJu Cheon
2026-08-27 15:20 ` [PATCH v2 10/39] xen/riscv: build the target hart index via aplic_hart_field() Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 14:28 ` Oleksii Kurochko
2026-09-09 14:51 ` Jan Beulich
2026-09-09 14:52 ` Jan Beulich
2026-09-10 10:59 ` Oleksii Kurochko
2026-09-10 11:23 ` Jan Beulich
2026-09-10 12:44 ` Oleksii Kurochko
2026-09-10 12:57 ` Jan Beulich
2026-09-11 9:47 ` Oleksii Kurochko
2026-09-10 11:23 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 11/39] xen/riscv: add helper to check APLIC MSI mode Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-09 14:53 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 12/39] xen/riscv: implement vCPU context switching Oleksii Kurochko
2026-09-02 14:42 ` Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 8:33 ` Jan Beulich
2026-09-04 9:54 ` Baptiste Le Duc
2026-09-04 14:55 ` Oleksii Kurochko
2026-09-07 8:17 ` Jan Beulich
2026-09-08 9:06 ` Oleksii Kurochko
2026-09-05 7:25 ` Oleksii Kurochko
2026-09-10 13:29 ` Jan Beulich
2026-09-11 10:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 13/39] xen/riscv: save and restore AIA state on vCPU context switch Oleksii Kurochko
2026-09-04 9:52 ` Baptiste Le Duc
2026-09-04 16:40 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 14/39] xen/riscv: introduce vintc_ctxt_switch_{from,to}() Oleksii Kurochko
2026-09-04 11:25 ` Baptiste Le Duc
2026-09-04 16:54 ` Oleksii Kurochko
2026-09-10 14:54 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 15/39] xen/riscv: add IMSIC vCPU context switch handlers Oleksii Kurochko
2026-09-04 11:33 ` Baptiste Le Duc
2026-09-04 16:56 ` Oleksii Kurochko
2026-09-10 14:57 ` Jan Beulich
2026-09-11 11:19 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 16/39] xen/riscv: extend exception tables with type and data fields Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 6:06 ` Jan Beulich
2026-09-08 8:18 ` Baptiste Le Duc
2026-09-08 9:19 ` Oleksii Kurochko
2026-09-08 16:26 ` Baptiste Le Duc
2026-09-08 13:44 ` Jan Beulich
2026-09-09 11:20 ` Oleksii Kurochko
2026-09-09 12:22 ` Jan Beulich
2026-09-09 12:42 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 17/39] xen/riscv: decouple INSN_PSEUDO_VS_* from the hypervisor's XLEN Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:34 ` Oleksii Kurochko
2026-09-08 16:04 ` Baptiste Le Duc
2026-09-09 12:57 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 18/39] xen/riscv: add guest page fault handling stub Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:49 ` Oleksii Kurochko
2026-09-08 14:10 ` Jan Beulich
2026-09-09 15:09 ` Oleksii Kurochko
2026-09-10 6:38 ` Jan Beulich
2026-09-11 11:47 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 19/39] xen/riscv: implement trap redirection to a guest Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:01 ` Oleksii Kurochko
2026-09-08 14:58 ` Oleksii Kurochko
2026-09-08 15:05 ` Jan Beulich
2026-09-08 15:47 ` Baptiste Le Duc
2026-09-08 15:58 ` Jan Beulich
2026-09-08 14:16 ` Jan Beulich
2026-09-08 14:16 ` Jan Beulich
2026-09-08 15:25 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 20/39] xen/riscv: detect Shtvala Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:15 ` Oleksii Kurochko
2026-09-08 15:49 ` Baptiste Le Duc
2026-08-27 15:21 ` [PATCH v2 21/39] xen/riscv: resolve the faulting guest physical address Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-11 12:56 ` Oleksii Kurochko
2026-09-10 15:06 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 22/39] xen/riscv: add guest memory read helper Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-10 15:19 ` Jan Beulich
2026-09-11 13:06 ` Oleksii Kurochko
2026-09-11 13:41 ` Oleksii Kurochko
2026-09-11 13:47 ` Jan Beulich
2026-09-11 13:50 ` Oleksii Kurochko
2026-09-10 15:28 ` Jan Beulich
2026-09-11 13:57 ` Oleksii Kurochko
2026-09-11 14:00 ` Jan Beulich
2026-09-11 14:29 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 23/39] xen/riscv: look up the exception table for any trap taken in Xen context Oleksii Kurochko
2026-09-10 15:31 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 24/39] xen/riscv: add helpers for decoding a trapped load or store Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 25/39] xen/riscv: add guest load emulation for trapped MMIO accesses Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 26/39] xen/riscv: add guest store " Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 27/39] xen/riscv: introduce arch_move_irqs() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 28/39] xen/riscv: handle the case when no vCPU migration is needed Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 29/39] xen/riscv: introduce aplic_reconfigure_target() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 30/39] xen/riscv: prepare new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 31/39] xen/riscv: implement APLIC-hart sync barrier for vCPU migration Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 32/39] xen/riscv: remap interrupts to new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 33/39] xen/riscv: dump old interrupt file to memory Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 34/39] xen/riscv: restore register state in the new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 35/39] xen/riscv: add basic VGEIN management for AIA guests Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 36/39] xen/riscv: wake up a descheduled vCPU on a guest external interrupt Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 37/39] xen/riscv: map IMSIC interrupt file for vCPUs Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 38/39] xen/riscv: implement continue_new_vcpu() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 39/39] xen/riscv: introduce IMSIC h/w interrupt file attaching to vcpu Oleksii Kurochko
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