From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Baptiste Le Duc <baptiste.le-duc@vates.tech>
Cc: xen-devel@lists.xenproject.org,
"Romain Caritey" <Romain.Caritey@microchip.com>,
"Zheng Zhang" <zhangzheng@iscas.ac.cn>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger@xenproject.org>,
"Stefano Stabellini" <sstabellini@kernel.org>
Subject: Re: [PATCH v2 13/39] xen/riscv: save and restore AIA state on vCPU context switch
Date: Fri, 4 Sep 2026 18:40:07 +0200 [thread overview]
Message-ID: <a2c4fe44-28bf-4623-9446-b2ec1814bcbb@gmail.com> (raw)
In-Reply-To: <1788515561.8631fc262581453bbf619ec5b2062170.1a06bd5af1a000c4f3@vates.tech>
On 9/4/26 11:52 AM, Baptiste Le Duc wrote:
>> vsiselect and hviprio{1,2} are per-hart CSRs which a guest can change, so
>> they have to be part of the vCPU context:
> Where in the spec did you see that? Because in AIA spec section 6.3.1,
> it is written that "When vsiselect has a value in the range 0x30-0x3F,
> an attempt from VS-mode to access sireg (really vsireg) causes a virtual
> instruction exception" and this even when hstateen0.CSRIND is set as hstateen0
> just control whether a guest/S-mode is allowed to access a CSR (exactly
> as you described below).
Your understanding is correct, it was me who confused the things. Sorry
for that.
>
> Therefore, the hypervisor has two options to modify the priority of a
> major irq:
> - emulate the iprio array in software.
> - Use hviprio1/hviprio2 (only 10 irqs configurable).
>
> But the guest shouldn't be able to modify h CSRs at all, in any case, or
> I may have misunderstood a part of the spec.
>
> For the moment I don't see any catch of possible instruction exception
> in do_trap().
There is no such because we don't emulate range 0x30-0x3F. We don't have
such use cases now.
I think that I have to recheck what should be saved/restored now.
There is no need to save/restore CSR_HVIPRIO* during context switch as
we don't have support of handling of 0x30-0x3f. I will introduce that
later when we really will need that.
VSISELECT should be save/restored then only in this patch as we have
hstateen0.SMSTATEEN0_SVSLCT set so guest could change VSISELECT directly
so we need to store/restore.
Am I missing something?
With having only VSISELECT saved/restored in this patch I think the
commit message should be:
xen/riscv: save and restore vsiselect on vCPU context switch
vsiselect is a per-hart CSR which a guest changes on its own: when V=1,
VS-mode accesses to siselect are really accesses to vsiselect.
Architecturally a vCPU has to find there the value it last wrote, but as
long as the CSR isn't part of the vCPU context it finds whatever selector
the vCPU which ran on the hart before it left behind. A guest which writes
siselect, is descheduled and then reads sireg without rewriting siselect
therefore reaches a register it never selected, and it can also observe
another guest's selector value.
When Smstateen is implemented, access to vsiselect and vsireg is gated by
hstateen0.CSRIND (bit 60, SMSTATEEN0_SVSLCT in Xen's headers), and
v->arch.hstateen0 holds the bits vcpu_csr_init() ended up with. A clear
bit there covers the two cases in which the CSR has to be skipped:
- Xen didn't hand the guest access to it, so the guest can't have changed
the CSR and there is no state to preserve;
- M-mode denied the state altogether. Smstateen makes a bit which is zero
in mstateen0 read-only zero in hstateen0, and a zero bit in mstateen0
traps accesses from every privilege mode less privileged than M-mode,
HS-mode included, so Xen couldn't even read the CSR to save it.
Without Smstateen no bit controls access to the CSR, so it is saved and
restored whenever Ssaia is available.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes in v3:
- Update the commit message.
- Save and restore only VSISELECT.
---
Changes in v2:
- New patch.
---
diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c
index 0ad851ee0f5f..1085ef152b8b 100644
--- a/xen/arch/riscv/domain.c
+++ b/xen/arch/riscv/domain.c
@@ -327,6 +327,28 @@ int arch_domain_create(struct domain *d,
return rc;
}
+/*
+ * vsiselect is a per-hart CSR, but a guest changes it on its own: when
V=1,
+ * VS-mode accesses to siselect are really accesses to vsiselect. Hence
it is
+ * part of the vCPU context.
+ *
+ * When Smstateen is implemented, hstateen0.CSRIND (SMSTATEEN0_SVSLCT)
gates
+ * that access, and a bit staying clear in v->arch.hstateen0 (see
+ * vcpu_csr_init()) means either that the guest was never given access
to the
+ * CSR, and so can't have changed it, or that M-mode denied the state
+ * altogether, in which case the CSR can't be accessed from HS-mode either.
+ */
+static bool vcpu_can_access_vsiselect(const struct vcpu *v)
+{
+ if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) )
+ return false;
+
+ if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) )
+ return true;
+
+ return v->arch.hstateen0 & SMSTATEEN0_SVSLCT;
+}
+
static void save_csr_regs(struct vcpu *p)
{
/*
@@ -354,6 +376,9 @@ static void save_csr_regs(struct vcpu *p)
p->arch.vscause = csr_read(CSR_VSCAUSE);
p->arch.vstval = csr_read(CSR_VSTVAL);
p->arch.vsepc = csr_read(CSR_VSEPC);
+
+ if ( vcpu_can_access_vsiselect(p) )
+ p->arch.vsiselect = csr_read(CSR_VSISELECT);
}
static void restore_csr_regs(struct vcpu *n)
@@ -375,6 +400,9 @@ static void restore_csr_regs(struct vcpu *n)
csr_write(CSR_VSCAUSE, n->arch.vscause);
csr_write(CSR_VSTVAL, n->arch.vstval);
csr_write(CSR_VSEPC, n->arch.vsepc);
+
+ if ( vcpu_can_access_vsiselect(n) )
+ csr_write(CSR_VSISELECT, n->arch.vsiselect);
}
static void ctxt_switch_from(struct vcpu *p)
diff --git a/xen/arch/riscv/include/asm/domain.h
b/xen/arch/riscv/include/asm/domain.h
index 58d1e8076876..b0824d7f9add 100644
--- a/xen/arch/riscv/include/asm/domain.h
+++ b/xen/arch/riscv/include/asm/domain.h
@@ -75,6 +75,7 @@ struct arch_vcpu {
register_t vscause;
register_t vsepc;
uint64_t vsie;
+ register_t vsiselect;
register_t vsscratch;
register_t vsstatus;
register_t vstval;
Does it make sense to you?
>
>> - vsiselect is written directly by VS-mode through siselect;
>> - hviprio1 and hviprio2 hold the priorities of the local interrupts which
>> VS-mode reaches through the iprio array of vsiselect/vsireg, so writes
>> the guest performs there land in these CSRs.
> hviprio1 and hviprio2 hold priorities for interrupts 1 (SSI), 5 (STI),
> 13 (counter overflow), and 14-23 (local) so calling all of them "local"
> is wrong.
Agree, it is incorrect to call them "local"
>> Without saving them, one vCPU's selector leaks into another vCPU's vsireg
>> accesses and one guest's interrupt priorities apply to the next guest which
>> runs on the same hart.
>>
>> Whether the CSRs may be touched at all is gated by hstateen0 when Smstateen
>> is implemented: SVSLCT for vsiselect/vsireg and AIA for the rest of the AIA
> I couldn't find any reference to SVSLCT in the spec. I assume you wanted
> to refer to CSRIND and SVSLCT is an OpenSBI's own nickname.
>
Indeed, SVSLCT is the OpenSBI nickname/macro definition for this feature
and CSRIND would be better to use in commit message.
Thanks.
~ Oleksii
next prev parent reply other threads:[~2026-09-04 16:40 UTC|newest]
Thread overview: 163+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 15:20 [PATCH v2 00/39] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 01/39] xen/riscv: drop pregs from struct cpu_user_regs Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 6:58 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 02/39] xen/riscv: drop bug.h's duplicate instruction length helpers Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:01 ` Jan Beulich
2026-09-02 10:48 ` Oleksii Kurochko
2026-09-02 13:02 ` Jan Beulich
2026-09-02 13:45 ` Oleksii Kurochko
2026-09-02 14:27 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 03/39] xen/riscv: set the guest's XLEN explicitly in hstatus.VSXL Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:03 ` Jan Beulich
2026-09-01 8:40 ` Oleksii Kurochko
2026-09-01 15:16 ` Jan Beulich
2026-09-01 15:20 ` Jan Beulich
2026-09-02 11:42 ` Oleksii Kurochko
2026-09-02 13:07 ` Jan Beulich
2026-09-02 13:29 ` Oleksii Kurochko
2026-09-02 14:31 ` Jan Beulich
2026-09-02 15:17 ` Oleksii Kurochko
2026-09-02 15:56 ` Oleksii Kurochko
2026-09-02 17:45 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 04/39] xen/riscv: introduce csr_read64() Oleksii Kurochko
2026-08-27 15:36 ` Andrew Cooper
2026-08-31 12:42 ` Oleksii Kurochko
2026-09-01 7:07 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 05/39] xen/riscv: request a G-stage flush on vmenter when VMIDs are disabled Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 8:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 06/39] xen/riscv: use UINT64_MAX to disable the VS-timer Oleksii Kurochko
2026-08-31 12:48 ` Baptiste Le Duc
2026-09-01 7:12 ` Jan Beulich
2026-09-01 8:47 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 07/39] xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-01 15:53 ` Jan Beulich
2026-09-02 13:22 ` Jan Beulich
2026-09-02 13:52 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 08/39] xen/riscv: introduce device-agnostic MMIO emulation dispatch Oleksii Kurochko
2026-09-01 15:36 ` Baptiste Le Duc
2026-09-03 10:28 ` Oleksii Kurochko
2026-09-09 13:24 ` Jan Beulich
2026-09-09 14:04 ` Oleksii Kurochko
2026-09-09 14:32 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 09/39] xen/riscv: implement virtual APLIC MMIO emulation Oleksii Kurochko
2026-09-02 11:51 ` Baptiste Le Duc
2026-09-04 11:58 ` Oleksii Kurochko
2026-09-04 12:03 ` Jan Beulich
2026-09-02 12:31 ` Baptiste Le Duc
2026-09-04 14:02 ` Oleksii Kurochko
2026-09-09 14:26 ` Jan Beulich
2026-09-10 10:37 ` Oleksii Kurochko
2026-09-10 11:14 ` Jan Beulich
2026-09-10 14:24 ` Oleksii Kurochko
2026-09-12 8:50 ` SeungJu Cheon
2026-08-27 15:20 ` [PATCH v2 10/39] xen/riscv: build the target hart index via aplic_hart_field() Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 14:28 ` Oleksii Kurochko
2026-09-09 14:51 ` Jan Beulich
2026-09-09 14:52 ` Jan Beulich
2026-09-10 10:59 ` Oleksii Kurochko
2026-09-10 11:23 ` Jan Beulich
2026-09-10 11:23 ` Jan Beulich
2026-09-10 12:44 ` Oleksii Kurochko
2026-09-10 12:57 ` Jan Beulich
2026-09-11 9:47 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 11/39] xen/riscv: add helper to check APLIC MSI mode Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-09 14:53 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 12/39] xen/riscv: implement vCPU context switching Oleksii Kurochko
2026-09-02 14:42 ` Oleksii Kurochko
2026-09-04 8:26 ` Baptiste Le Duc
2026-09-04 8:33 ` Jan Beulich
2026-09-04 9:54 ` Baptiste Le Duc
2026-09-04 14:55 ` Oleksii Kurochko
2026-09-07 8:17 ` Jan Beulich
2026-09-08 9:06 ` Oleksii Kurochko
2026-09-05 7:25 ` Oleksii Kurochko
2026-09-10 13:29 ` Jan Beulich
2026-09-11 10:43 ` Oleksii Kurochko
2026-08-27 15:20 ` [PATCH v2 13/39] xen/riscv: save and restore AIA state on vCPU context switch Oleksii Kurochko
2026-09-04 9:52 ` Baptiste Le Duc
2026-09-04 16:40 ` Oleksii Kurochko [this message]
2026-08-27 15:20 ` [PATCH v2 14/39] xen/riscv: introduce vintc_ctxt_switch_{from,to}() Oleksii Kurochko
2026-09-04 11:25 ` Baptiste Le Duc
2026-09-04 16:54 ` Oleksii Kurochko
2026-09-10 14:54 ` Jan Beulich
2026-08-27 15:20 ` [PATCH v2 15/39] xen/riscv: add IMSIC vCPU context switch handlers Oleksii Kurochko
2026-09-04 11:33 ` Baptiste Le Duc
2026-09-04 16:56 ` Oleksii Kurochko
2026-09-10 14:57 ` Jan Beulich
2026-09-11 11:19 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 16/39] xen/riscv: extend exception tables with type and data fields Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 6:06 ` Jan Beulich
2026-09-08 8:18 ` Baptiste Le Duc
2026-09-08 9:19 ` Oleksii Kurochko
2026-09-08 16:26 ` Baptiste Le Duc
2026-09-08 13:44 ` Jan Beulich
2026-09-09 11:20 ` Oleksii Kurochko
2026-09-09 12:22 ` Jan Beulich
2026-09-09 12:42 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 17/39] xen/riscv: decouple INSN_PSEUDO_VS_* from the hypervisor's XLEN Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:34 ` Oleksii Kurochko
2026-09-08 16:04 ` Baptiste Le Duc
2026-09-09 12:57 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 18/39] xen/riscv: add guest page fault handling stub Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 9:49 ` Oleksii Kurochko
2026-09-08 14:10 ` Jan Beulich
2026-09-09 15:09 ` Oleksii Kurochko
2026-09-10 6:38 ` Jan Beulich
2026-09-11 11:47 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 19/39] xen/riscv: implement trap redirection to a guest Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:01 ` Oleksii Kurochko
2026-09-08 14:58 ` Oleksii Kurochko
2026-09-08 15:05 ` Jan Beulich
2026-09-08 15:47 ` Baptiste Le Duc
2026-09-08 15:58 ` Jan Beulich
2026-09-08 14:16 ` Jan Beulich
2026-09-08 15:25 ` Oleksii Kurochko
2026-09-08 14:16 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 20/39] xen/riscv: detect Shtvala Oleksii Kurochko
2026-09-07 15:57 ` Baptiste Le Duc
2026-09-08 10:15 ` Oleksii Kurochko
2026-09-08 15:49 ` Baptiste Le Duc
2026-08-27 15:21 ` [PATCH v2 21/39] xen/riscv: resolve the faulting guest physical address Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-11 12:56 ` Oleksii Kurochko
2026-09-10 15:06 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 22/39] xen/riscv: add guest memory read helper Oleksii Kurochko
2026-09-09 12:04 ` Baptiste Le Duc
2026-09-10 15:19 ` Jan Beulich
2026-09-11 13:06 ` Oleksii Kurochko
2026-09-11 13:41 ` Oleksii Kurochko
2026-09-11 13:47 ` Jan Beulich
2026-09-11 13:50 ` Oleksii Kurochko
2026-09-10 15:28 ` Jan Beulich
2026-09-11 13:57 ` Oleksii Kurochko
2026-09-11 14:00 ` Jan Beulich
2026-09-11 14:29 ` Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 23/39] xen/riscv: look up the exception table for any trap taken in Xen context Oleksii Kurochko
2026-09-10 15:31 ` Jan Beulich
2026-08-27 15:21 ` [PATCH v2 24/39] xen/riscv: add helpers for decoding a trapped load or store Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 25/39] xen/riscv: add guest load emulation for trapped MMIO accesses Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 26/39] xen/riscv: add guest store " Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 27/39] xen/riscv: introduce arch_move_irqs() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 28/39] xen/riscv: handle the case when no vCPU migration is needed Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 29/39] xen/riscv: introduce aplic_reconfigure_target() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 30/39] xen/riscv: prepare new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 31/39] xen/riscv: implement APLIC-hart sync barrier for vCPU migration Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 32/39] xen/riscv: remap interrupts to new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 33/39] xen/riscv: dump old interrupt file to memory Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 34/39] xen/riscv: restore register state in the new IMSIC VS-file Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 35/39] xen/riscv: add basic VGEIN management for AIA guests Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 36/39] xen/riscv: wake up a descheduled vCPU on a guest external interrupt Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 37/39] xen/riscv: map IMSIC interrupt file for vCPUs Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 38/39] xen/riscv: implement continue_new_vcpu() Oleksii Kurochko
2026-08-27 15:21 ` [PATCH v2 39/39] xen/riscv: introduce IMSIC h/w interrupt file attaching to vcpu Oleksii Kurochko
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