* [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block @ 2015-11-04 6:48 ` Liu Gang 0 siblings, 0 replies; 16+ messages in thread From: Liu Gang @ 2015-11-04 6:48 UTC (permalink / raw) To: robh+dt, linus.walleij, arnd, shawnguo Cc: bhupesh.sharma, devicetree, linux-gpio, linux-arm-kernel, b07421, R58472, Gang.Liu The GPIO block for ls2080a platform has little endian registers, the GPIO driver needs this property to read/write registers by right interface. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt index f2455c5..c836dab 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt @@ -10,6 +10,9 @@ Required properties: the second cell is used to specify the gpio polarity: 0 = active high 1 = active low +- little-endian : Should be set if the GPIO has little endian + registers. No the property means the GPIO + registers are big endian mode. Example: diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index f3c59f9..41bb8c1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -277,6 +277,7 @@ reg = <0x0 0x2300000 0x0 0x10000>; interrupts = <0 36 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -287,6 +288,7 @@ reg = <0x0 0x2310000 0x0 0x10000>; interrupts = <0 36 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -297,6 +299,7 @@ reg = <0x0 0x2320000 0x0 0x10000>; interrupts = <0 37 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -307,6 +310,7 @@ reg = <0x0 0x2330000 0x0 0x10000>; interrupts = <0 37 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block @ 2015-11-04 6:48 ` Liu Gang 0 siblings, 0 replies; 16+ messages in thread From: Liu Gang @ 2015-11-04 6:48 UTC (permalink / raw) To: linux-arm-kernel The GPIO block for ls2080a platform has little endian registers, the GPIO driver needs this property to read/write registers by right interface. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt index f2455c5..c836dab 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt @@ -10,6 +10,9 @@ Required properties: the second cell is used to specify the gpio polarity: 0 = active high 1 = active low +- little-endian : Should be set if the GPIO has little endian + registers. No the property means the GPIO + registers are big endian mode. Example: diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index f3c59f9..41bb8c1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -277,6 +277,7 @@ reg = <0x0 0x2300000 0x0 0x10000>; interrupts = <0 36 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -287,6 +288,7 @@ reg = <0x0 0x2310000 0x0 0x10000>; interrupts = <0 36 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -297,6 +299,7 @@ reg = <0x0 0x2320000 0x0 0x10000>; interrupts = <0 37 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -307,6 +310,7 @@ reg = <0x0 0x2330000 0x0 0x10000>; interrupts = <0 37 0x4>; /* Level high type */ gpio-controller; + little-endian; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform 2015-11-04 6:48 ` Liu Gang @ 2015-11-04 6:48 ` Liu Gang -1 siblings, 0 replies; 16+ messages in thread From: Liu Gang @ 2015-11-04 6:48 UTC (permalink / raw) To: robh+dt, linus.walleij, arnd, shawnguo Cc: bhupesh.sharma, devicetree, linux-gpio, linux-arm-kernel, b07421, R58472, Gang.Liu, Shaveta Leekha Layerscape has the same ip block/controller as GPIO on powerpc platform(MPC8XXX). So use portable i/o accessors, as in_be32/out_be32 accessors are Power architecture specific whereas ioread32/iowrite32 and ioread32be/iowrite32be are available in other architectures. Layerscape GPIO controller's registers may be big or little endian, so the code needs to get the endian property from DTB, then make additional functions to fit right register read/write operations. Currently the code can support ls2080a GPIO with little endian registers. And it can also work well on other layerscape platform with big endian GPIO registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8949b3f..c3ca283 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -290,12 +290,12 @@ config GPIO_MPC5200 depends on PPC_MPC52xx config GPIO_MPC8XXX - bool "MPC512x/MPC8xxx GPIO support" + bool "MPC512x/MPC8xxx/QorIQ GPIO support" depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ - FSL_SOC_BOOKE || PPC_86xx + FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE help Say Y here if you're going to use hardware that connects to the - MPC512x/831x/834x/837x/8572/8610 GPIOs. + MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs. config GPIO_MSM_V2 tristate "Qualcomm MSM GPIO v2" diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 48ef368..eb7a1ca 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -1,5 +1,5 @@ /* - * GPIOs on MPC512x/8349/8572/8610 and compatible + * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible * * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> * @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/slab.h> #include <linux/irq.h> +#include <linux/irqdomain.h> #define MPC8XXX_GPIO_PINS 32 @@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip { const void *of_dev_id_data; }; +static bool gpio_little_endian; +static inline u32 gpio_in32(void __iomem *addr) +{ + u32 val; + + if (gpio_little_endian) + val = ioread32(addr); + else + val = ioread32be(addr); + + return val; +} + +static inline void gpio_out32(u32 val, void __iomem *addr) +{ + if (gpio_little_endian) + iowrite32(val, addr); + else + iowrite32be(val, addr); +} + static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) { return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); @@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); - mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); + mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT); } +/* Generic set and clear bits accessor ports */ +#define bgpio_setbits32(_addr, _v) \ + gpio_out32(gpio_in32(_addr) | (_v), (_addr)) +#define bgpio_clrbits32(_addr, _v) \ + gpio_out32(gpio_in32(_addr) & ~(_v), (_addr)) +#define bgpio_clrsetbits32(addr, clear, set) \ + gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr)) + /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs * defined as output cannot be determined by reading GPDAT register, * so we use shadow data register instead. The status of input pins @@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); u32 out_mask, out_shadow; - out_mask = in_be32(mm->regs + GPIO_DIR); + out_mask = gpio_in32(mm->regs + GPIO_DIR); - val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; + val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask; out_shadow = mpc8xxx_gc->data & out_mask; return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); @@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); - return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); + return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); } static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) @@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) else mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc, } } - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); + bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); + bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; unsigned int mask; - mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); + mask = gpio_in32(mm->regs + GPIO_IER) + & gpio_in32(mm->regs + GPIO_IMR); if (mask) generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 32 - ffs(mask))); @@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct irq_data *d) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_setbits32(mm->regs + GPIO_IMR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_clrbits32(mm->regs + GPIO_IMR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_data *d) struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; - out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER); } static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) @@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) switch (flow_type) { case IRQ_TYPE_EDGE_FALLING: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_ICR, - mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_setbits32(mm->regs + GPIO_ICR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_ICR, - mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_clrbits32(mm->regs + GPIO_ICR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrsetbits_be32(reg, 3 << shift, 2 << shift); + bgpio_clrsetbits32(reg, 3 << shift, 2 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrsetbits_be32(reg, 3 << shift, 1 << shift); + bgpio_clrsetbits32(reg, 3 << shift, 1 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(reg, 3 << shift); + bgpio_clrbits32(reg, 3 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform_device *pdev) mm_gc = &mpc8xxx_gc->mm_gc; gc = &mm_gc->gc; + if (of_property_read_bool(np, "little-endian")) { + gpio_little_endian = true; + dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n"); + } else { + gpio_little_endian = false; + dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n"); + } + mm_gc->save_regs = mpc8xxx_gpio_save_regs; gc->ngpio = MPC8XXX_GPIO_PINS; gc->direction_input = mpc8xxx_gpio_dir_in; @@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform_device *pdev) return ret; mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); - if (mpc8xxx_gc->irqn == NO_IRQ) + if (mpc8xxx_gc->irqn == 0) return 0; mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, @@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform_device *pdev) mpc8xxx_gc->of_dev_id_data = id->data; /* ack and mask all irqs */ - out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); - out_be32(mm_gc->regs + GPIO_IMR, 0); + gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER); + gpio_out32(0, mm_gc->regs + GPIO_IMR); irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform @ 2015-11-04 6:48 ` Liu Gang 0 siblings, 0 replies; 16+ messages in thread From: Liu Gang @ 2015-11-04 6:48 UTC (permalink / raw) To: linux-arm-kernel Layerscape has the same ip block/controller as GPIO on powerpc platform(MPC8XXX). So use portable i/o accessors, as in_be32/out_be32 accessors are Power architecture specific whereas ioread32/iowrite32 and ioread32be/iowrite32be are available in other architectures. Layerscape GPIO controller's registers may be big or little endian, so the code needs to get the endian property from DTB, then make additional functions to fit right register read/write operations. Currently the code can support ls2080a GPIO with little endian registers. And it can also work well on other layerscape platform with big endian GPIO registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8949b3f..c3ca283 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -290,12 +290,12 @@ config GPIO_MPC5200 depends on PPC_MPC52xx config GPIO_MPC8XXX - bool "MPC512x/MPC8xxx GPIO support" + bool "MPC512x/MPC8xxx/QorIQ GPIO support" depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ - FSL_SOC_BOOKE || PPC_86xx + FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE help Say Y here if you're going to use hardware that connects to the - MPC512x/831x/834x/837x/8572/8610 GPIOs. + MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs. config GPIO_MSM_V2 tristate "Qualcomm MSM GPIO v2" diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 48ef368..eb7a1ca 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -1,5 +1,5 @@ /* - * GPIOs on MPC512x/8349/8572/8610 and compatible + * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible * * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> * @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/slab.h> #include <linux/irq.h> +#include <linux/irqdomain.h> #define MPC8XXX_GPIO_PINS 32 @@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip { const void *of_dev_id_data; }; +static bool gpio_little_endian; +static inline u32 gpio_in32(void __iomem *addr) +{ + u32 val; + + if (gpio_little_endian) + val = ioread32(addr); + else + val = ioread32be(addr); + + return val; +} + +static inline void gpio_out32(u32 val, void __iomem *addr) +{ + if (gpio_little_endian) + iowrite32(val, addr); + else + iowrite32be(val, addr); +} + static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) { return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); @@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); - mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); + mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT); } +/* Generic set and clear bits accessor ports */ +#define bgpio_setbits32(_addr, _v) \ + gpio_out32(gpio_in32(_addr) | (_v), (_addr)) +#define bgpio_clrbits32(_addr, _v) \ + gpio_out32(gpio_in32(_addr) & ~(_v), (_addr)) +#define bgpio_clrsetbits32(addr, clear, set) \ + gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr)) + /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs * defined as output cannot be determined by reading GPDAT register, * so we use shadow data register instead. The status of input pins @@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); u32 out_mask, out_shadow; - out_mask = in_be32(mm->regs + GPIO_DIR); + out_mask = gpio_in32(mm->regs + GPIO_DIR); - val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; + val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask; out_shadow = mpc8xxx_gc->data & out_mask; return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); @@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); - return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); + return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); } static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) @@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) else mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc, } } - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); + bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); + bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; unsigned int mask; - mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); + mask = gpio_in32(mm->regs + GPIO_IER) + & gpio_in32(mm->regs + GPIO_IMR); if (mask) generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 32 - ffs(mask))); @@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct irq_data *d) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_setbits32(mm->regs + GPIO_IMR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_clrbits32(mm->regs + GPIO_IMR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } @@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_data *d) struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; - out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER); } static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) @@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) switch (flow_type) { case IRQ_TYPE_EDGE_FALLING: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - setbits32(mm->regs + GPIO_ICR, - mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_setbits32(mm->regs + GPIO_ICR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(mm->regs + GPIO_ICR, - mpc8xxx_gpio2mask(irqd_to_hwirq(d))); + bgpio_clrbits32(mm->regs + GPIO_ICR, + mpc8xxx_gpio2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrsetbits_be32(reg, 3 << shift, 2 << shift); + bgpio_clrsetbits32(reg, 3 << shift, 2 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrsetbits_be32(reg, 3 << shift, 1 << shift); + bgpio_clrsetbits32(reg, 3 << shift, 1 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - clrbits32(reg, 3 << shift); + bgpio_clrbits32(reg, 3 << shift); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform_device *pdev) mm_gc = &mpc8xxx_gc->mm_gc; gc = &mm_gc->gc; + if (of_property_read_bool(np, "little-endian")) { + gpio_little_endian = true; + dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n"); + } else { + gpio_little_endian = false; + dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n"); + } + mm_gc->save_regs = mpc8xxx_gpio_save_regs; gc->ngpio = MPC8XXX_GPIO_PINS; gc->direction_input = mpc8xxx_gpio_dir_in; @@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform_device *pdev) return ret; mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); - if (mpc8xxx_gc->irqn == NO_IRQ) + if (mpc8xxx_gc->irqn == 0) return 0; mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, @@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform_device *pdev) mpc8xxx_gc->of_dev_id_data = id->data; /* ack and mask all irqs */ - out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); - out_be32(mm_gc->regs + GPIO_IMR, 0); + gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER); + gpio_out32(0, mm_gc->regs + GPIO_IMR); irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform 2015-11-04 6:48 ` Liu Gang @ 2015-11-04 8:53 ` Arnd Bergmann -1 siblings, 0 replies; 16+ messages in thread From: Arnd Bergmann @ 2015-11-04 8:53 UTC (permalink / raw) To: linux-arm-kernel Cc: Liu Gang, robh+dt, linus.walleij, shawnguo, devicetree, R58472, Shaveta Leekha, b07421, bhupesh.sharma, linux-gpio On Wednesday 04 November 2015 14:48:24 Liu Gang wrote: > Layerscape has the same ip block/controller as > GPIO on powerpc platform(MPC8XXX). > > So use portable i/o accessors, as in_be32/out_be32 > accessors are Power architecture specific whereas > ioread32/iowrite32 and ioread32be/iowrite32be are > available in other architectures. > > Layerscape GPIO controller's registers may be big > or little endian, so the code needs to get the > endian property from DTB, then make additional > functions to fit right register read/write > operations. > > Currently the code can support ls2080a GPIO with > little endian registers. And it can also work well > on other layerscape platform with big endian GPIO > registers. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > Signed-off-by: Shaveta Leekha <shaveta@freescale.com> > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 8949b3f..c3ca283 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -290,12 +290,12 @@ config GPIO_MPC5200 > depends on PPC_MPC52xx > > config GPIO_MPC8XXX > - bool "MPC512x/MPC8xxx GPIO support" > + bool "MPC512x/MPC8xxx/QorIQ GPIO support" > depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ > - FSL_SOC_BOOKE || PPC_86xx > + FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE > help > Say Y here if you're going to use hardware that connects to the > - MPC512x/831x/834x/837x/8572/8610 GPIOs. > + MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs. It would be nice to also add '|| COMPILE_TEST' here and ensure that it also builds on x86 with that set, to get better coverage from the automated build testing infrastructure. > +static bool gpio_little_endian; > +static inline u32 gpio_in32(void __iomem *addr) > +{ > + u32 val; > + > + if (gpio_little_endian) > + val = ioread32(addr); > + else > + val = ioread32be(addr); > + > + return val; > +} > + > +static inline void gpio_out32(u32 val, void __iomem *addr) > +{ > + if (gpio_little_endian) > + iowrite32(val, addr); > + else > + iowrite32be(val, addr); > +} I guess this is fixed per architecture, so you could also do this as static inline void gpio_out32(u32 val, void __iomem *addr) { if (IS_ENABLED(CONFIG_ARM)) iowrite32(val, addr); else if (IS_ENABLED(CONFIG_PPC) iowrite32be(val, addr); else BUG(); } and then check that the DT flag for little-endian matches the architecture specific default. Your version is more generic of course, while the one I show here is a little more efficient and avoids the global variable. Your choice. Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform @ 2015-11-04 8:53 ` Arnd Bergmann 0 siblings, 0 replies; 16+ messages in thread From: Arnd Bergmann @ 2015-11-04 8:53 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 04 November 2015 14:48:24 Liu Gang wrote: > Layerscape has the same ip block/controller as > GPIO on powerpc platform(MPC8XXX). > > So use portable i/o accessors, as in_be32/out_be32 > accessors are Power architecture specific whereas > ioread32/iowrite32 and ioread32be/iowrite32be are > available in other architectures. > > Layerscape GPIO controller's registers may be big > or little endian, so the code needs to get the > endian property from DTB, then make additional > functions to fit right register read/write > operations. > > Currently the code can support ls2080a GPIO with > little endian registers. And it can also work well > on other layerscape platform with big endian GPIO > registers. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > Signed-off-by: Shaveta Leekha <shaveta@freescale.com> > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 8949b3f..c3ca283 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -290,12 +290,12 @@ config GPIO_MPC5200 > depends on PPC_MPC52xx > > config GPIO_MPC8XXX > - bool "MPC512x/MPC8xxx GPIO support" > + bool "MPC512x/MPC8xxx/QorIQ GPIO support" > depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ > - FSL_SOC_BOOKE || PPC_86xx > + FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE > help > Say Y here if you're going to use hardware that connects to the > - MPC512x/831x/834x/837x/8572/8610 GPIOs. > + MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs. It would be nice to also add '|| COMPILE_TEST' here and ensure that it also builds on x86 with that set, to get better coverage from the automated build testing infrastructure. > +static bool gpio_little_endian; > +static inline u32 gpio_in32(void __iomem *addr) > +{ > + u32 val; > + > + if (gpio_little_endian) > + val = ioread32(addr); > + else > + val = ioread32be(addr); > + > + return val; > +} > + > +static inline void gpio_out32(u32 val, void __iomem *addr) > +{ > + if (gpio_little_endian) > + iowrite32(val, addr); > + else > + iowrite32be(val, addr); > +} I guess this is fixed per architecture, so you could also do this as static inline void gpio_out32(u32 val, void __iomem *addr) { if (IS_ENABLED(CONFIG_ARM)) iowrite32(val, addr); else if (IS_ENABLED(CONFIG_PPC) iowrite32be(val, addr); else BUG(); } and then check that the DT flag for little-endian matches the architecture specific default. Your version is more generic of course, while the one I show here is a little more efficient and avoids the global variable. Your choice. Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform 2015-11-04 8:53 ` Arnd Bergmann @ 2015-11-04 9:17 ` Scott Wood -1 siblings, 0 replies; 16+ messages in thread From: Scott Wood @ 2015-11-04 9:17 UTC (permalink / raw) To: Arnd Bergmann Cc: linux-arm-kernel, Liu Gang, robh+dt, linus.walleij, shawnguo, devicetree, R58472, Shaveta Leekha, b07421, bhupesh.sharma, linux-gpio On Wed, 2015-11-04 at 09:53 +0100, Arnd Bergmann wrote: > On Wednesday 04 November 2015 14:48:24 Liu Gang wrote: > > > > +static bool gpio_little_endian; > > +static inline u32 gpio_in32(void __iomem *addr) > > +{ > > + u32 val; > > + > > + if (gpio_little_endian) > > + val = ioread32(addr); > > + else > > + val = ioread32be(addr); > > + > > + return val; > > +} > > + > > +static inline void gpio_out32(u32 val, void __iomem *addr) > > +{ > > + if (gpio_little_endian) > > + iowrite32(val, addr); > > + else > > + iowrite32be(val, addr); > > +} > > I guess this is fixed per architecture, so you could also do this as > > static inline void gpio_out32(u32 val, void __iomem *addr) > { > if (IS_ENABLED(CONFIG_ARM)) > iowrite32(val, addr); > else if (IS_ENABLED(CONFIG_PPC) > iowrite32be(val, addr); > else > BUG(); > } Unfortunately that guess is wrong. Some of our ARM chips have big-endian I/O and some have little-endian I/O. -Scott ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform @ 2015-11-04 9:17 ` Scott Wood 0 siblings, 0 replies; 16+ messages in thread From: Scott Wood @ 2015-11-04 9:17 UTC (permalink / raw) To: linux-arm-kernel On Wed, 2015-11-04 at 09:53 +0100, Arnd Bergmann wrote: > On Wednesday 04 November 2015 14:48:24 Liu Gang wrote: > > > > +static bool gpio_little_endian; > > +static inline u32 gpio_in32(void __iomem *addr) > > +{ > > + u32 val; > > + > > + if (gpio_little_endian) > > + val = ioread32(addr); > > + else > > + val = ioread32be(addr); > > + > > + return val; > > +} > > + > > +static inline void gpio_out32(u32 val, void __iomem *addr) > > +{ > > + if (gpio_little_endian) > > + iowrite32(val, addr); > > + else > > + iowrite32be(val, addr); > > +} > > I guess this is fixed per architecture, so you could also do this as > > static inline void gpio_out32(u32 val, void __iomem *addr) > { > if (IS_ENABLED(CONFIG_ARM)) > iowrite32(val, addr); > else if (IS_ENABLED(CONFIG_PPC) > iowrite32be(val, addr); > else > BUG(); > } Unfortunately that guess is wrong. Some of our ARM chips have big-endian I/O and some have little-endian I/O. -Scott ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform 2015-11-04 9:17 ` Scott Wood @ 2015-11-04 10:09 ` Arnd Bergmann -1 siblings, 0 replies; 16+ messages in thread From: Arnd Bergmann @ 2015-11-04 10:09 UTC (permalink / raw) To: linux-arm-kernel Cc: Scott Wood, devicetree, R58472, b07421, Shaveta Leekha, linus.walleij, bhupesh.sharma, Liu Gang, robh+dt, linux-gpio, shawnguo On Wednesday 04 November 2015 03:17:38 Scott Wood wrote: > > I guess this is fixed per architecture, so you could also do this as > > > > static inline void gpio_out32(u32 val, void __iomem *addr) > > { > > if (IS_ENABLED(CONFIG_ARM)) > > iowrite32(val, addr); > > else if (IS_ENABLED(CONFIG_PPC)) > > iowrite32be(val, addr); > > else > > BUG(); > > } > > Unfortunately that guess is wrong. Some of our ARM chips have big-endian I/O > and some have little-endian I/O. Ok, I see. In that case, using run-time detection everywhere is probably best. Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform @ 2015-11-04 10:09 ` Arnd Bergmann 0 siblings, 0 replies; 16+ messages in thread From: Arnd Bergmann @ 2015-11-04 10:09 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 04 November 2015 03:17:38 Scott Wood wrote: > > I guess this is fixed per architecture, so you could also do this as > > > > static inline void gpio_out32(u32 val, void __iomem *addr) > > { > > if (IS_ENABLED(CONFIG_ARM)) > > iowrite32(val, addr); > > else if (IS_ENABLED(CONFIG_PPC)) > > iowrite32be(val, addr); > > else > > BUG(); > > } > > Unfortunately that guess is wrong. Some of our ARM chips have big-endian I/O > and some have little-endian I/O. Ok, I see. In that case, using run-time detection everywhere is probably best. Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block 2015-11-04 6:48 ` Liu Gang @ 2015-11-05 13:27 ` Rob Herring -1 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2015-11-05 13:27 UTC (permalink / raw) To: Liu Gang Cc: linus.walleij, arnd, shawnguo, bhupesh.sharma, devicetree, linux-gpio, linux-arm-kernel, b07421, R58472 On Wed, Nov 04, 2015 at 02:48:23PM +0800, Liu Gang wrote: > The GPIO block for ls2080a platform has little endian registers, > the GPIO driver needs this property to read/write registers by > right interface. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Rob Herring <robh@kernel.org> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > index f2455c5..c836dab 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > @@ -10,6 +10,9 @@ Required properties: > the second cell is used to specify the gpio polarity: > 0 = active high > 1 = active low > +- little-endian : Should be set if the GPIO has little endian > + registers. No the property means the GPIO > + registers are big endian mode. > > Example: > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index f3c59f9..41bb8c1 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -277,6 +277,7 @@ > reg = <0x0 0x2300000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -287,6 +288,7 @@ > reg = <0x0 0x2310000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -297,6 +299,7 @@ > reg = <0x0 0x2320000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -307,6 +310,7 @@ > reg = <0x0 0x2330000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > -- > 2.1.0.27.g96db324 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block @ 2015-11-05 13:27 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2015-11-05 13:27 UTC (permalink / raw) To: linux-arm-kernel On Wed, Nov 04, 2015 at 02:48:23PM +0800, Liu Gang wrote: > The GPIO block for ls2080a platform has little endian registers, > the GPIO driver needs this property to read/write registers by > right interface. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Rob Herring <robh@kernel.org> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > index f2455c5..c836dab 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > @@ -10,6 +10,9 @@ Required properties: > the second cell is used to specify the gpio polarity: > 0 = active high > 1 = active low > +- little-endian : Should be set if the GPIO has little endian > + registers. No the property means the GPIO > + registers are big endian mode. > > Example: > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index f3c59f9..41bb8c1 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -277,6 +277,7 @@ > reg = <0x0 0x2300000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -287,6 +288,7 @@ > reg = <0x0 0x2310000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -297,6 +299,7 @@ > reg = <0x0 0x2320000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -307,6 +310,7 @@ > reg = <0x0 0x2330000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > -- > 2.1.0.27.g96db324 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block 2015-11-04 6:48 ` Liu Gang @ 2015-11-24 6:57 ` Shawn Guo -1 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-11-24 6:57 UTC (permalink / raw) To: Liu Gang Cc: robh+dt, linus.walleij, arnd, devicetree, R58472, b07421, bhupesh.sharma, linux-gpio, linux-arm-kernel On Wed, Nov 04, 2015 at 02:48:23PM +0800, Liu Gang wrote: > The GPIO block for ls2080a platform has little endian registers, > the GPIO driver needs this property to read/write registers by > right interface. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Please do not mix binding doc together with dts changes in one patch. Shawn > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > index f2455c5..c836dab 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > @@ -10,6 +10,9 @@ Required properties: > the second cell is used to specify the gpio polarity: > 0 = active high > 1 = active low > +- little-endian : Should be set if the GPIO has little endian > + registers. No the property means the GPIO > + registers are big endian mode. > > Example: > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index f3c59f9..41bb8c1 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -277,6 +277,7 @@ > reg = <0x0 0x2300000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -287,6 +288,7 @@ > reg = <0x0 0x2310000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -297,6 +299,7 @@ > reg = <0x0 0x2320000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -307,6 +310,7 @@ > reg = <0x0 0x2330000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > -- > 2.1.0.27.g96db324 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block @ 2015-11-24 6:57 ` Shawn Guo 0 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-11-24 6:57 UTC (permalink / raw) To: linux-arm-kernel On Wed, Nov 04, 2015 at 02:48:23PM +0800, Liu Gang wrote: > The GPIO block for ls2080a platform has little endian registers, > the GPIO driver needs this property to read/write registers by > right interface. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Please do not mix binding doc together with dts changes in one patch. Shawn > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > index f2455c5..c836dab 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > +++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt > @@ -10,6 +10,9 @@ Required properties: > the second cell is used to specify the gpio polarity: > 0 = active high > 1 = active low > +- little-endian : Should be set if the GPIO has little endian > + registers. No the property means the GPIO > + registers are big endian mode. > > Example: > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index f3c59f9..41bb8c1 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -277,6 +277,7 @@ > reg = <0x0 0x2300000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -287,6 +288,7 @@ > reg = <0x0 0x2310000 0x0 0x10000>; > interrupts = <0 36 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -297,6 +299,7 @@ > reg = <0x0 0x2320000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > @@ -307,6 +310,7 @@ > reg = <0x0 0x2330000 0x0 0x10000>; > interrupts = <0 37 0x4>; /* Level high type */ > gpio-controller; > + little-endian; > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > -- > 2.1.0.27.g96db324 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1446549552-40675-1-git-send-email-Gang.Liu@freescale.com>]
[parent not found: <1446549552-40675-2-git-send-email-Gang.Liu@freescale.com>]
* Re: [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform [not found] ` <1446549552-40675-2-git-send-email-Gang.Liu@freescale.com> @ 2015-11-16 15:09 ` Linus Walleij 0 siblings, 0 replies; 16+ messages in thread From: Linus Walleij @ 2015-11-16 15:09 UTC (permalink / raw) To: Liu Gang Cc: Rob Herring, Bhupesh Sharma, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, b07421, R58472, Shaveta Leekha On Tue, Nov 3, 2015 at 12:19 PM, Liu Gang <Gang.Liu@freescale.com> wrote: > Layerscape has the same ip block/controller as > GPIO on powerpc platform(MPC8XXX). > > So use portable i/o accessors, as in_be32/out_be32 > accessors are Power architecture specific whereas > ioread32/iowrite32 and ioread32be/iowrite32be are > available in other architectures. > > Layerscape GPIO controller's registers may be big > or little endian, so the code needs to get the > endian property from DTB, then make additional > functions to fit right register read/write > operations. > > Currently the code can support ls2080a GPIO with > little endian registers. And it can also work well > on other layerscape platform with big endian GPIO > registers. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > Signed-off-by: Shaveta Leekha <shaveta@freescale.com> This doesn't seem good. You are starting to duplicate stuff that is already available inside the gpio-generic.c driver. Why can't this driver just select GPIO_GENERIC in Kconfig and use the common code for handling the endianness accessors? bgpio_init() takes a flag BGPIOF_BIG_ENDIAN_BYTE_ORDER to make all accesses big endian, so using the generic GPIO library would save you a lot of code. Just look at other drivers for those selecting GPIO_GENERIC, including <linux/basic_mmio_gpio.h> and calling bgpio_init(). You might want to keep some local custom BE code around the IRQ parts. But I would do two patches: - One that switches MPC8xxx to using GENERIC_GPIO - One that adds BE support using that infrastructure It will result in a lot less code. I think. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform @ 2015-11-16 15:09 ` Linus Walleij 0 siblings, 0 replies; 16+ messages in thread From: Linus Walleij @ 2015-11-16 15:09 UTC (permalink / raw) To: linux-arm-kernel On Tue, Nov 3, 2015 at 12:19 PM, Liu Gang <Gang.Liu@freescale.com> wrote: > Layerscape has the same ip block/controller as > GPIO on powerpc platform(MPC8XXX). > > So use portable i/o accessors, as in_be32/out_be32 > accessors are Power architecture specific whereas > ioread32/iowrite32 and ioread32be/iowrite32be are > available in other architectures. > > Layerscape GPIO controller's registers may be big > or little endian, so the code needs to get the > endian property from DTB, then make additional > functions to fit right register read/write > operations. > > Currently the code can support ls2080a GPIO with > little endian registers. And it can also work well > on other layerscape platform with big endian GPIO > registers. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > Signed-off-by: Shaveta Leekha <shaveta@freescale.com> This doesn't seem good. You are starting to duplicate stuff that is already available inside the gpio-generic.c driver. Why can't this driver just select GPIO_GENERIC in Kconfig and use the common code for handling the endianness accessors? bgpio_init() takes a flag BGPIOF_BIG_ENDIAN_BYTE_ORDER to make all accesses big endian, so using the generic GPIO library would save you a lot of code. Just look at other drivers for those selecting GPIO_GENERIC, including <linux/basic_mmio_gpio.h> and calling bgpio_init(). You might want to keep some local custom BE code around the IRQ parts. But I would do two patches: - One that switches MPC8xxx to using GENERIC_GPIO - One that adds BE support using that infrastructure It will result in a lot less code. I think. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2015-11-24 6:58 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2015-11-04 6:48 [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block Liu Gang
2015-11-04 6:48 ` Liu Gang
2015-11-04 6:48 ` [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform Liu Gang
2015-11-04 6:48 ` Liu Gang
2015-11-04 8:53 ` Arnd Bergmann
2015-11-04 8:53 ` Arnd Bergmann
2015-11-04 9:17 ` Scott Wood
2015-11-04 9:17 ` Scott Wood
2015-11-04 10:09 ` Arnd Bergmann
2015-11-04 10:09 ` Arnd Bergmann
2015-11-05 13:27 ` [PATCH 1/2] ls2080a/dts: Add little endian property for GPIO IP block Rob Herring
2015-11-05 13:27 ` Rob Herring
2015-11-24 6:57 ` Shawn Guo
2015-11-24 6:57 ` Shawn Guo
[not found] <1446549552-40675-1-git-send-email-Gang.Liu@freescale.com>
[not found] ` <1446549552-40675-2-git-send-email-Gang.Liu@freescale.com>
2015-11-16 15:09 ` [PATCH 2/2] drivers/gpio: Port gpio driver to layerscape platform Linus Walleij
2015-11-16 15:09 ` Linus Walleij
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