* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040228212407.DB126494190@palinux.hppa> @ 2004-02-28 22:21 ` Joel Soete 2004-02-28 22:42 ` James Bottomley 0 siblings, 1 reply; 50+ messages in thread From: Joel Soete @ 2004-02-28 22:21 UTC (permalink / raw) To: parisc-linux James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/02/28 14:24:07 > > Modified files: > . : Makefile > > Log message: > Compiles, boots and stands the BK torture test on my C360, so -pa1 > Hey interesting, I mean 'torture test'. Where can I get more detail on this stuff to test on the N4K also? Thanks in advance for help, Joel ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-02-28 22:21 ` [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb Joel Soete @ 2004-02-28 22:42 ` James Bottomley 2004-02-29 9:39 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-02-28 22:42 UTC (permalink / raw) To: Joel Soete; +Cc: PARISC list On Sat, 2004-02-28 at 16:21, Joel Soete wrote: > Hey interesting, I mean 'torture test'. Where can I get more detail on this stuff to test on the N4K also? It just means running bk doing a tree merge, checking out the results and compiling the kernel. It seems to sow up most types of problems ... James ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-02-28 22:42 ` James Bottomley @ 2004-02-29 9:39 ` Joel Soete 2004-03-04 16:39 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: Joel Soete @ 2004-02-29 9:39 UTC (permalink / raw) To: James Bottomley; +Cc: PARISC list James Bottomley wrote: > On Sat, 2004-02-28 at 16:21, Joel Soete wrote: > >>Hey interesting, I mean 'torture test'. Where can I get more detail on this stuff to test on the N4K also? > > > It just means running bk doing a tree merge, checking out the results > and compiling the kernel. It seems to sow up most types of problems ... > > James > > > Ah ok , it just sound like some gcc test :) , that is why I though there was bourned a new test for our kernel. Thanks for feedback, Joel PS: I will so prepare such boot kernel for the N ;) ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-02-29 9:39 ` Joel Soete @ 2004-03-04 16:39 ` Joel Soete 0 siblings, 0 replies; 50+ messages in thread From: Joel Soete @ 2004-03-04 16:39 UTC (permalink / raw) To: James Bottomley; +Cc: PARISC list Hi all, Sorry for delay but i fill a bit lazy this week (may be because a bit sick :( ). Anyway, I get cvs and last a500 config file (in which i just change tulip builtin in place of module) and it boot fine :). Thanks to all for great job, Joel PS: Anticipating rc2-pa0, this merge is straighforward, and boot fine on a b180 ;) James Bottomley wrote: > On Sat, 2004-02-28 at 16:21, Joel Soete wrote: > >>Hey interesting, I mean 'torture test'. Where can I get more detail on this stuff to test on the N4K also? > > > It just means running bk doing a tree merge, check > ng out the results > and compiling the kernel. It seems to sow up most types of problems ... > > James > > > Ah ok , it just sound like some gcc test :) , that is why I though there was bourned a new test for our kernel. Thanks for feedb > ck, Joel PS: I will so prepare such boot kernel for the N ;) ---------------------------------------------------------------------------------------- Tiscali ADSL: 19,50 €/mois, pendant 3 mois! L'Internet rapide, c'est pour tout le monde. http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
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* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040505204811.27F0C4945E4@palinux.hppa> @ 2004-05-05 20:50 ` James Bottomley 2004-05-06 5:05 ` Randolph Chung 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-05-05 20:50 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Wed, 2004-05-05 at 15:48, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/05/05 14:48:11 > > Modified files: > . : Makefile > include/asm-parisc: page.h pgtable.h > > Log message: > Move to 8 byte Page Table Entries for 32 bit kernels. This allows us > to recover sixteen flag bits (the sixteen bits at the top of the pte for > 64 bit - 48 address bits is pretty unlikely to be hit soon) on both 32 > and 64 bits. ===== include/asm-parisc/page.h 1.10 vs edited ===== --- 1.10/include/asm-parisc/page.h Mon May 3 14:40:20 2004 +++ edited/include/asm-parisc/page.h Wed May 5 10:12:19 2004 @@ -40,7 +40,14 @@ /* * These are used to make use of C type-checking.. */ +#ifdef __LP64__ typedef struct { unsigned long pte; } pte_t; +#else +typedef struct { + unsigned long pte; + unsigned long flags; +} pte_t; +#endif /* NOTE: even on 64 bits, these entries are __u32 because we allocate * the pmd and pgd in ZONE_DMA (i.e. under 4GB) */ typedef struct { __u32 pmd; } pmd_t; @@ -48,6 +55,11 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define pte_val(x) ((x).pte) +#ifdef __LP64__ +#define pte_flags(x) #error +#else +#define pte_flags(x) ((x).flags) +#endif #define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) @@ -95,7 +107,7 @@ #define BITS_PER_PMD_ENTRY 2 #define BITS_PER_PGD_ENTRY 2 #else -#define BITS_PER_PTE_ENTRY 2 +#define BITS_PER_PTE_ENTRY 3 #define BITS_PER_PMD_ENTRY 2 #define BITS_PER_PGD_ENTRY BITS_PER_PMD_ENTRY #endif ===== include/asm-parisc/pgtable.h 1.21 vs edited ===== --- 1.21/include/asm-parisc/pgtable.h Sun May 2 05:20:20 2004 +++ edited/include/asm-parisc/pgtable.h Wed May 5 12:13:18 2004 @@ -70,8 +70,8 @@ #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ #else #define PT_NLEVELS 2 -#define PT_INITIAL 2 /* Number of initial page tables */ -#define PGD_ORDER 0 /* Number of pages per pgd */ +#define PT_INITIAL 4 /* Number of initial page tables */ +#define PGD_ORDER 1 /* Number of pages per pgd */ #define PGD_ALLOC_ORDER PGD_ORDER #endif ^ permalink raw reply [flat|nested] 50+ messages in thread
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-05-05 20:50 ` James Bottomley @ 2004-05-06 5:05 ` Randolph Chung 2004-05-06 5:22 ` Randolph Chung ` (2 more replies) 0 siblings, 3 replies; 50+ messages in thread From: Randolph Chung @ 2004-05-06 5:05 UTC (permalink / raw) To: James Bottomley; +Cc: PARISC list > > Move to 8 byte Page Table Entries for 32 bit kernels. This allows us > > to recover sixteen flag bits (the sixteen bits at the top of the pte for > > 64 bit - 48 address bits is pretty unlikely to be hit soon) on both 32 > > and 64 bits. jejb, this seems to have broken the kernel for me. On my c3750, -pa9 doesn't boot (-pa7 is ok). With -pa9 the machine HPMC's very early during boot (i have early debug turned on, but there was no console output). unfortunately the hpmc data doesn't seem to say very much. iaoq is pointing to skip_save_ior. rp is 0 :-( perhaps this is sensitive to amount of physical memory in the system? i have 1.5GB in my system. randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-05-06 5:05 ` Randolph Chung @ 2004-05-06 5:22 ` Randolph Chung 2004-05-06 9:33 ` M. Grabert 2004-05-06 13:25 ` Kyle McMartin 2 siblings, 0 replies; 50+ messages in thread From: Randolph Chung @ 2004-05-06 5:22 UTC (permalink / raw) To: James Bottomley; +Cc: PARISC list > jejb, this seems to have broken the kernel for me. On my c3750, -pa9 > doesn't boot (-pa7 is ok). With -pa9 the machine HPMC's very early > during boot (i have early debug turned on, but there was no console > output). i forgot to mention, this is running 32-bit. randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-05-06 5:05 ` Randolph Chung 2004-05-06 5:22 ` Randolph Chung @ 2004-05-06 9:33 ` M. Grabert 2004-05-06 13:25 ` Kyle McMartin 2 siblings, 0 replies; 50+ messages in thread From: M. Grabert @ 2004-05-06 9:33 UTC (permalink / raw) To: Randolph Chung; +Cc: James Bottomley, PARISC list On Wed, 5 May 2004, Randolph Chung wrote: > > > Move to 8 byte Page Table Entries for 32 bit kernels. This allows us > > > to recover sixteen flag bits (the sixteen bits at the top of the pte for > > > 64 bit - 48 address bits is pretty unlikely to be hit soon) on both 32 > > > and 64 bits. > > jejb, this seems to have broken the kernel for me. On my c3750, -pa9 > doesn't boot (-pa7 is ok). With -pa9 the machine HPMC's very early > during boot (i have early debug turned on, but there was no console > output). I tried -pa8 yesterday (32bit) on my C3000, and it also HPMCs straight after the 'if this is the last message ...' output. At first I thought it was related to the palo-1.4 bug, so I reinstalled palo-1.3, but this didn't solve the problem. > perhaps this is sensitive to amount of physical memory in the system? i > have 1.5GB in my system. 1GB here. Thanks, Max ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-05-06 5:05 ` Randolph Chung 2004-05-06 5:22 ` Randolph Chung 2004-05-06 9:33 ` M. Grabert @ 2004-05-06 13:25 ` Kyle McMartin 2 siblings, 0 replies; 50+ messages in thread From: Kyle McMartin @ 2004-05-06 13:25 UTC (permalink / raw) To: parisc-linux On Wed, May 05, 2004 at 10:05:21PM -0700, Randolph Chung wrote: > jejb, this seems to have broken the kernel for me. On my c3750, -pa9 > doesn't boot (-pa7 is ok). With -pa9 the machine HPMC's very early > during boot (i have early debug turned on, but there was no console > output). > Same thing happens on a b180. Regards, -- Kyle McMartin ^ permalink raw reply [flat|nested] 50+ messages in thread
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* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040502161601.DC7C24945C7@palinux.hppa> @ 2004-05-03 20:51 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-05-03 20:51 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Sun, 2004-05-02 at 11:16, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/05/02 10:16:01 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S init_task.c > include/asm-parisc: pgalloc.h pgtable.h > > Log message: > Implement L2/L3 hybrid page tables for 64 bit kernels Index: arch/parisc/kernel/asm-offsets.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/asm-offsets.c,v retrieving revision 1.7 diff -u -r1.7 asm-offsets.c --- a/arch/parisc/kernel/asm-offsets.c 1 May 2004 20:03:11 -0000 1.7 +++ b/arch/parisc/kernel/asm-offsets.c 2 May 2004 15:53:49 -0000 @@ -282,6 +282,7 @@ DEFINE(ASM_BITS_PER_PGD, BITS_PER_PGD); DEFINE(ASM_BITS_PER_PMD, BITS_PER_PMD); DEFINE(ASM_BITS_PER_PTE, BITS_PER_PTE); + DEFINE(ASM_PGD_PMD_OFFSET, -(PAGE_SIZE << PGD_ORDER)); DEFINE(ASM_PMD_ENTRY, ((PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); DEFINE(ASM_PGD_ENTRY, PAGE_OFFSET >> PGDIR_SHIFT); DEFINE(ASM_PGD_ENTRY_SIZE, PGD_ENTRY_SIZE); Index: arch/parisc/kernel/entry.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/entry.S,v retrieving revision 1.13 diff -u -r1.13 entry.S --- a/arch/parisc/kernel/entry.S 1 May 2004 20:03:11 -0000 1.13 +++ b/arch/parisc/kernel/entry.S 2 May 2004 15:53:51 -0000 @@ -474,11 +474,24 @@ bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault .endm - /* Look up PTE in a 3-Level scheme */ + /* Look up PTE in a 3-Level scheme. + * + * Here we implement a Hybrid L2/L3 scheme: we allocate the + * first pmd adjacent to the pgd. This means that we can + * subtract a constant offset to get to it. The pmd and pgd + * sizes are arranged so that a single pmd covers 4GB (giving + * a full LP64 process access to 8TB) so our lookups are + * effectively L2 for the first 4GB of the kernel (i.e. for + * all ILP32 processes and all the kernel for machines with + * under 4GB of memory) */ .macro L3_ptep pgd,pte,index,va,fault extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index copy %r0,\pte + extrd,u,*= \va,31,32,%r0 ldw,s \index(\pgd),\pgd + extrd,u,*<> \va,31,32,%r0 + ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd + extrd,u,*= \va,31,32,%r0 bb,>=,n \pgd,_PAGE_PRESENT_BIT,\fault L2_ptep \pgd,\pte,\index,\va,\fault .endm Index: arch/parisc/kernel/init_task.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/init_task.c,v retrieving revision 1.5 diff -u -r1.5 init_task.c --- a/arch/parisc/kernel/init_task.c 1 May 2004 16:05:55 -0000 1.5 +++ b/arch/parisc/kernel/init_task.c 2 May 2004 15:53:51 -0000 @@ -52,11 +52,13 @@ __attribute__((aligned(128))) __attribute__((__section__(".data.init_task"))) = { INIT_THREAD_INFO(init_task) }; -pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE<<PGD_ORDER))) = { {0}, }; #ifdef __LP64__ -pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((aligned(4096))) = { {0}, }; +/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout + * with the first pmd adjacent to the pgd and below it */ +pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((aligned(PAGE_SIZE))) = { {0}, }; #endif -pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((aligned(4096))) = { {0}, }; +pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE))) = { {0}, }; +pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((aligned(PAGE_SIZE))) = { {0}, }; /* * Initial task structure. Index: include/asm-parisc/pgalloc.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/pgalloc.h,v retrieving revision 1.4 diff -u -r1.4 pgalloc.h --- a/include/asm-parisc/pgalloc.h 1 May 2004 20:03:11 -0000 1.4 +++ b/include/asm-parisc/pgalloc.h 2 May 2004 15:54:10 -0000 @@ -10,18 +10,44 @@ #include <asm/pgtable.h> #include <asm/cache.h> +/* Allocate the top level pgd (page directory) + * + * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we + * allocate the first pmd adjacent to the pgd. This means that we can + * subtract a constant offset to get to it. The pmd and pgd sizes are + * arranged so that a single pmd covers 4GB (giving a full LP64 + * process access to 8TB) so our lookups are effectively L2 for the + * first 4GB of the kernel (i.e. for all ILP32 processes and all the + * kernel for machines with under 4GB of memory) */ static inline pgd_t *pgd_alloc(struct mm_struct *mm) { - pgd_t *pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, PGD_ORDER); - - if (likely(pgd != NULL)) - memset(pgd, 0, PAGE_SIZE<<PGD_ORDER); - return pgd; + pgd_t *pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|GFP_DMA, + PGD_ALLOC_ORDER); + pgd_t *actual_pgd = pgd; + + if (likely(pgd != NULL)) { + memset(pgd, 0, PAGE_SIZE<<PGD_ALLOC_ORDER); +#ifdef __LP64__ + actual_pgd += PTRS_PER_PGD; + /* Populate first pmd with allocated memory. We mark it + * with _PAGE_GATEWAY as a signal to the system that this + * pmd entry may not be cleared. */ + pgd_val(*actual_pgd) = (_PAGE_TABLE | _PAGE_GATEWAY) + + (__u32)__pa((unsigned long)pgd); + /* The first pmd entry also is marked with _PAGE_GATEWAY as + * a signal that this pmd may not be freed */ + pgd_val(*pgd) = _PAGE_GATEWAY; +#endif + } + return actual_pgd; } static inline void pgd_free(pgd_t *pgd) { - free_pages((unsigned long)pgd, PGD_ORDER); +#ifdef __LP64__ + pgd -= PTRS_PER_PGD; +#endif + free_pages((unsigned long)pgd, PGD_ALLOC_ORDER); } #if PT_NLEVELS == 3 @@ -46,6 +72,12 @@ static inline void pmd_free(pmd_t *pmd) { +#ifdef __LP64__ + if(pmd_val(*pmd) & _PAGE_GATEWAY) + /* This is the permanent pmd attached to the pgd; + * cannot free it */ + return; +#endif free_pages((unsigned long)pmd, PMD_ORDER); } @@ -67,7 +99,15 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) { - pmd_val(*pmd) = _PAGE_TABLE + (__u32)__pa((unsigned long)pte); +#ifdef __LP64__ + /* preserve the gateway marker if this is the beginning of + * the permanent pmd */ + if(pmd_val(*pmd) & _PAGE_GATEWAY) + pmd_val(*pmd) = (_PAGE_TABLE | _PAGE_GATEWAY) + + (__u32)__pa((unsigned long)pte); + else +#endif + pmd_val(*pmd) = _PAGE_TABLE + (__u32)__pa((unsigned long)pte); } #define pmd_populate(mm, pmd, pte_page) \ Index: include/asm-parisc/pgtable.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/pgtable.h,v retrieving revision 1.8 diff -u -r1.8 pgtable.h --- a/include/asm-parisc/pgtable.h 1 May 2004 20:03:11 -0000 1.8 +++ b/include/asm-parisc/pgtable.h 2 May 2004 15:54:11 -0000 @@ -67,10 +67,12 @@ #define PT_INITIAL 4 /* Number of initial page tables */ #define PGD_ORDER 1 /* Number of pages per pgd */ #define PMD_ORDER 1 /* Number of pages per pmd */ +#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ #else #define PT_NLEVELS 2 #define PT_INITIAL 2 /* Number of initial page tables */ #define PGD_ORDER 0 /* Number of pages per pgd */ +#define PGD_ALLOC_ORDER PGD_ORDER #endif /* Definitions for 3rd level (we use PLD here for Page Lower directory @@ -242,10 +244,26 @@ #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) #define pte_clear(xp) do { pte_val(*(xp)) = 0; } while (0) +#ifdef __LP64__ +/* The first entry of the permanent pmd is not there if it contains + * the gateway marker */ +#define pmd_none(x) (!pmd_val(x) || pmd_val(x) == _PAGE_GATEWAY) +#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK) != _PAGE_TABLE && (pmd_val(x) & ~PAGE_MASK) != (_PAGE_TABLE | _PAGE_GATEWAY)) +#else #define pmd_none(x) (!pmd_val(x)) #define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK) != _PAGE_TABLE) +#endif #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) -#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) +static inline void pmd_clear(pmd_t *pmd) { +#ifdef __LP64__ + if(pmd_val(*pmd) & _PAGE_GATEWAY) + /* This is the entry pointing to the permanent pmd + * attached to the pgd; cannot clear it */ + pmd_val(*pmd) = _PAGE_GATEWAY; + else +#endif + pmd_val(*pmd) = 0; +} @@ -255,9 +273,21 @@ /* For 64 bit we have three level tables */ #define pgd_none(x) (!pgd_val(x)) +#ifdef __LP64__ +#define pgd_bad(x) ((pgd_val(x) & ~PAGE_MASK) != _PAGE_TABLE && (pgd_val(x) & ~PAGE_MASK) != (_PAGE_TABLE | _PAGE_GATEWAY)) +#else #define pgd_bad(x) ((pgd_val(x) & ~PAGE_MASK) != _PAGE_TABLE) +#endif #define pgd_present(x) (pgd_val(x) & _PAGE_PRESENT) -#define pgd_clear(xp) do { pgd_val(*(xp)) = 0; } while (0) +static inline void pgd_clear(pgd_t *pgd) { +#ifdef __LP64__ + if(pgd_val(*pgd) & _PAGE_GATEWAY) + /* This is the permanent pmd attached to the pgd; cannot + * free it */ + return; +#endif + pgd_val(*pgd) = 0; +} #else /* * The "pgd_xxx()" functions here are trivial for a folded two-level ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040501200312.40BB74945E1@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040501200312.40BB74945E1@palinux.hppa> @ 2004-05-01 20:09 ` James Bottomley 2004-05-03 8:57 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-05-01 20:09 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Sat, 2004-05-01 at 15:03, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/05/01 14:03:11 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S head64.S > include/asm-parisc: page.h pgalloc.h pgtable.h > > Log message: > Increase the maximum physical and virtual space available to > the 64 bit kernel from 512GB to 8TB > > As jsm pointed out, we could do a depd,z on the pgd and pmd entries > instead to compress our unused bits in the flags. However, for the > moment, I elected to allocate the pte and pmd in ZONE_DMA instead. ===== arch/parisc/kernel/asm-offsets.c 1.8 vs edited ===== --- 1.8/arch/parisc/kernel/asm-offsets.c Sat May 1 05:20:09 2004 +++ edited/arch/parisc/kernel/asm-offsets.c Sat May 1 12:50:25 2004 @@ -282,8 +282,8 @@ DEFINE(ASM_BITS_PER_PGD, BITS_PER_PGD); DEFINE(ASM_BITS_PER_PMD, BITS_PER_PMD); DEFINE(ASM_BITS_PER_PTE, BITS_PER_PTE); - DEFINE(ASM_PMD_ENTRY, ((__PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); - DEFINE(ASM_PGD_ENTRY, __PAGE_OFFSET >> PGDIR_SHIFT); + DEFINE(ASM_PMD_ENTRY, ((PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); + DEFINE(ASM_PGD_ENTRY, PAGE_OFFSET >> PGDIR_SHIFT); DEFINE(ASM_PGD_ENTRY_SIZE, PGD_ENTRY_SIZE); DEFINE(ASM_PMD_ENTRY_SIZE, PMD_ENTRY_SIZE); DEFINE(ASM_PTE_ENTRY_SIZE, PTE_ENTRY_SIZE); ===== arch/parisc/kernel/entry.S 1.19 vs edited ===== --- 1.19/arch/parisc/kernel/entry.S Sat May 1 05:20:09 2004 +++ edited/arch/parisc/kernel/entry.S Sat May 1 14:58:00 2004 @@ -453,7 +453,10 @@ .endm /* Look up a PTE in a 2-Level scheme (faulting at each - * level if the entry isn't present */ + * level if the entry isn't present + * + * NOTE: we use ldw even for LP64 because our pte + * and pmd are allocated <4GB */ .macro L2_ptep pmd,pte,index,va,fault #if PT_NLEVELS == 3 EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index @@ -462,7 +465,7 @@ #endif DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ copy %r0,\pte - LDREG,s \index(\pmd),\pmd + ldw,s \index(\pmd),\pmd EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index bb,>=,n \pmd,_PAGE_PRESENT_BIT,\fault DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ @@ -475,7 +478,7 @@ .macro L3_ptep pgd,pte,index,va,fault extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index copy %r0,\pte - ldd,s \index(\pgd),\pgd + ldw,s \index(\pgd),\pgd bb,>=,n \pgd,_PAGE_PRESENT_BIT,\fault L2_ptep \pgd,\pte,\index,\va,\fault .endm ===== arch/parisc/kernel/head64.S 1.7 vs edited ===== --- 1.7/arch/parisc/kernel/head64.S Sat May 1 05:20:09 2004 +++ edited/arch/parisc/kernel/head64.S Sat May 1 12:52:13 2004 @@ -88,16 +88,16 @@ mtctl %r4,%cr24 /* Initialize kernel root pointer */ mtctl %r4,%cr25 /* Initialize user root pointer */ - std %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4) + stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4) ldo _PAGE_TABLE(%r1),%r3 - std %r3,(ASM_PMD_ENTRY * ASM_PMD_ENTRY_SIZE) (%r5) + stw %r3,(ASM_PMD_ENTRY * ASM_PMD_ENTRY_SIZE) (%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 1)*ASM_PMD_ENTRY_SIZE)(%r5) + stw %r3,((ASM_PMD_ENTRY + 1)*ASM_PMD_ENTRY_SIZE)(%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 2)*ASM_PMD_ENTRY_SIZE)(%r5) + stw %r3,((ASM_PMD_ENTRY + 2)*ASM_PMD_ENTRY_SIZE)(%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 3)*ASM_PMD_ENTRY_SIZE)(%r5) + stw %r3,((ASM_PMD_ENTRY + 3)*ASM_PMD_ENTRY_SIZE)(%r5) ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */ $pgt_fill_loop: ===== include/asm-parisc/page.h 1.8 vs edited ===== --- 1.8/include/asm-parisc/page.h Fri Apr 30 05:40:20 2004 +++ edited/include/asm-parisc/page.h Sat May 1 14:53:09 2004 @@ -40,8 +40,10 @@ * These are used to make use of C type-checking.. */ typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; +/* NOTE: even on 64 bits, these entries are __u32 because we allocate + * the pmd and pgd in ZONE_DMA (i.e. under 4GB) */ +typedef struct { __u32 pmd; } pmd_t; +typedef struct { __u32 pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #define pte_val(x) ((x).pte) @@ -89,8 +91,8 @@ */ #ifdef __LP64__ #define BITS_PER_PTE_ENTRY 3 -#define BITS_PER_PMD_ENTRY 3 -#define BITS_PER_PGD_ENTRY 3 +#define BITS_PER_PMD_ENTRY 2 +#define BITS_PER_PGD_ENTRY 2 #else #define BITS_PER_PTE_ENTRY 2 #define BITS_PER_PMD_ENTRY 2 ===== include/asm-parisc/pgalloc.h 1.10 vs edited ===== --- 1.10/include/asm-parisc/pgalloc.h Fri Apr 30 05:40:20 2004 +++ edited/include/asm-parisc/pgalloc.h Sat May 1 14:54:36 2004 @@ -30,12 +30,14 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd) { - pgd_val(*pgd) = _PAGE_TABLE + __pa((unsigned long)pmd); + pgd_val(*pgd) = _PAGE_TABLE + (__u32)__pa((unsigned long)pmd); } +/* NOTE: pmd must be in ZONE_DMA (<4GB) so the pgd pointer can be + * housed in 32 bits */ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { - pmd_t *pmd = (pmd_t *)__get_free_pages(GFP_KERNEL|__GFP_REPEAT, + pmd_t *pmd = (pmd_t *)__get_free_pages(GFP_KERNEL|__GFP_REPEAT|GFP_DMA, PMD_ORDER); if (pmd) memset(pmd, 0, PAGE_SIZE<<PMD_ORDER); @@ -65,16 +67,18 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) { - pmd_val(*pmd) = _PAGE_TABLE + __pa((unsigned long)pte); + pmd_val(*pmd) = _PAGE_TABLE + (__u32)__pa((unsigned long)pte); } #define pmd_populate(mm, pmd, pte_page) \ pmd_populate_kernel(mm, pmd, page_address(pte_page)) +/* NOTE: pte must be in ZONE_DMA (<4GB) so that the pmd pointer + * can be housed in 32 bits */ static inline struct page * pte_alloc_one(struct mm_struct *mm, unsigned long address) { - struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT); + struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|GFP_DMA); if (likely(page != NULL)) clear_page(page_address(page)); return page; @@ -83,7 +87,7 @@ static inline pte_t * pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) { - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT); + pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|GFP_DMA); if (likely(pte != NULL)) clear_page(pte); return pte; ===== include/asm-parisc/pgtable.h 1.19 vs edited ===== --- 1.19/include/asm-parisc/pgtable.h Sat May 1 05:20:20 2004 +++ edited/include/asm-parisc/pgtable.h Sat May 1 13:00:07 2004 @@ -43,9 +43,9 @@ #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) + printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) #define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) + printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) /* Note: If you change ISTACK_SIZE, you need to change the corresponding * values in vmlinux.lds and vmlinux64.lds (init_istack section). Also, @@ -65,8 +65,8 @@ #ifdef __LP64__ #define PT_NLEVELS 3 #define PT_INITIAL 4 /* Number of initial page tables */ -#define PGD_ORDER 0 /* Number of pages per pgd */ -#define PMD_ORDER 0 /* Number of pages per pmd */ +#define PGD_ORDER 1 /* Number of pages per pgd */ +#define PMD_ORDER 1 /* Number of pages per pmd */ #else #define PT_NLEVELS 2 #define PT_INITIAL 2 /* Number of initial page tables */ ^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-05-01 20:09 ` James Bottomley @ 2004-05-03 8:57 ` Joel Soete 0 siblings, 0 replies; 50+ messages in thread From: Joel Soete @ 2004-05-03 8:57 UTC (permalink / raw) To: James Bottomley, PARISC list; +Cc: parisc-linux-cvs > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S head64.S > i > clude/asm-parisc: page.h pgalloc.h pgtable.h > > Log message: > Increase the maximum physical and virtual space available to > the 64 bit kernel from 512GB to 8TB > Sincerely nice job but how will it permit me to access at least to the only all 4GB of the N4k I test when setup_bootmem() limits actually the usage to the first 2Gb? For remind: arch/parisc/mm/init.c static void __init setup_bootmem(void) { [snip] /* * Throw out ranges that are too far apart (controlled by * MAX_GAP). If CONFIG_DISCONTIGMEM wasn't implemented so * poorly, we would recommend enabling that option, but, * until it is fixed, this is the best way to go. */ printk("npmem_ranges = %d.(line 171)\n", npmem_ranges); for (i = 1; i < npmem_ranges; i++) { printk("pmem_ranges[%d].start_pfn = %ld.\n", i-1, pmem_ranges[i-1].pages); printk("pmem_ranges[%d].pages = %ld.\n", i-1, pmem_ranges[i-1].pages); printk("pmem_ranges[%d].start_pfn = %ld.\n", i, pmem_ranges[i].pages); [snip] And actual results would be: <==== return by setup_bootmem() ====> pmem_ranges[0].start_pfn = 0. pmem_ranges[0].pages = 524288. pmem_ranges[1].start_pfn = 1572864. so 1572864-524288-0=1048576 greater then MAX_GAP = 262144. I also investigate the choice of using CONFIG_DISCONTIGMEM but as far as I understand this option is foreseen when each processor has its own ram and can/want access the ram of the others (as on sun 6800): not the N4k case where all ram is shared between all processor? Thanks again for your attention, Joel ---------------------------------------------------------------------------------------- Tiscali ADSL: 35 €/mois, la meilleure offre du marché! http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040501160556.D07DC4945CA@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040501160556.D07DC4945CA@palinux.hppa> @ 2004-05-01 16:13 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-05-01 16:13 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Sat, 2004-05-01 at 11:05, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/05/01 10:05:56 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c head.S head64.S init_task.c > arch/parisc/mm : init.c > include/asm-parisc: pgtable.h > > Log message: > More magic number elimination > > Also break the assumption that sizeof(unsigned long) == sizeof(pte_t) Index: arch/parisc/kernel/asm-offsets.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/asm-offsets.c,v retrieving revision 1.5 diff -u -r1.5 asm-offsets.c --- a/arch/parisc/kernel/asm-offsets.c 30 Apr 2004 16:20:36 -0000 1.5 +++ b/arch/parisc/kernel/asm-offsets.c 1 May 2004 15:11:57 -0000 @@ -283,6 +283,10 @@ DEFINE(ASM_BITS_PER_PMD, BITS_PER_PMD); DEFINE(ASM_BITS_PER_PTE, BITS_PER_PTE); DEFINE(ASM_PMD_ENTRY, ((__PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); + DEFINE(ASM_PGD_ENTRY, __PAGE_OFFSET >> PGDIR_SHIFT); + DEFINE(ASM_PGD_ENTRY_SIZE, PGD_ENTRY_SIZE); + DEFINE(ASM_PMD_ENTRY_SIZE, PMD_ENTRY_SIZE); + DEFINE(ASM_PTE_ENTRY_SIZE, PTE_ENTRY_SIZE); BLANK(); return 0; } Index: arch/parisc/kernel/head.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head.S,v retrieving revision 1.4 diff -u -r1.4 head.S --- a/arch/parisc/kernel/head.S 25 Apr 2004 14:50:51 -0000 1.4 +++ b/arch/parisc/kernel/head.S 1 May 2004 15:11:58 -0000 @@ -83,12 +83,12 @@ mtctl %r4,%cr24 /* Initialize kernel root pointer */ mtctl %r4,%cr25 /* Initialize user root pointer */ - stw %r3,((__PAGE_OFFSET>>PGDIR_SHIFT)*4)(%r4) + stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4) ldo 0x1000(%r3),%r3 - stw %r3,(((__PAGE_OFFSET>>PGDIR_SHIFT) + 1)*4)(%r4) + stw %r3,(ASM_PGD_ENTRY + 1)*ASM_PGD_ENTRY_SIZE(%r4) ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */ $pgt_fill_loop: - stwm %r3,4(%r1) + stwm %r3,ASM_PTE_ENTRY_SIZE(%r1) ldo 0x1000(%r3),%r3 bb,>= %r3,8,$pgt_fill_loop nop Index: arch/parisc/kernel/head64.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head64.S,v retrieving revision 1.5 diff -u -r1.5 head64.S --- a/arch/parisc/kernel/head64.S 25 Apr 2004 14:50:51 -0000 1.5 +++ b/arch/parisc/kernel/head64.S 1 May 2004 15:11:58 -0000 @@ -88,20 +88,20 @@ mtctl %r4,%cr24 /* Initialize kernel root pointer */ mtctl %r4,%cr25 /* Initialize user root pointer */ - std %r3,((__PAGE_OFFSET >> PGDIR_SHIFT)*8)(%r4) + std %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4) ldo _PAGE_TABLE(%r1),%r3 - std %r3,(ASM_PMD_ENTRY * 8) (%r5) + std %r3,(ASM_PMD_ENTRY * ASM_PMD_ENTRY_SIZE) (%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 1)*8)(%r5) + std %r3,((ASM_PMD_ENTRY + 1)*ASM_PMD_ENTRY_SIZE)(%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 2)*8)(%r5) + std %r3,((ASM_PMD_ENTRY + 2)*ASM_PMD_ENTRY_SIZE)(%r5) ldo 0x1000(%r3),%r3 - std %r3,((ASM_PMD_ENTRY + 3)*8)(%r5) + std %r3,((ASM_PMD_ENTRY + 3)*ASM_PMD_ENTRY_SIZE)(%r5) ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */ $pgt_fill_loop: - std,ma %r3,8(%r1) + std,ma %r3,ASM_PTE_ENTRY_SIZE(%r1) ldo 0x1000(%r3),%r3 bb,>= %r3,8,$pgt_fill_loop nop Index: arch/parisc/kernel/init_task.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/init_task.c,v retrieving revision 1.4 diff -u -r1.4 init_task.c --- a/arch/parisc/kernel/init_task.c 30 Apr 2004 16:20:36 -0000 1.4 +++ b/arch/parisc/kernel/init_task.c 1 May 2004 15:11:58 -0000 @@ -54,9 +54,9 @@ pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE<<PGD_ORDER))) = { {0}, }; #ifdef __LP64__ -unsigned long pmd0[PTRS_PER_PMD] __attribute__ ((aligned(4096))) = { 0, }; +pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((aligned(4096))) = { {0}, }; #endif -unsigned long pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((aligned(4096))) = { 0, }; +pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((aligned(4096))) = { {0}, }; /* * Initial task structure. Index: arch/parisc/mm/init.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/mm/init.c,v retrieving revision 1.4 diff -u -r1.4 init.c --- a/arch/parisc/mm/init.c 25 Apr 2004 14:50:51 -0000 1.4 +++ b/arch/parisc/mm/init.c 1 May 2004 15:11:59 -0000 @@ -550,7 +550,7 @@ */ if (!pmd) { - pmd = (pmd_t *) alloc_bootmem_low_pages_node(NODE_DATA(0),PAGE_SIZE); + pmd = (pmd_t *) alloc_bootmem_low_pages_node(NODE_DATA(0),PAGE_SIZE << PMD_ORDER); pmd = (pmd_t *) __pa(pmd); } Index: include/asm-parisc/pgtable.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/pgtable.h,v retrieving revision 1.6 diff -u -r1.6 pgtable.h --- a/include/asm-parisc/pgtable.h 30 Apr 2004 16:20:36 -0000 1.6 +++ b/include/asm-parisc/pgtable.h 1 May 2004 15:12:18 -0000 @@ -225,7 +225,7 @@ /* initial page tables for 0-8MB for kernel */ -extern unsigned long pg0[]; +extern pte_t pg0[]; /* zero page used for uninitialized stuff */ ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040430162037.9D2B94945CD@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040430162037.9D2B94945CD@palinux.hppa> @ 2004-04-30 16:25 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-30 16:25 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Fri, 2004-04-30 at 11:20, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/30 10:20:37 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S init_task.c > include/asm-parisc: page.h pgalloc.h pgtable.h > > Log message: > Update the parametrisation of our page tables > > This fix also allows variable size pgd and pmd and thus lays the ground > work for expanding the number of page table flags we have ===== arch/parisc/kernel/asm-offsets.c 1.6 vs edited ===== --- 1.6/arch/parisc/kernel/asm-offsets.c Sun Apr 25 04:00:10 2004 +++ edited/arch/parisc/kernel/asm-offsets.c Thu Apr 29 12:52:22 2004 @@ -276,6 +276,12 @@ BLANK(); DEFINE(PA_BLOCKSTEP_BIT, 31-PT_BLOCKSTEP_BIT); DEFINE(PA_SINGLESTEP_BIT, 31-PT_SINGLESTEP_BIT); + BLANK(); + DEFINE(ASM_PMD_SHIFT, PMD_SHIFT); + DEFINE(ASM_PGDIR_SHIFT, PGDIR_SHIFT); + DEFINE(ASM_BITS_PER_PGD, BITS_PER_PGD); + DEFINE(ASM_BITS_PER_PMD, BITS_PER_PMD); + DEFINE(ASM_BITS_PER_PTE, BITS_PER_PTE); DEFINE(ASM_PMD_ENTRY, ((__PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); BLANK(); return 0; ===== arch/parisc/kernel/entry.S 1.17 vs edited ===== --- 1.17/arch/parisc/kernel/entry.S Tue Apr 27 06:20:11 2004 +++ edited/arch/parisc/kernel/entry.S Thu Apr 29 18:16:28 2004 @@ -455,21 +455,25 @@ /* Look up a PTE in a 2-Level scheme (faulting at each * level if the entry isn't present */ .macro L2_ptep pmd,pte,index,va,fault - EXTR \va,31-PMD_SHIFT,PAGE_SHIFT-BITS_PER_PMD,\index +#if PT_NLEVELS == 3 + EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index +#else + EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index +#endif copy %r0,\pte DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ LDREG,s \index(\pmd),\pmd - EXTR \va,31-PAGE_SHIFT,PAGE_SHIFT-BITS_PER_PTE,\index + EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index bb,>=,n \pmd,_PAGE_PRESENT_BIT,\fault DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ - shladd \index,BITS_PER_PTE,\pmd,\pmd + shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd LDREG %r0(\pmd),\pte /* pmd is now pte */ bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault .endm /* Look up PTE in a 3-Level scheme */ .macro L3_ptep pgd,pte,index,va,fault - extrd,u \va,63-PGDIR_SHIFT,PAGE_SHIFT-BITS_PER_PGD,\index + extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index copy %r0,\pte ldd,s \index(\pgd),\pgd bb,>=,n \pgd,_PAGE_PRESENT_BIT,\fault ===== arch/parisc/kernel/init_task.c 1.7 vs edited ===== --- 1.7/arch/parisc/kernel/init_task.c Tue Feb 3 23:41:56 2004 +++ edited/arch/parisc/kernel/init_task.c Thu Apr 29 11:42:08 2004 @@ -52,7 +52,7 @@ __attribute__((aligned(128))) __attribute__((__section__(".data.init_task"))) = { INIT_THREAD_INFO(init_task) }; -pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(4096))) = { {0}, }; +pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE<<PGD_ORDER))) = { {0}, }; #ifdef __LP64__ unsigned long pmd0[PTRS_PER_PMD] __attribute__ ((aligned(4096))) = { 0, }; #endif ===== include/asm-parisc/page.h 1.7 vs edited ===== --- 1.7/include/asm-parisc/page.h Tue Apr 27 06:20:26 2004 +++ edited/include/asm-parisc/page.h Fri Apr 30 09:16:34 2004 @@ -84,14 +84,21 @@ #endif /* !__ASSEMBLY__ */ +/* WARNING: The definitions below must match exactly to sizeof(pte_t) + * etc + */ #ifdef __LP64__ -#define BITS_PER_PTE 3 -#define BITS_PER_PMD 3 -#define BITS_PER_PGD 3 +#define BITS_PER_PTE_ENTRY 3 +#define BITS_PER_PMD_ENTRY 3 +#define BITS_PER_PGD_ENTRY 3 #else -#define BITS_PER_PTE 2 -#define BITS_PER_PMD 2 +#define BITS_PER_PTE_ENTRY 2 +#define BITS_PER_PMD_ENTRY 2 +#define BITS_PER_PGD_ENTRY BITS_PER_PMD_ENTRY #endif +#define PGD_ENTRY_SIZE (1UL << BITS_PER_PGD_ENTRY) +#define PMD_ENTRY_SIZE (1UL << BITS_PER_PMD_ENTRY) +#define PTE_ENTRY_SIZE (1UL << BITS_PER_PTE_ENTRY) /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) ===== include/asm-parisc/pgalloc.h 1.9 vs edited ===== --- 1.9/include/asm-parisc/pgalloc.h Sat Sep 27 16:43:45 2003 +++ edited/include/asm-parisc/pgalloc.h Thu Apr 29 17:07:16 2004 @@ -12,18 +12,19 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm) { - pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL); + pgd_t *pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, PGD_ORDER); + if (likely(pgd != NULL)) - clear_page(pgd); + memset(pgd, 0, PAGE_SIZE<<PGD_ORDER); return pgd; } static inline void pgd_free(pgd_t *pgd) { - free_page((unsigned long)pgd); + free_pages((unsigned long)pgd, PGD_ORDER); } -#ifdef __LP64__ +#if PT_NLEVELS == 3 /* Three Level Page Table Support for pmd's */ @@ -34,15 +35,16 @@ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { - pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT); + pmd_t *pmd = (pmd_t *)__get_free_pages(GFP_KERNEL|__GFP_REPEAT, + PMD_ORDER); if (pmd) - clear_page(pmd); + memset(pmd, 0, PAGE_SIZE<<PMD_ORDER); return pmd; } static inline void pmd_free(pmd_t *pmd) { - free_page((unsigned long)pmd); + free_pages((unsigned long)pmd, PMD_ORDER); } #else ===== include/asm-parisc/pgtable.h 1.17 vs edited ===== --- 1.17/include/asm-parisc/pgtable.h Sun Apr 25 04:00:21 2004 +++ edited/include/asm-parisc/pgtable.h Fri Apr 30 11:16:11 2004 @@ -63,41 +63,49 @@ */ #ifdef __LP64__ -#define PT_NLEVELS 3 -#define PT_INITIAL 4 /* Number of initial page tables */ +#define PT_NLEVELS 3 +#define PT_INITIAL 4 /* Number of initial page tables */ +#define PGD_ORDER 0 /* Number of pages per pgd */ +#define PMD_ORDER 0 /* Number of pages per pmd */ #else -#define PT_NLEVELS 2 -#define PT_INITIAL 2 /* Number of initial page tables */ +#define PT_NLEVELS 2 +#define PT_INITIAL 2 /* Number of initial page tables */ +#define PGD_ORDER 0 /* Number of pages per pgd */ #endif -#define MAX_ADDRBITS (PAGE_SHIFT + (PT_NLEVELS)*(PAGE_SHIFT - PT_NLEVELS)) -#define MAX_ADDRESS (1UL << MAX_ADDRBITS) - -#define SPACEID_SHIFT (MAX_ADDRBITS - 32) - -/* Definitions for 1st level */ - -#define PGDIR_SHIFT (PAGE_SHIFT + (PT_NLEVELS - 1)*(PAGE_SHIFT - PT_NLEVELS)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) -#define PTRS_PER_PGD (1UL << (PAGE_SHIFT - PT_NLEVELS)) -#define USER_PTRS_PER_PGD PTRS_PER_PGD +/* Definitions for 3rd level (we use PLD here for Page Lower directory + * because PTE_SHIFT is used lower down to mean shift that has to be + * done to get usable bits out of the PTE) */ +#define PLD_SHIFT PAGE_SHIFT +#define PLD_SIZE PAGE_SIZE +#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) +#define PTRS_PER_PTE (1UL << BITS_PER_PTE) /* Definitions for 2nd level */ #define pgtable_cache_init() do { } while (0) -#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PT_NLEVELS)) +#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) #if PT_NLEVELS == 3 -#define PTRS_PER_PMD (1UL << (PAGE_SHIFT - PT_NLEVELS)) +#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) #else -#define PTRS_PER_PMD 1 +#define BITS_PER_PMD 0 #endif +#define PTRS_PER_PMD (1UL << BITS_PER_PMD) -/* Definitions for 3rd level */ +/* Definitions for 1st level */ +#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD) +#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) +#define PTRS_PER_PGD (1UL << BITS_PER_PGD) +#define USER_PTRS_PER_PGD PTRS_PER_PGD -#define PTRS_PER_PTE (1UL << (PAGE_SHIFT - PT_NLEVELS)) +#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) +#define MAX_ADDRESS (1UL << MAX_ADDRBITS) + +#define SPACEID_SHIFT (MAX_ADDRBITS - 32) /* * pgd entries used up by user/kernel: @@ -241,7 +249,7 @@ -#ifdef __LP64__ +#if PT_NLEVELS == 3 #define pgd_page(pgd) ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) /* For 64 bit we have three level tables */ @@ -337,7 +345,7 @@ /* Find an entry in the second-level page table.. */ -#ifdef __LP64__ +#if PT_NLEVELS == 3 #define pmd_offset(dir,address) \ ((pmd_t *) pgd_page(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1))) #else ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040427171140.706074945BD@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040427171140.706074945BD@palinux.hppa> @ 2004-04-27 17:15 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-27 17:15 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Tue, 2004-04-27 at 12:11, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/27 11:11:39 > > Modified files: > . : Makefile > arch/parisc/kernel: entry.S > include/asm-parisc: page.h > > Log message: > More assembler magic entry removal. > > Also macro'ise the tlb miss handlers, making it much easier to > alter them since all the information is collated in one place ===== arch/parisc/kernel/entry.S 1.15 vs edited ===== --- 1.15/arch/parisc/kernel/entry.S Sun Apr 25 04:00:10 2004 +++ edited/arch/parisc/kernel/entry.S Tue Apr 27 11:05:46 2004 @@ -40,11 +40,13 @@ #ifdef __LP64__ #define CMPIB cmpib,* #define CMPB cmpb,* +#define COND(x) *x .level 2.0w #else #define CMPIB cmpib, #define CMPB cmpb, +#define COND(x) x .level 2.0 #endif @@ -389,6 +391,208 @@ .align 32 .endm + /* The following are simple 32 vs 64 bit instruction + * abstractions for the macros */ + .macro EXTR reg1,start,length,reg2 +#ifdef __LP64__ + extrd,u \reg1,32+\start,\length,\reg2 +#else + extrw,u \reg1,\start,\length,\reg2 +#endif + .endm + + .macro DEP reg1,start,length,reg2 +#ifdef __LP64__ + depd \reg1,32+\start,\length,\reg2 +#else + depw \reg1,\start,\length,\reg2 +#endif + .endm + + .macro DEPI val,start,length,reg +#ifdef __LP64__ + depdi \val,32+\start,\length,\reg +#else + depwi \val,\start,\length,\reg +#endif + .endm + + /* In LP64, the space contains part of the upper 32 bits of the + * fault. We have to extract this and place it in the va, + * zeroing the corresponding bits in the space register */ + .macro space_adjust spc,va,tmp +#ifdef __LP64__ + extrd,u \spc,63,SPACEID_SHIFT,\tmp + depd %r0,63,SPACEID_SHIFT,\spc + depd \tmp,31,SPACEID_SHIFT,\va +#endif + .endm + + .import swapper_pg_dir,code + + /* Get the pgd. For faults on space zero (kernel space), this + * is simply swapper_pg_dir. For user space faults, the + * pgd is stored in %cr25 */ + .macro get_pgd spc,reg + ldil L%PA(swapper_pg_dir),\reg + ldo R%PA(swapper_pg_dir)(\reg),\reg + or,COND(=) %r0,\spc,%r0 + mfctl %cr25,\reg + .endm + + /* Only allow faults on different spaces from the + * currently active one if we're the kernel */ + .macro space_check spc,tmp,fault + mfsp %sr7,\tmp + or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page + * as kernel, so defeat the space + * check if it is */ + copy \spc,\tmp + or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */ + cmpb,COND(<>),n \tmp,\spc,\fault + .endm + + /* Look up a PTE in a 2-Level scheme (faulting at each + * level if the entry isn't present */ + .macro L2_ptep pmd,pte,index,va,fault + EXTR \va,31-PMD_SHIFT,PAGE_SHIFT-BITS_PER_PMD,\index + copy %r0,\pte + DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ + LDREG,s \index(\pmd),\pmd + EXTR \va,31-PAGE_SHIFT,PAGE_SHIFT-BITS_PER_PTE,\index + bb,>=,n \pmd,_PAGE_PRESENT_BIT,\fault + DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ + shladd \index,BITS_PER_PTE,\pmd,\pmd + LDREG %r0(\pmd),\pte /* pmd is now pte */ + bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault + .endm + + /* Look up PTE in a 3-Level scheme */ + .macro L3_ptep pgd,pte,index,va,fault + extrd,u \va,63-PGDIR_SHIFT,PAGE_SHIFT-BITS_PER_PGD,\index + copy %r0,\pte + ldd,s \index(\pgd),\pgd + bb,>=,n \pgd,_PAGE_PRESENT_BIT,\fault + L2_ptep \pgd,\pte,\index,\va,\fault + .endm + + /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and + * don't needlessly dirty the cache line if it was already set */ + .macro update_ptep ptep,pte,tmp,tmp1 + ldi _PAGE_ACCESSED,\tmp1 + or \tmp1,\pte,\tmp + and,COND(<>) \tmp1,\pte,%r0 + STREG \tmp,0(\ptep) + .endm + + /* Set the dirty bit (and accessed bit). No need to be + * clever, this is only used from the dirty fault */ + .macro update_dirty ptep,pte,tmp,tmp1 + ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp + or \tmp,\pte,\pte + STREG \pte,0(\ptep) + .endm + + /* Convert the pte and prot to tlb insertion values. How + * this happens is quite subtle, read below */ + .macro make_insert_tlb spc,pte,prot + space_to_prot \spc \prot /* create prot id from space */ + /* The following is the real subtlety. This is depositing + * T <-> _PAGE_REFTRAP + * D <-> _PAGE_DIRTY + * B <-> _PAGE_DMB (memory break) + * + * Then incredible subtlety: The access rights are + * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ + * See 3-14 of the parisc 2.0 manual + * + * Finally, _PAGE_READ goes in the top bit of PL1 (so we + * trigger an access rights trap in user space if the user + * tries to read an unreadable page */ + depd \pte,8,7,\prot + + /* PAGE_USER indicates the page can be read with user privileges, + * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1 + * contains _PAGE_READ */ + extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0 + depdi 7,11,3,\prot + /* If we're a gateway page, drop PL2 back to zero for promotion + * to kernel privilege (so we can execute the page as kernel). + * Any privilege promotion page always denys read and write */ + extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0 + depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */ + + /* Get rid of prot bits and convert to page addr for iitlbt */ + + depd %r0,63,PAGE_SHIFT,\pte + extrd,u \pte,56,32,\pte + .endm + + /* Identical macro to make_insert_tlb above, except it + * makes the tlb entry for the differently formatted pa11 + * insertion instructions */ + .macro make_insert_tlb_11 spc,pte,prot + zdep \spc,30,15,\prot + dep \pte,8,7,\prot + extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0 + depi 1,12,1,\prot + extru,= \pte,_PAGE_USER_BIT,1,%r0 + depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */ + extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0 + depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */ + + /* Get rid of prot bits and convert to page addr for iitlba */ + + depi 0,31,12,\pte + extru \pte,24,25,\pte + + .endm + + /* This is for ILP32 PA2.0 only. The TLB insertion needs + * to extend into I/O space if the address is 0xfXXXXXXX + * so we extend the f's into the top word of the pte in + * this case */ + .macro f_extend pte,tmp + extrd,s \pte,44,4,\tmp + addi,<> 1,\tmp,%r0 + extrd,s \pte,63,32,\pte + .endm + + /* The alias region is an 8MB aligned 16MB to do clear and + * copy user pages at addresses congruent with the user + * virtual address. + * + * To use the alias page, you set %r26 up with the to TLB + * entry (identifying the physical page) and %r23 up with + * the from tlb entry (or nothing if only a to entry---for + * clear_user_page_asm) */ + .macro do_alias spc,tmp,tmp1,va,pte,prot,fault + cmpib,COND(<>),n 0,\spc,\fault + ldil L%(TMPALIAS_MAP_START),\tmp +#if defined(__LP64__) && (TMPALIAS_MAP_START >= 0x80000000) + /* on LP64, ldi will sign extend into the upper 32 bits, + * which is behaviour we don't want */ + depdi 0,31,32,\tmp +#endif + copy \va,\tmp1 + DEPI 0,31,23,\tmp1 + cmpb,COND(<>),n \tmp,\tmp1,\fault + ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot + depd,z \prot,8,7,\prot + /* + * OK, it is in the temp alias region, check whether "from" or "to". + * Check "subtle" note in pacache.S re: r23/r26. + */ +#ifdef __LP64__ + extrd,u,*= \va,41,1,%r0 +#else + extrw,u,= \va,9,1,%r0 +#endif + or,COND(tr) %r23,%r0,\pte + or %r26,%r0,\pte + .endm + + /* * Align fault_vector_20 on 4K boundary so that both * fault_vector_11 and fault_vector_20 are on the @@ -979,85 +1183,23 @@ #ifdef __LP64__ dtlb_miss_20w: - extrd,u spc,63,7,t1 /* adjust va */ - depd t1,31,7,va /* adjust va */ - depdi 0,63,7,spc /* adjust space */ - mfctl %cr25,ptp /* Assume user space miss */ - or,*<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extrd,u va,33,9,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,*= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,*<>,n t0,spc,dtlb_fault /* forward */ - - /* First level page table lookup */ - - ldd,s t1(ptp),ptp - extrd,u va,42,9,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dtlb_check_alias_20w - depdi 0,63,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - ldd,s t0(ptp),ptp - extrd,u va,51,9,t0 /* get third-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dtlb_check_alias_20w - depdi 0,63,12,ptp /* clear prot bits */ - - /* Third level page table lookup */ - - shladd t0,3,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldd 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dtlb_check_alias_20w - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,*<> t1,pte,%r0 /* test and nullify if already set */ - std t0,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,dtlb_fault - /* Get rid of prot bits and convert to page addr for idtlbt */ + L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w - depdi 0,63,12,pte - extrd,u pte,56,52,pte + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + idtlbt pte,prot rfir nop dtlb_check_alias_20w: - - /* Check to see if fault is in the temporary alias region */ - - cmpib,*<>,n 0,spc,dtlb_fault /* forward */ - ldil L%(TMPALIAS_MAP_START),t0 -#if (TMPALIAS_MAP_START >= 0x80000000) - depdi 0,31,32,t0 /* clear any sign extension */ -#endif - copy va,t1 - depdi 0,63,23,t1 - cmpb,*<>,n t0,t1,dtlb_fault /* forward */ - ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot - depd,z prot,8,7,prot - - /* - * OK, it is in the temp alias region, check whether "from" or "to". - * Check "subtle" note in pacache.S re: r23/r26. - */ - - extrd,u,*= va,41,1,r0 - or,*tr %r23,%r0,pte /* If "from" use "from" page */ - or,* %r26,%r0,pte /* else "to", use "to" page */ + do_alias spc,t0,t1,va,pte,prot,dtlb_fault idtlbt pte,prot @@ -1065,51 +1207,16 @@ nop nadtlb_miss_20w: - extrd,u spc,63,7,t1 /* adjust va */ - depd t1,31,7,va /* adjust va */ - depdi 0,63,7,spc /* adjust space */ - mfctl %cr25,ptp /* Assume user space miss */ - or,*<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extrd,u va,33,9,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,*= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,*<>,n t0,spc,nadtlb_fault /* forward */ - - /* First level page table lookup */ - - ldd,s t1(ptp),ptp - extrd,u va,42,9,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,nadtlb_emulate - depdi 0,63,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - ldd,s t0(ptp),ptp - extrd,u va,51,9,t0 /* get third-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,nadtlb_emulate - depdi 0,63,12,ptp /* clear prot bits */ - - /* Third level page table lookup */ - - shladd t0,3,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldd 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,nadtlb_check_flush_20w - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,nadtlb_fault - /* Get rid of prot bits and convert to page addr for idtlbt */ + L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot - depdi 0,63,12,pte - extrd,u pte,56,52,pte idtlbt pte,prot rfir @@ -1135,49 +1242,15 @@ #else dtlb_miss_11: - mfctl %cr25,ptp /* Assume user space miss */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,dtlb_fault /* forward */ - - /* First level page table lookup */ - - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dtlb_check_alias_11 - depi 0,31,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dtlb_check_alias_11 - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,<> t1,pte,%r0 /* test and nullify if already set */ - stw t0,0(ptp) /* write back pte */ - - zdep spc,30,15,prot /* create prot id from space */ - dep pte,8,7,prot /* add in prot bits from pte */ - - extru,= pte,_PAGE_NO_CACHE_BIT,1,r0 - depi 1,12,1,prot - extru,= pte,_PAGE_USER_BIT,1,r0 - depi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extru,= pte,_PAGE_GATEWAY_BIT,1,r0 - depi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + get_pgd spc,ptp - /* Get rid of prot bits and convert to page addr for idtlba */ + space_check spc,t0,dtlb_fault - depi 0,31,12,pte - extru pte,24,25,pte + L2_ptep ptp,pte,t0,va,dtlb_check_alias_11 + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb_11 spc,pte,prot mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ mtsp spc,%sr1 @@ -1218,43 +1291,16 @@ nop nadtlb_miss_11: - mfctl %cr25,ptp /* Assume user space miss */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,nadtlb_fault /* forward */ - - /* First level page table lookup */ - - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,nadtlb_emulate - depi 0,31,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,nadtlb_check_flush_11 - - zdep spc,30,15,prot /* create prot id from space */ - dep pte,8,7,prot /* add in prot bits from pte */ - - extru,= pte,_PAGE_NO_CACHE_BIT,1,r0 - depi 1,12,1,prot - extru,= pte,_PAGE_USER_BIT,1,r0 - depi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extru,= pte,_PAGE_GATEWAY_BIT,1,r0 - depi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + get_pgd spc,ptp - /* Get rid of prot bits and convert to page addr for idtlba */ + space_check spc,t0,nadtlb_fault + + L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11 + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb_11 spc,pte,prot - depi 0,31,12,pte - extru pte,24,25,pte mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ mtsp spc,%sr1 @@ -1292,120 +1338,44 @@ nop dtlb_miss_20: - mfctl %cr25,ptp /* Assume user space miss */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,dtlb_fault /* forward */ - - /* First level page table lookup */ - - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dtlb_check_alias_20 - depi 0,31,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dtlb_check_alias_20 - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,<> t1,pte,%r0 /* test and nullify if already set */ - stw t0,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,dtlb_fault - /* Get rid of prot bits and convert to page addr for idtlbt */ + L2_ptep ptp,pte,t0,va,dtlb_check_alias_20 + + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + + f_extend pte,t0 - extrd,s pte,35,4,t0 - depdi 0,63,12,pte /* clear lower 12 bits */ - addi,= 1,t0,0 - extrd,u,*tr pte,56,25,pte - extrd,s pte,56,25,pte /* bit 31:8 >> 8 */ idtlbt pte,prot rfir nop dtlb_check_alias_20: - - /* Check to see if fault is in the temporary alias region */ - - cmpib,<>,n 0,spc,dtlb_fault /* forward */ - ldil L%(TMPALIAS_MAP_START),t0 - copy va,t1 - depwi 0,31,23,t1 - cmpb,<>,n t0,t1,dtlb_fault /* forward */ - ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot - depd,z prot,8,7,prot - - /* - * OK, it is in the temp alias region, check whether "from" or "to". - * Check "subtle" note in pacache.S re: r23/r26. - */ - - extrw,u,= va,9,1,r0 - or,tr %r23,%r0,pte /* If "from" use "from" page */ - or %r26,%r0,pte /* else "to", use "to" page */ - + do_alias spc,t0,t1,va,pte,prot,dtlb_fault + idtlbt pte,prot rfir nop nadtlb_miss_20: - mfctl %cr25,ptp /* Assume user space miss */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,nadtlb_fault /* forward */ - - /* First level page table lookup */ - - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,nadtlb_emulate - depi 0,31,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,nadtlb_check_flush_20 - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + get_pgd spc,ptp - /* Get rid of prot bits and convert to page addr for idtlbt */ + space_check spc,t0,nadtlb_fault + + L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20 - extrd,s pte,35,4,t0 - depdi 0,63,12,pte /* clear lower 12 bits */ - addi,= 1,t0,0 - extrd,u,*tr pte,56,25,pte - extrd,s pte,56,25,pte /* bit 31:8 >> 8 */ + update_ptep ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + + f_extend pte,t0 + idtlbt pte,prot rfir @@ -1478,119 +1448,33 @@ * on the gateway page which is in the kernel address space. */ - extrd,u spc,63,7,t1 /* adjust va */ - depd t1,31,7,va /* adjust va */ - depdi 0,63,7,spc /* adjust space */ - cmpib,*= 0,spc,itlb_miss_kernel_20w - extrd,u va,33,9,t1 /* Get pgd index */ - - mfctl %cr25,ptp /* load user pgd */ - - mfsp %sr7,t0 /* Get current space */ - or,*= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,*<>,n t0,spc,itlb_fault /* forward */ - - /* First level page table lookup */ - -itlb_miss_common_20w: - ldd,s t1(ptp),ptp - extrd,u va,42,9,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,itlb_fault - depdi 0,63,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,itlb_fault - ldd,s t0(ptp),ptp - extrd,u va,51,9,t0 /* get third-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,itlb_fault - depdi 0,63,12,ptp /* clear prot bits */ + L3_ptep ptp,pte,t0,va,itlb_fault - /* Third level page table lookup */ + update_ptep ptp,pte,t0,t1 - shladd t0,3,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldd 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,itlb_fault - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,*<> t1,pte,%r0 /* test and nullify if already set */ - std t0,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ - - /* Get rid of prot bits and convert to page addr for iitlbt */ - - depdi 0,63,12,pte - extrd,u pte,56,32,pte + make_insert_tlb spc,pte,prot + iitlbt pte,prot rfir nop -itlb_miss_kernel_20w: - b itlb_miss_common_20w - mfctl %cr24,ptp /* Load kernel pgd */ #else itlb_miss_11: + get_pgd spc,ptp - /* - * I miss is a little different, since we allow users to fault - * on the gateway page which is in the kernel address space. - */ - - cmpib,= 0,spc,itlb_miss_kernel_11 - extru va,9,10,t1 /* Get pgd index */ - - mfctl %cr25,ptp /* load user pgd */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,itlb_fault /* forward */ + space_check spc,t0,itlb_fault - /* First level page table lookup */ + L2_ptep ptp,pte,t0,va,itlb_fault -itlb_miss_common_11: - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,itlb_fault - depi 0,31,12,ptp /* clear prot bits */ + update_ptep ptp,pte,t0,t1 - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,itlb_fault - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,<> t1,pte,%r0 /* test and nullify if already set */ - stw t0,0(ptp) /* write back pte */ - - zdep spc,30,15,prot /* create prot id from space */ - dep pte,8,7,prot /* add in prot bits from pte */ - - extru,= pte,_PAGE_NO_CACHE_BIT,1,r0 - depi 1,12,1,prot - extru,= pte,_PAGE_USER_BIT,1,r0 - depi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extru,= pte,_PAGE_GATEWAY_BIT,1,r0 - depi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ - - /* Get rid of prot bits and convert to page addr for iitlba */ - - depi 0,31,12,pte - extru pte,24,25,pte + make_insert_tlb_11 spc,pte,prot mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ mtsp spc,%sr1 @@ -1603,106 +1487,35 @@ rfir nop -itlb_miss_kernel_11: - b itlb_miss_common_11 - mfctl %cr24,ptp /* Load kernel pgd */ - itlb_miss_20: + get_pgd spc,ptp - /* - * I miss is a little different, since we allow users to fault - * on the gateway page which is in the kernel address space. - */ - - cmpib,= 0,spc,itlb_miss_kernel_20 - extru va,9,10,t1 /* Get pgd index */ - - mfctl %cr25,ptp /* load user pgd */ + space_check spc,t0,itlb_fault - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,itlb_fault /* forward */ + L2_ptep ptp,pte,t0,va,itlb_fault - /* First level page table lookup */ + update_ptep ptp,pte,t0,t1 -itlb_miss_common_20: - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,itlb_fault - depi 0,31,12,ptp /* clear prot bits */ + make_insert_tlb spc,pte,prot - /* Second level page table lookup */ + f_extend pte,t0 - sh2addl t0,ptp,ptp - ldi _PAGE_ACCESSED,t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,itlb_fault - - /* Check whether the "accessed" bit was set, otherwise do so */ - - or t1,pte,t0 /* t0 has R bit set */ - and,<> t1,pte,%r0 /* test and nullify if already set */ - stw t0,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ - - /* Get rid of prot bits and convert to page addr for iitlbt */ - - extrd,s pte,35,4,t0 - depdi 0,63,12,pte /* clear lower 12 bits */ - addi,= 1,t0,0 - extrd,u,*tr pte,56,25,pte - extrd,s pte,56,25,pte /* bit 31:8 >> 8 */ iitlbt pte,prot rfir nop - -itlb_miss_kernel_20: - b itlb_miss_common_20 - mfctl %cr24,ptp /* Load kernel pgd */ #endif #ifdef __LP64__ dbit_trap_20w: - extrd,u spc,63,7,t1 /* adjust va */ - depd t1,31,7,va /* adjust va */ - depdi 0,1,2,va /* adjust va */ - depdi 0,63,7,spc /* adjust space */ - mfctl %cr25,ptp /* Assume user space miss */ - or,*<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extrd,u va,33,9,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,*= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,*<>,n t0,spc,dbit_fault /* forward */ - - /* First level page table lookup */ - - ldd,s t1(ptp),ptp - extrd,u va,42,9,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dbit_fault - depdi 0,63,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - ldd,s t0(ptp),ptp - extrd,u va,51,9,t0 /* get third-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dbit_fault - depdi 0,63,12,ptp /* clear prot bits */ + space_adjust spc,va,t0 + get_pgd spc,ptp + space_check spc,t0,dbit_fault - /* Third level page table lookup */ + L3_ptep ptp,pte,t0,va,dbit_fault - shladd t0,3,ptp,ptp #ifdef CONFIG_SMP CMPIB=,n 0,spc,dbit_nolock_20w ldil L%PA(pa_dbit_lock),t0 @@ -1715,27 +1528,10 @@ dbit_nolock_20w: #endif - ldi (_PAGE_ACCESSED|_PAGE_DIRTY),t1 - ldd 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dbit_fault - - /* Set Accessed and Dirty bits in the pte */ - - or t1,pte,pte - std pte,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ + update_dirty ptp,pte,t0,t1 - /* Get rid of prot bits and convert to page addr for idtlbt */ - - depdi 0,63,12,pte - extrd,u pte,56,52,pte + make_insert_tlb spc,pte,prot + idtlbt pte,prot #ifdef CONFIG_SMP CMPIB=,n 0,spc,dbit_nounlock_20w @@ -1750,25 +1546,13 @@ #else dbit_trap_11: - mfctl %cr25,ptp /* Assume user space trap */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ - - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,dbit_fault /* forward */ - /* First level page table lookup */ + get_pgd spc,ptp - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dbit_fault - depi 0,31,12,ptp /* clear prot bits */ + space_check spc,t0,dbit_fault - /* Second level page table lookup */ + L2_ptep ptp,pte,t0,va,dbit_fault - sh2addl t0,ptp,ptp #ifdef CONFIG_SMP CMPIB=,n 0,spc,dbit_nolock_11 ldil L%PA(pa_dbit_lock),t0 @@ -1781,29 +1565,9 @@ dbit_nolock_11: #endif - ldi (_PAGE_ACCESSED|_PAGE_DIRTY),t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dbit_fault - - /* Set Accessed and Dirty bits in the pte */ - - or t1,pte,pte - stw pte,0(ptp) /* write back pte */ - - zdep spc,30,15,prot /* create prot id from space */ - dep pte,8,7,prot /* add in prot bits from pte */ - - extru,= pte,_PAGE_NO_CACHE_BIT,1,r0 - depi 1,12,1,prot - extru,= pte,_PAGE_USER_BIT,1,r0 - depi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extru,= pte,_PAGE_GATEWAY_BIT,1,r0 - depi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ - - /* Get rid of prot bits and convert to page addr for idtlba */ + update_dirty ptp,pte,t0,t1 - depi 0,31,12,pte - extru pte,24,25,pte + make_insert_tlb_11 spc,pte,prot mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */ mtsp spc,%sr1 @@ -1824,25 +1588,12 @@ nop dbit_trap_20: - mfctl %cr25,ptp /* Assume user space trap */ - or,<> %r0,spc,%r0 /* If it is user space, nullify */ - mfctl %cr24,ptp /* Load kernel pgd instead */ - extru va,9,10,t1 /* Get pgd index */ + get_pgd spc,ptp - mfsp %sr7,t0 /* Get current space */ - or,= %r0,t0,%r0 /* If kernel, nullify following test */ - cmpb,<>,n t0,spc,dbit_fault /* forward */ + space_check spc,t0,dbit_fault - /* First level page table lookup */ + L2_ptep ptp,pte,t0,va,dbit_fault - ldwx,s t1(ptp),ptp - extru va,19,10,t0 /* get second-level index */ - bb,>=,n ptp,_PAGE_PRESENT_BIT,dbit_fault - depi 0,31,12,ptp /* clear prot bits */ - - /* Second level page table lookup */ - - sh2addl t0,ptp,ptp #ifdef CONFIG_SMP CMPIB=,n 0,spc,dbit_nolock_20 ldil L%PA(pa_dbit_lock),t0 @@ -1855,28 +1606,12 @@ dbit_nolock_20: #endif - ldi (_PAGE_ACCESSED|_PAGE_DIRTY),t1 - ldw 0(ptp),pte - bb,>=,n pte,_PAGE_PRESENT_BIT,dbit_fault - - /* Set Accessed and Dirty bits in the pte */ - - or t1,pte,pte - stw pte,0(ptp) /* write back pte */ - - space_to_prot spc prot /* create prot id from space */ - depd pte,8,7,prot /* add in prot bits from pte */ - - extrd,u,*= pte,_PAGE_USER_BIT+32,1,r0 - depdi 7,11,3,prot /* Set for user space (1 rsvd for read) */ - extrd,u,*= pte,_PAGE_GATEWAY_BIT+32,1,r0 - depdi 0,11,2,prot /* If Gateway, Set PL2 to 0 */ - - extrd,s pte,35,4,t0 - depdi 0,63,12,pte /* clear lower 12 bits */ - addi,= 1,t0,0 - extrd,u,*tr pte,56,25,pte - extrd,s pte,56,25,pte /* bit 31:8 >> 8 */ + update_dirty ptp,pte,t0,t1 + + make_insert_tlb spc,pte,prot + + f_extend pte,t0 + idtlbt pte,prot #ifdef CONFIG_SMP ===== include/asm-parisc/page.h 1.6 vs edited ===== --- 1.6/include/asm-parisc/page.h Sun Apr 25 04:00:21 2004 +++ edited/include/asm-parisc/page.h Tue Apr 27 11:02:42 2004 @@ -84,6 +84,15 @@ #endif /* !__ASSEMBLY__ */ +#ifdef __LP64__ +#define BITS_PER_PTE 3 +#define BITS_PER_PMD 3 +#define BITS_PER_PGD 3 +#else +#define BITS_PER_PTE 2 +#define BITS_PER_PMD 2 +#endif + /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040425145051.10F5C4942B8@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040425145051.10F5C4942B8@palinux.hppa> @ 2004-04-25 14:55 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-25 14:55 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Sun, 2004-04-25 at 09:50, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/25 08:50:51 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S head.S head64.S > pacache.S vmlinux.lds.S > arch/parisc/mm : init.c > include/asm-parisc: fixmap.h page.h pgtable.h > > Log message: > Eliminate some Magic numbers > > Also move fixed mapping definitions into fixmap.h Index: arch/parisc/kernel/asm-offsets.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/asm-offsets.c,v retrieving revision 1.3 diff -u -r1.3 asm-offsets.c --- a/arch/parisc/kernel/asm-offsets.c 17 Jan 2004 06:39:24 -0000 1.3 +++ b/arch/parisc/kernel/asm-offsets.c 25 Apr 2004 14:48:12 -0000 @@ -32,6 +32,7 @@ #include <linux/thread_info.h> #include <linux/version.h> #include <linux/ptrace.h> +#include <asm/pgtable.h> #include <asm/ptrace.h> #include <asm/processor.h> @@ -275,6 +276,7 @@ BLANK(); DEFINE(PA_BLOCKSTEP_BIT, 31-PT_BLOCKSTEP_BIT); DEFINE(PA_SINGLESTEP_BIT, 31-PT_SINGLESTEP_BIT); + DEFINE(ASM_PMD_ENTRY, ((__PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); BLANK(); return 0; } Index: arch/parisc/kernel/entry.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/entry.S,v retrieving revision 1.7 diff -u -r1.7 entry.S --- a/arch/parisc/kernel/entry.S 7 Feb 2004 18:32:50 -0000 1.7 +++ b/arch/parisc/kernel/entry.S 25 Apr 2004 14:48:14 -0000 @@ -1041,6 +1041,9 @@ cmpib,*<>,n 0,spc,dtlb_fault /* forward */ ldil L%(TMPALIAS_MAP_START),t0 +#if (TMPALIAS_MAP_START >= 0x80000000) + depdi 0,31,32,t0 /* clear any sign extension */ +#endif copy va,t1 depdi 0,63,23,t1 cmpb,*<>,n t0,t1,dtlb_fault /* forward */ Index: arch/parisc/kernel/head.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head.S,v retrieving revision 1.3 diff -u -r1.3 head.S --- a/arch/parisc/kernel/head.S 17 Jan 2004 15:00:32 -0000 1.3 +++ b/arch/parisc/kernel/head.S 25 Apr 2004 14:48:15 -0000 @@ -83,13 +83,9 @@ mtctl %r4,%cr24 /* Initialize kernel root pointer */ mtctl %r4,%cr25 /* Initialize user root pointer */ -#if (__PAGE_OFFSET != 0x10000000UL) -Error! Code below (the next two stw's) needs to be changed -#endif - - stw %r3,0x100(%r4) /* Hardwired 0x1... kernel Vaddr start*/ + stw %r3,((__PAGE_OFFSET>>PGDIR_SHIFT)*4)(%r4) ldo 0x1000(%r3),%r3 - stw %r3,0x104(%r4) + stw %r3,(((__PAGE_OFFSET>>PGDIR_SHIFT) + 1)*4)(%r4) ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */ $pgt_fill_loop: stwm %r3,4(%r1) Index: arch/parisc/kernel/head64.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head64.S,v retrieving revision 1.4 diff -u -r1.4 head64.S --- a/arch/parisc/kernel/head64.S 7 Feb 2004 17:56:51 -0000 1.4 +++ b/arch/parisc/kernel/head64.S 25 Apr 2004 14:48:15 -0000 @@ -88,20 +88,16 @@ mtctl %r4,%cr24 /* Initialize kernel root pointer */ mtctl %r4,%cr25 /* Initialize user root pointer */ -#if (__PAGE_OFFSET != 0x10000000UL) -Error! Code below (the next five std's) needs to be changed -#endif - - std %r3,0x00(%r4) /* Hardwired 0x1... kernel Vaddr start*/ + std %r3,((__PAGE_OFFSET >> PGDIR_SHIFT)*8)(%r4) ldo _PAGE_TABLE(%r1),%r3 - std %r3,0x400(%r5) /* Hardwired 0x1... kernel Vaddr start*/ + std %r3,(ASM_PMD_ENTRY * 8) (%r5) ldo 0x1000(%r3),%r3 - std %r3,0x408(%r5) + std %r3,((ASM_PMD_ENTRY + 1)*8)(%r5) ldo 0x1000(%r3),%r3 - std %r3,0x410(%r5) + std %r3,((ASM_PMD_ENTRY + 2)*8)(%r5) ldo 0x1000(%r3),%r3 - std %r3,0x418(%r5) + std %r3,((ASM_PMD_ENTRY + 3)*8)(%r5) ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */ $pgt_fill_loop: Index: arch/parisc/kernel/pacache.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/pacache.S,v retrieving revision 1.5 diff -u -r1.5 pacache.S --- a/arch/parisc/kernel/pacache.S 5 Apr 2004 02:47:39 -0000 1.5 +++ b/arch/parisc/kernel/pacache.S 25 Apr 2004 14:48:16 -0000 @@ -350,10 +350,6 @@ .procend -#if (TMPALIAS_MAP_START >= 0x80000000UL) -Warning TMPALIAS_MAP_START changed. If > 2 Gb, code in pacache.S is bogus -#endif - /* * NOTE: Code in clear_user_page has a hard coded dependency on the * maximum alias boundary being 4 Mb. We've been assured by the @@ -490,6 +486,9 @@ ldil L%(TMPALIAS_MAP_START),%r28 #ifdef __LP64__ +#if (TMPALIAS_MAP_START >= 0x80000000) + depdi 0,31,32,%r28 /* clear any sign extension */ +#endif extrd,u %r26,56,32,%r26 /* convert phys addr to tlb insert format */ depd %r25,63,22,%r28 /* Form aliased virtual address 'to' */ depdi 0,63,12,%r28 /* Clear any offset bits */ Index: arch/parisc/kernel/vmlinux.lds.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/vmlinux.lds.S,v retrieving revision 1.11 diff -u -r1.11 vmlinux.lds.S --- a/arch/parisc/kernel/vmlinux.lds.S 23 Apr 2004 13:57:54 -0000 1.11 +++ b/arch/parisc/kernel/vmlinux.lds.S 25 Apr 2004 14:48:16 -0000 @@ -26,6 +26,7 @@ #include <asm-generic/vmlinux.lds.h> /* needed for the processor specific cache alignment size */ #include <asm/cache.h> +#include <asm/page.h> /* ld script to make hppa Linux kernel */ #ifndef CONFIG_PARISC64 @@ -45,7 +46,7 @@ SECTIONS { - . = 0x10100000; + . = KERNEL_BINARY_TEXT_START; _text = .; /* Text and read-only data */ .text ALIGN(16) : { Index: arch/parisc/mm/init.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/mm/init.c,v retrieving revision 1.3 diff -u -r1.3 init.c --- a/arch/parisc/mm/init.c 29 Sep 2003 16:05:00 -0000 1.3 +++ b/arch/parisc/mm/init.c 25 Apr 2004 14:48:17 -0000 @@ -424,7 +424,12 @@ * a hole of 4kB between each vmalloced area for the same reason. */ -#define MAP_START 0x4000 /* Leave room for gateway page expansion */ + /* Leave room for gateway page expansion */ +#if KERNEL_MAP_START < GATEWAY_PAGE_SIZE +#error KERNEL_MAP_START is in gateway reserved region +#endif +#define MAP_START (KERNEL_MAP_START) + #define VM_MAP_OFFSET (32*1024) #define SET_MAP_OFFSET(x) ((void *)(((unsigned long)(x) + VM_MAP_OFFSET) \ & ~(VM_MAP_OFFSET-1))) Index: include/asm-parisc/fixmap.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/fixmap.h,v retrieving revision 1.1 diff -u -r1.1 fixmap.h --- a/include/asm-parisc/fixmap.h 29 Jul 2003 17:02:03 -0000 1.1 +++ b/include/asm-parisc/fixmap.h 25 Apr 2004 14:48:36 -0000 @@ -2,18 +2,22 @@ #define _ASM_FIXMAP_H /* - * Allocate a 8 Mb temporary mapping area for copy_user_page/clear_user_page. - * This area needs to be aligned on a 8 Mb boundary. + * This file defines the locations of the fixed mappings on parisc. * - * FIXME: + * All of the values in this file are machine virtual addresses. * - * For PA-RISC, this has no meaning. It is starting to be used on x86 - * for vsyscalls. PA will probably do this using space registers. - */ + * All of the values in this file must be <4GB (because of assembly + * loading restrictions). If you place this region anywhere above + * __PAGE_OFFSET, you must adjust the memory map accordingly */ -/* This TMPALIAS_MAP_START reserves some of the memory where the - * FIXMAP region is on x86. It's only real use is to constrain - * VMALLOC_END (see pktable.h) */ -#define TMPALIAS_MAP_START (__PAGE_OFFSET - 0x01000000) +/* The alias region is used in kernel space to do copy/clear to or + * from areas congruently mapped with user space. It is 8MB large + * and must be 16MB aligned */ +#define TMPALIAS_MAP_START ((__PAGE_OFFSET) - 16*1024*1024) +/* This is the kernel area for all maps (vmalloc, dma etc.) most + * usually, it extends up to TMPALIAS_MAP_START. Virtual addresses + * 0..GATEWAY_PAGE_SIZE are reserved for the gateway page */ +#define KERNEL_MAP_START (GATEWAY_PAGE_SIZE) +#define KERNEL_MAP_END (TMPALIAS_MAP_START) #endif Index: include/asm-parisc/page.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/page.h,v retrieving revision 1.2 diff -u -r1.2 page.h --- a/include/asm-parisc/page.h 25 Sep 2003 01:07:21 -0000 1.2 +++ b/include/asm-parisc/page.h 25 Apr 2004 14:48:36 -0000 @@ -89,9 +89,22 @@ #define LINUX_GATEWAY_SPACE 0 + +/* This governs the relationship between virtual and physical addresses. + * If you alter it, make sure to take care of our various fixed mapping + * segments in fixmap.h */ #define __PAGE_OFFSET (0x10000000) #define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET) + +/* The size of the gateway page (we leave lots of room for expansion) */ +#define GATEWAY_PAGE_SIZE 0x4000 + +/* The start of the actual kernel binary---used in vmlinux.lds.S + * Leave some space after __PAGE_OFFSET for detecting kernel null + * ptr derefs */ +#define KERNEL_BINARY_TEXT_START (__PAGE_OFFSET + 0x100000) + /* These macros don't work for 64-bit C code -- don't allow in C at all */ #ifdef __ASSEMBLY__ # define PA(x) ((x)-__PAGE_OFFSET) Index: include/asm-parisc/pgtable.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/pgtable.h,v retrieving revision 1.4 diff -u -r1.4 pgtable.h --- a/include/asm-parisc/pgtable.h 27 Jan 2004 18:46:14 -0000 1.4 +++ b/include/asm-parisc/pgtable.h 25 Apr 2004 14:48:37 -0000 @@ -110,7 +110,7 @@ #define PCXL_DMA_MAP_SIZE (8*1024*1024) #define VMALLOC_START ((unsigned long)vmalloc_start) /* this is a fixmap remnant, see fixmap.h */ -#define VMALLOC_END (TMPALIAS_MAP_START) +#define VMALLOC_END (KERNEL_MAP_END) #endif /* NB: The tlb miss handlers make certain assumptions about the order */ ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040414174535.81173494194@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040414174535.81173494194@palinux.hppa> @ 2004-04-14 17:53 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-14 17:53 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Wed, 2004-04-14 at 12:45, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/14 11:45:35 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c sys_parisc.c > > Log message: > Make all shared mappings and all file mappings (including MAP_PRIVATE) > equivalently mapped. > > This allows us only to flush a single space again in flush_dcache_page(). > > The flip side is that now all shared libraries are going to be mapped > on 4MB boundaries. This only wastes virtual space, but it may run us > out of mappings faster than would otherwise happen in ILP32 processes. Index: arch/parisc/kernel/cache.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/cache.c,v retrieving revision 1.9 diff -u -r1.9 cache.c --- a/arch/parisc/kernel/cache.c 12 Apr 2004 15:48:00 -0000 1.9 +++ b/arch/parisc/kernel/cache.c 14 Apr 2004 17:42:54 -0000 @@ -265,12 +265,16 @@ __flush_cache_page(mpnt, addr); - break; + /* If we find an address to flush, that will also + * bring all the private mappings up to date (see + * comment below) */ + return; } - /* Private mappings will not have congruent addresses, so we - * have to flush each of them individually to make the change - * in the kernel page visible */ + /* we have carefully arranged in arch_get_unmapped_area() that + * *any* mappings of a file are always congruently mapped (whether + * declared as MAP_PRIVATE or MAP_SHARED), so we only need + * to flush one address here too */ list_for_each(l, &page->mapping->i_mmap) { struct vm_area_struct *mpnt; unsigned long off, addr; @@ -293,6 +297,8 @@ continue; __flush_cache_page(mpnt, addr); + + return; } } EXPORT_SYMBOL(__flush_dcache_page); Index: arch/parisc/kernel/sys_parisc.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/sys_parisc.c,v retrieving revision 1.21 diff -u -r1.21 sys_parisc.c --- a/arch/parisc/kernel/sys_parisc.c 16 Mar 2004 15:39:55 -0000 1.21 +++ b/arch/parisc/kernel/sys_parisc.c 14 Apr 2004 17:42:54 -0000 @@ -93,7 +93,7 @@ unsigned long addr, unsigned long len, unsigned long pgoff) { struct vm_area_struct *vma; - int offset = get_offset(mapping); + int offset = mapping ? get_offset(mapping) : 0; addr = DCACHE_ALIGN(addr - offset) + offset; @@ -117,8 +117,10 @@ if (!addr) addr = TASK_UNMAPPED_BASE; - if (filp && (flags & MAP_SHARED)) { + if (filp) { addr = get_shared_area(filp->f_mapping, addr, len, pgoff); + } else if(flags & MAP_SHARED) { + addr = get_shared_area(NULL, addr, len, pgoff); } else { addr = get_unshared_area(addr, len); } ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040412154800.D31F6494194@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040412154800.D31F6494194@palinux.hppa> @ 2004-04-12 15:55 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-12 15:55 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Mon, 2004-04-12 at 10:48, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/12 09:48:00 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c > > Log message: > According to recent discussion on the parisc list, it's far more > expensive to walk the i_mmap_shared list to find our current mm than > it is simply to change the space registers to flush the first mm we > find. This change updates __flush_dcache_page() accordingly. Index: arch/parisc/kernel/cache.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/cache.c,v retrieving revision 1.8 diff -u -r1.8 cache.c --- a/arch/parisc/kernel/cache.c 7 Apr 2004 00:49:01 -0000 1.8 +++ b/arch/parisc/kernel/cache.c 12 Apr 2004 15:44:55 -0000 @@ -229,9 +229,7 @@ void __flush_dcache_page(struct page *page) { - struct mm_struct *mm = current->active_mm; struct list_head *l; - struct vm_area_struct *anyvma = NULL; flush_kernel_dcache_page(page_address(page)); @@ -265,31 +263,10 @@ if (!translation_exists(mpnt, addr)) continue; - anyvma = mpnt; - - /* - * We try first to find a page in our current user process - */ - if (mpnt->vm_mm != mm) - continue; - - __flush_cache_page(mpnt, addr); - /* All user shared mappings should be equivalently mapped, - * so once we've flushed one we should be ok - */ - goto flush_unshared; + break; } - - /* OK, shared page but not in our current process' address space */ - if (anyvma) { - unsigned long addr = anyvma->vm_start - + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); - __flush_cache_page(anyvma, addr); - } - - flush_unshared: /* Private mappings will not have congruent addresses, so we * have to flush each of them individually to make the change ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040407004901.031D3494194@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040407004901.031D3494194@palinux.hppa> @ 2004-04-07 0:54 ` James Bottomley 2004-04-08 6:15 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-04-07 0:54 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Tue, 2004-04-06 at 19:49, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/06 18:49:01 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c > include/asm-parisc: cacheflush.h > > Log message: > Optimise flush_cache_page > > Now that we have a way of checking translations for a page, don't bother > flushing if there's no translation. Index: arch/parisc/kernel/cache.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/cache.c,v retrieving revision 1.7 diff -u -r1.7 cache.c --- a/arch/parisc/kernel/cache.c 6 Apr 2004 21:34:46 -0000 1.7 +++ b/arch/parisc/kernel/cache.c 7 Apr 2004 00:16:55 -0000 @@ -227,32 +227,6 @@ disable_sr_hashing_asm(srhash_type); } -/* Simple function to work out if we have an existing address translation - * for a user space vma. */ -static inline int translation_exists(struct vm_area_struct *vma, - unsigned long addr) -{ - pgd_t *pgd = pgd_offset(vma->vm_mm, addr); - pmd_t *pmd; - pte_t *pte; - - if(pgd_none(*pgd)) - return 0; - - pmd = pmd_offset(pgd, addr); - if(pmd_none(*pmd) || pmd_bad(*pmd)) - return 0; - - pte = pte_offset_map(pmd, addr); - - /* The PA flush mappings show up as pte_none, but they're - * valid none the less */ - if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0)) - return 0; - return 1; -} - - void __flush_dcache_page(struct page *page) { struct mm_struct *mm = current->active_mm; @@ -300,7 +274,7 @@ continue; - flush_cache_page(mpnt, addr); + __flush_cache_page(mpnt, addr); /* All user shared mappings should be equivalently mapped, * so once we've flushed one we should be ok @@ -312,7 +286,7 @@ if (anyvma) { unsigned long addr = anyvma->vm_start + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); - flush_cache_page(anyvma, addr); + __flush_cache_page(anyvma, addr); } flush_unshared: @@ -341,7 +315,7 @@ if(!translation_exists(mpnt, addr)) continue; - flush_cache_page(mpnt, addr); + __flush_cache_page(mpnt, addr); } } EXPORT_SYMBOL(__flush_dcache_page); Index: include/asm-parisc/cacheflush.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/cacheflush.h,v retrieving revision 1.8 diff -u -r1.8 cacheflush.h --- a/include/asm-parisc/cacheflush.h 5 Apr 2004 17:41:30 -0000 1.8 +++ b/include/asm-parisc/cacheflush.h 7 Apr 2004 00:17:15 -0000 @@ -107,6 +107,32 @@ } } +/* Simple function to work out if we have an existing address translation + * for a user space vma. */ +static inline int translation_exists(struct vm_area_struct *vma, + unsigned long addr) +{ + pgd_t *pgd = pgd_offset(vma->vm_mm, addr); + pmd_t *pmd; + pte_t *pte; + + if(pgd_none(*pgd)) + return 0; + + pmd = pmd_offset(pgd, addr); + if(pmd_none(*pmd) || pmd_bad(*pmd)) + return 0; + + pte = pte_offset_map(pmd, addr); + + /* The PA flush mappings show up as pte_none, but they're + * valid none the less */ + if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0)) + return 0; + return 1; +} + + /* Private function to flush a page from the cache of a non-current * process. cr25 contains the Page Directory of the current user * process; we're going to hijack both it and the user space %sr3 to @@ -141,17 +167,25 @@ } static inline void -flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) +__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) { - BUG_ON(!vma->vm_mm->context); - - if (vma->vm_mm->context == mfsp(3)) { + if (likely(vma->vm_mm->context == mfsp(3))) { flush_user_dcache_page(vmaddr); if (vma->vm_flags & VM_EXEC) flush_user_icache_page(vmaddr); } else { flush_user_cache_page_non_current(vma, vmaddr); } +} + +static inline void +flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) +{ + BUG_ON(!vma->vm_mm->context); + + if(likely(translation_exists(vma, vmaddr))) + __flush_cache_page(vma, vmaddr); + } #endif ^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-04-07 0:54 ` James Bottomley @ 2004-04-08 6:15 ` Joel Soete 2004-04-08 12:36 ` James Bottomley 0 siblings, 1 reply; 50+ messages in thread From: Joel Soete @ 2004-04-08 6:15 UTC (permalink / raw) To: James Bottomley; +Cc: parisc-linux Hi all, Sorry first for bad wrapping (known pb with webmail interface :( ). Now as far as remember .h files are headers and so should only contains declaration of function and not their definition excepted if they are very short (imho 3 line max) but that is a personal limit: does it exist a common agreement on this limit? And here why changing translation_exists() definition location? That said, I tested 2.6.5-pa5 32bit on a b2k and 64bits (gcc-3.0.4 from ftp.p-l.org) on a n4k and they works fine. (I couldn't just reproduce Grant pb because no usb device available :( ) Sorry if I annoye with philosophical question and thanks for great job as well as additional for info, Joel > -- Original Message -- > From: James Bottomley <James.Bottomley@steeleye.com> > To: PARISC list <parisc-linux@lists.parisc-linux.org> > Date: 06 Apr 2004 19:54:21 -0500 > Cc: parisc-linux-cvs@lists.parisc-linux.org > Subject: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb > > > On Tue, 2004-04-06 at 19:49, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/06 18:49:01 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c > include/asm-parisc: cach > flush.h > > Log message: > Optimise flush_cache_page > > Now that we have a way of checking translations for a page, don't bother > flushing if there's no translation. Index: arch/parisc/kernel/cache.c ===================================== > ============================= RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/cache.c,v retrieving revision 1.7 diff -u -r1.7 cache.c --- a/arch/parisc/kernel/cache.c 6 Apr 2004 21:34:46 -0000 1.7 +++ b/arch/parisc/kernel/cache.c 7 Apr 2004 00:16: > 5 -0000 @@ -227,32 +227,6 @@ disable_sr_hashing_asm(srhash_type); } -/* Simple function to work out if we have an existing address translation - * for a user space vma. */ -static inline int translation_exists(struct vm_area_struct *vma, - > unsigned long addr) -{ - pgd_t *pgd = pgd_offset(vma->vm_mm, addr); - pmd_t *pmd; - pte_t *pte; - - if(pgd_none(*pgd)) - return 0; - - pmd = pmd_offset(pgd, addr); - if(pmd_none(*pmd) || pmd_bad(*pmd)) - return 0; - - pte = pte_o > fset_map(pmd, addr); - - /* The PA flush mappings show up as pte_none, but they're - * valid none the less */ - if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0)) - return 0; - return 1; -} - - void __flush_dcache_page(struct p > ge *page) { struct mm_struct *mm = current->active_mm; @@ -300,7 +274,7 @@ continue; - flush_cache_page(mpnt, addr); + __flush_cache_page(mpnt, addr); /* All user shared mappings should be equivalently mapped, * so once > e've flushed one we should be ok @@ -312,7 +286,7 @@ if (anyvma) { unsigned long addr = anyvma->vm_start + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); - flush_cache_page(anyvma, addr); + __flush_cache_page(anyvma, addr); } > flush_unshared: @@ -341,7 +315,7 @@ if(!translation_exists(mpnt, addr)) continue; - flush_cache_page(mpnt, addr); + __flush_cache_page(mpnt, addr); } } EXPORT_SYMBOL(__flush_dcache_page); Index: include/asm-parisc/cacheflush. > =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/cacheflush.h,v retrieving revision 1.8 diff -u -r1.8 cacheflush.h --- a/include/asm-parisc/cacheflush.h 5 Apr 2004 17:41:30 -0000 > .8 +++ b/include/asm-parisc/cacheflush.h 7 Apr 2004 00:17:15 -0000 @@ -107,6 +107,32 @@ } } +/* Simple function to work out if we have an existing address translation + * for a user space vma. */ +static inline int translation_exists(struc > vm_area_struct *vma, + unsigned long addr) +{ + pgd_t *pgd = pgd_offset(vma->vm_mm, addr); + pmd_t *pmd; + pte_t *pte; + + if(pgd_none(*pgd)) + return 0; + + pmd = pmd_offset(pgd, addr); + if(pmd_none(*pmd) || pmd_bad(*pmd)) + re > urn 0; + + pte = pte_offset_map(pmd, addr); + + /* The PA flush mappings show up as pte_none, but they're + * valid none the less */ + if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0)) + return 0; + return 1; +} + + /* Private f > nction to flush a page from the cache of a non-current * process. cr25 contains the Page Directory of the current user * process; we're going to hijack both it and the user space %sr3 to @@ -141,17 +167,25 @@ } static inline void -flush > cache_page(struct vm_area_struct *vma, unsigned long vmaddr) +__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) { - BUG_ON(!vma->vm_mm->context); - - if (vma->vm_mm->context == mfsp(3)) { + if (likely(vma->vm_mm->context == mf > p(3))) { flush_user_dcache_page(vmaddr); if (vma->vm_flags & VM_EXEC) flush_user_icache_page(vmaddr); } else { flush_user_cache_page_non_current(vma, vmaddr); } +} + +static inline void +flush_cache_page(struct vm_area_struct > *vma, unsigned long vmaddr) +{ + BUG_ON(!vma->vm_mm->context); + + if(likely(translation_exists(vma, vmaddr))) + __flush_cache_page(vma, vmaddr); + } #endif _______________________________________________ parisc-linux mailing list pa > isc-linux@lists.parisc-linux.org http://lists.parisc-linux.org/mailman/listinfo/parisc-linux ---------------------------------------------------------------------------------------- Tiscali ADSL: 35 €/mois, la meilleure offre du marché! http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-04-08 6:15 ` Joel Soete @ 2004-04-08 12:36 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-08 12:36 UTC (permalink / raw) To: Joel Soete; +Cc: PARISC list On Thu, 2004-04-08 at 01:15, Joel Soete wrote: > Now as far as remember .h files are headers and so should only contains declaration > of function and not their definition excepted if they are very short (imho > 3 line max) but that is a personal limit: does it exist a common agreement > on this limit? > And here why changing translation_exists() definition location? Because it's an inline function. To move an inline function to a place shareable by other files it has to go into a header. James ^ permalink raw reply [flat|nested] 50+ messages in thread
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* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040406213446.CB675494194@palinux.hppa> @ 2004-04-06 21:37 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-06 21:37 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Tue, 2004-04-06 at 16:34, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/06 15:34:46 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c > > Log message: > Fix flush_dcache_page Index: arch/parisc/kernel/cache.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/cache.c,v retrieving revision 1.6 diff -u -r1.6 cache.c --- a/arch/parisc/kernel/cache.c 5 Apr 2004 02:47:39 -0000 1.6 +++ b/arch/parisc/kernel/cache.c 6 Apr 2004 21:30:44 -0000 @@ -227,6 +227,32 @@ disable_sr_hashing_asm(srhash_type); } +/* Simple function to work out if we have an existing address translation + * for a user space vma. */ +static inline int translation_exists(struct vm_area_struct *vma, + unsigned long addr) +{ + pgd_t *pgd = pgd_offset(vma->vm_mm, addr); + pmd_t *pmd; + pte_t *pte; + + if(pgd_none(*pgd)) + return 0; + + pmd = pmd_offset(pgd, addr); + if(pmd_none(*pmd) || pmd_bad(*pmd)) + return 0; + + pte = pte_offset_map(pmd, addr); + + /* The PA flush mappings show up as pte_none, but they're + * valid none the less */ + if(pte_none(*pte) && ((pte_val(*pte) & _PAGE_FLUSH) == 0)) + return 0; + return 1; +} + + void __flush_dcache_page(struct page *page) { struct mm_struct *mm = current->active_mm; @@ -237,19 +263,15 @@ if (!page->mapping) return; - /* check shared list first if it's not empty...it's usually - * the shortest */ + + /* We have ensured in arch_get_unmapped_area() that all shared + * mappings are mapped at equivalent addresses, so we only need + * to flush one for them all to become coherent */ list_for_each(l, &page->mapping->i_mmap_shared) { struct vm_area_struct *mpnt; - unsigned long off; + unsigned long off, addr; - anyvma = mpnt = list_entry(l, struct vm_area_struct, shared); - - /* - * If this VMA is not in our MM, we can ignore it. - */ - if (mpnt->vm_mm != mm) - continue; + mpnt = list_entry(l, struct vm_area_struct, shared); if (page->index < mpnt->vm_pgoff) continue; @@ -258,25 +280,51 @@ if (off >= (mpnt->vm_end - mpnt->vm_start) >> PAGE_SHIFT) continue; - flush_cache_page(mpnt, mpnt->vm_start + (off << PAGE_SHIFT)); + addr = mpnt->vm_start + (off << PAGE_SHIFT); + + /* flush instructions produce non access tlb misses. + * On PA, we nullify these instructions rather than + * taking a page fault if the pte doesn't exist, so we + * have to find a congruent address with an existing + * translation */ + + if (!translation_exists(mpnt, addr)) + continue; + + anyvma = mpnt; + + /* + * We try first to find a page in our current user process + */ + if (mpnt->vm_mm != mm) + continue; + + + flush_cache_page(mpnt, addr); /* All user shared mappings should be equivalently mapped, * so once we've flushed one we should be ok */ - return; + goto flush_unshared; } - /* then check private mapping list for read only shared mappings - * which are flagged by VM_MAYSHARE */ - list_for_each(l, &page->mapping->i_mmap) { - struct vm_area_struct *mpnt; - unsigned long off; + /* OK, shared page but not in our current process' address space */ + if (anyvma) { + unsigned long addr = anyvma->vm_start + + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); + flush_cache_page(anyvma, addr); + } - anyvma = mpnt = list_entry(l, struct vm_area_struct, shared); + flush_unshared: + /* Private mappings will not have congruent addresses, so we + * have to flush each of them individually to make the change + * in the kernel page visible */ + list_for_each(l, &page->mapping->i_mmap) { + struct vm_area_struct *mpnt; + unsigned long off, addr; - if (mpnt->vm_mm != mm || !(mpnt->vm_flags & VM_MAYSHARE)) - continue; + mpnt = list_entry(l, struct vm_area_struct, shared); if (page->index < mpnt->vm_pgoff) continue; @@ -285,20 +333,15 @@ if (off >= (mpnt->vm_end - mpnt->vm_start) >> PAGE_SHIFT) continue; - flush_cache_page(mpnt, mpnt->vm_start + (off << PAGE_SHIFT)); + addr = mpnt->vm_start + (off << PAGE_SHIFT); - /* All user shared mappings should be equivalently mapped, - * so once we've flushed one we should be ok - */ - return; - } - /* This is the problem case. We failed to find the page to be - * flushed in the current vma thus we have to flush it in some - * other user process */ - if (likely(anyvma)) { - unsigned long addr = anyvma->vm_start - + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); - flush_user_cache_page_non_current(anyvma, addr); + /* This is just for speed. If the page translation isn't + * there there's no point exciting the nadtlb handler into + * a nullification frenzy */ + if(!translation_exists(mpnt, addr)) + continue; + + flush_cache_page(mpnt, addr); } } EXPORT_SYMBOL(__flush_dcache_page); ^ permalink raw reply [flat|nested] 50+ messages in thread
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* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040405174131.84BF1494194@palinux.hppa> @ 2004-04-06 13:21 ` Carlos O'Donell 2004-04-06 14:18 ` James Bottomley 0 siblings, 1 reply; 50+ messages in thread From: Carlos O'Donell @ 2004-04-06 13:21 UTC (permalink / raw) To: parisc-linux; +Cc: James Bottomley On Mon, Apr 05, 2004 at 11:41:31AM -0600, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/05 11:41:31 > > Modified files: > . : Makefile > include/asm-parisc: cacheflush.h > > Log message: > Fix our gdb breakpoint problem > > Removing the full cache flush on non-current process access showed up a > but in copy_to_user_page(), which is now fixed. > > I also revoked the uselessly named > > flush_icache_user_range() What was the fix? Can you explain the change please? :) The glibc test-suite almost completed without issue on the newest kernel, though I saw a transient failure in one of the resolv tests, it wasn't a failure in the test, but rather the test ran longer than 2 seconds and was killed. The test uses mtrace() and I've not been able to duplicate the failure, the test should *not* have run over the milisecond mark. I wasn't running anything on the box at that point so it worries me quite a bit. With the box up and running I'm no longer able to trigger the slow behaviour that caused the timeout. Previous to this I had run the entire compile + testsuite from a clean boot, I'll see if doing that again triggers the failure. It might not be related to anything you've done, I don't think I've ever run a glibc build and testsuite from a cold boot... who knows what VM issues lurk? c. ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-04-06 13:21 ` Carlos O'Donell @ 2004-04-06 14:18 ` James Bottomley 2004-04-06 15:40 ` Randolph Chung 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-04-06 14:18 UTC (permalink / raw) To: Carlos O'Donell; +Cc: PARISC list On Tue, 2004-04-06 at 08:21, Carlos O'Donell wrote: > What was the fix? Can you explain the change please? :) copy_to_user_page() does the copy via a non-equivalently aliased kernel page. Unless that page is flushed at the kernel address, the writeback cache may not make the data visible (which is why gdb wasn't able to set breakpoints anymore). For some reason every arch implements copy_to_user_page as a memcpy followed by flush_icache_user_range(). The usually map flush_icache_user_range() to a kernel dcache page flush, which is contradictory. > The glibc test-suite almost completed without issue on the newest > kernel, though I saw a transient failure in one of the resolv tests, it > wasn't a failure in the test, but rather the test ran longer than 2 > seconds and was killed. The test uses mtrace() and I've not been able to > duplicate the failure, the test should *not* have run over the > milisecond mark. I wasn't running anything on the box at that point so > it worries me quite a bit. With the box up and running I'm no longer > able to trigger the slow behaviour that caused the timeout. Previous to > this I had run the entire compile + testsuite from a clean boot, I'll > see if doing that again triggers the failure. It might not be related to > anything you've done, I don't think I've ever run a glibc build and > testsuite from a cold boot... who knows what VM issues lurk? It's possible. As global flushes get removed any lurking holes in the rest of the API will emerge when they stop being covered by the global flush. James ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-04-06 14:18 ` James Bottomley @ 2004-04-06 15:40 ` Randolph Chung 0 siblings, 0 replies; 50+ messages in thread From: Randolph Chung @ 2004-04-06 15:40 UTC (permalink / raw) To: James Bottomley; +Cc: Carlos O'Donell, PARISC list > It's possible. As global flushes get removed any lurking holes in the > rest of the API will emerge when they stop being covered by the global > flush. i also saw a weird problem last night where i suddenly ran out of memory (1.5G physical + 500MB swap) and the OOM killer killed lots of apache processes. Earlier I was running a gdb testsuite and had to kill a bunch of stuck processes (there's some problems in gdb that i'm debugging...). There are a lot of "protection id trap" messages in my kernel log. not sure which bit was real and which bit was coincidence though :( i'll try this again with an older kernel and see what happens. randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
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* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040405024740.9330F494194@palinux.hppa> @ 2004-04-05 2:49 ` James Bottomley 2004-04-05 2:54 ` James Bottomley 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-04-05 2:49 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Sun, 2004-04-04 at 22:47, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/04 20:47:40 > > Modified files: > . : Makefile > arch/parisc/kernel: cache.c pacache.S > include/asm-parisc: cache.h cacheflush.h > > Log message: > Fix non current user process flushing. > > We have two problems: > > - There's a bug in __flush_dcache_page() that causes it to do nothing > if the current process doesn't contain the page. This is incorrect > since it will leave the congruent user pages incoherent with the > kernel page. > > - flush_cache_page() flushes everything if the mm of the > requested vma isn't current (this is correct, but cumbersome and is > what gives us the abysmally slow ptrace performance). > > We can fix both of these by introducing a new API: > > flush_user_cache_page_non_current() > > Specifically designed to flush a page in a non-current process. ===== arch/parisc/kernel/cache.c 1.7 vs edited ===== --- 1.7/arch/parisc/kernel/cache.c Wed Dec 17 23:48:38 2003 +++ edited/arch/parisc/kernel/cache.c Sat Apr 3 20:24:33 2004 @@ -71,9 +71,9 @@ if (VALID_PAGE(page) && page->mapping && test_bit(PG_dcache_dirty, &page->flags)) { - flush_kernel_dcache_page(page_address(page)); clear_bit(PG_dcache_dirty, &page->flags); } + flush_kernel_dcache_page(page_address(page)); } void @@ -293,6 +293,185 @@ } } EXPORT_SYMBOL(__flush_dcache_page); + +/* set to max pages to flush before a full flush. Zero means no limit */ +#define MAX_FLUSH_PAGES 0 +#undef DEBUG_PAGE_FLUSHING + +#ifdef DEBUG_PAGE_FLUSHING +#define DBG(a...) printk(a) +#else +#define DBG(...) +#endif + +#if (MAX_FLUSH_PAGES != 0) + +/* we get to use the bottom 12 bits of the addr for flags since the + * address must be page aligned */ +#define ICACHE_FLUSH_FLAG 0x1 + +void flush_cache_mm(struct mm_struct *mm) +{ + struct vm_area_struct *vma; + unsigned long count = 0, actual_count = 0; + unsigned long sr3 = mfsp(3), cr25 = mfctl(25); + unsigned long *pages; + + preempt_disable(); + if(mm != current->active_mm) { + DBG("flush_tlb_mm: current MM is not active "); + /* FIXME: awful hack: move the process the mm belongs + * to temporarily to being the active one. This only + * works because we can never get back into user + * context from here. */ + mtctl(__pa(mm->pgd), 25); + mtsp(mm->context, 3); + } + + pages = kmalloc(MAX_FLUSH_PAGES * sizeof(unsigned long), GFP_ATOMIC); + if(!pages) { + printk(KERN_ERR "flush_tlb_mm: allocation failed: full flush\n"); + goto full_flush; + } + + for (vma = mm->mmap; vma != NULL; vma = vma->vm_next) { + unsigned long start; + + pmd_t *pmd; + pgd_t *pgd; + pte_t *pte; + + count += (vma->vm_end - vma->vm_start)/PAGE_SIZE; + + for (start = vma->vm_start; start < vma->vm_end; + start += PAGE_SIZE) { + pgd = pgd_offset(mm, start); + + if (pgd_none(*pgd)) { + start = (start & PGDIR_MASK) + PGDIR_SIZE - PAGE_SIZE; + continue; + } + + pmd = pmd_offset(pgd, start); + if (pmd_none(*pmd)) { + start = (start & PMD_MASK) + PMD_SIZE - PAGE_SIZE; + continue; + } + pte = pte_offset_map(pmd, start); + if(pte_val(*pte)==0 || !pte_present(*pte)) + continue; + + /* FIXME: Here we could also skip over any + * shared mapping page (i.e. equivalently + * aliased) with at least one other user */ + + pages[actual_count] = start; + + if (vma->vm_flags && VM_EXEC) + pages[actual_count] |= ICACHE_FLUSH_FLAG; + if(++actual_count >= MAX_FLUSH_PAGES) + goto full_flush_free; + + } + } + + DBG("FLUSHED %lu (actual %lu)\n", count, actual_count); + for(count = 0; count < actual_count; count++) { + unsigned long addr = pages[count] & PAGE_MASK; + flush_user_dcache_page(addr); + if(pages[count] & ICACHE_FLUSH_FLAG) + flush_user_icache_page(addr); + } + out_free: + kfree(pages); + out: + mtsp(sr3, 3); + mtctl(cr25, 25); + preempt_enable(); + return; + + full_flush_free: + DBG("flush_cache_mm: over max pages %ld (count %ld), flushing everything\n", actual_count, count); + flush_cache_all(); + goto out_free; + + full_flush: + flush_cache_all(); + goto out; +} + +#else + +void flush_cache_mm(struct mm_struct *mm) +{ + struct vm_area_struct *vma; + unsigned long count = 0, actual_count = 0; + unsigned long sr3 = mfsp(3), cr25 = mfctl(25); + static int flushed = 0; + + if(unlikely(!flushed)) { + printk("flush_cache_mm: INIT FLUSH ALL\n"); + flushed = 1; + flush_cache_all(); + return; + } + + preempt_disable(); + if(mm != current->active_mm) { + DBG("flush_tlb_mm: current MM is not active "); + /* FIXME: awful hack: move the process the mm belongs + * to temporarily to being the active one. This only + * works because we can never get back into user + * context from here. */ + mtctl(__pa(mm->pgd), 25); + mtsp(mm->context, 3); + } + + for (vma = mm->mmap; vma != NULL; vma = vma->vm_next) { + unsigned long start; + + pmd_t *pmd; + pgd_t *pgd; + pte_t *pte; + + count += (vma->vm_end - vma->vm_start)/PAGE_SIZE; + + for (start = vma->vm_start; start < vma->vm_end; + start += PAGE_SIZE) { + pgd = pgd_offset(mm, start); + + if (pgd_none(*pgd)) { + start = (start & PGDIR_MASK) + PGDIR_SIZE - PAGE_SIZE; + continue; + } + + pmd = pmd_offset(pgd, start); + if (pmd_none(*pmd)) { + start = (start & PMD_MASK) + PMD_SIZE - PAGE_SIZE; + continue; + } + pte = pte_offset_map(pmd, start); + if(pte_val(*pte)==0 || !pte_present(*pte)) + continue; + + /* FIXME: Here we could also skip over any + * shared mapping page (i.e. equivalently + * aliased) with at least one other user */ + + flush_user_dcache_page(start); + if (vma->vm_flags && VM_EXEC) + flush_user_icache_page(start); + actual_count++; + } + } + mtsp(sr3, 3); + mtctl(cr25, 25); + preempt_enable(); + DBG("FLUSHED %lu (actual %lu)\n", count, actual_count); +} +#endif + +EXPORT_SYMBOL(flush_cache_mm); /* Defined in arch/parisc/kernel/pacache.S */ EXPORT_SYMBOL(flush_kernel_dcache_range_asm); ===== arch/parisc/kernel/pacache.S 1.4 vs edited ===== --- 1.4/arch/parisc/kernel/pacache.S Thu Mar 11 03:05:50 2004 +++ edited/arch/parisc/kernel/pacache.S Sat Apr 3 08:52:19 2004 @@ -574,6 +574,95 @@ .exit .procend + + .export flush_user_dcache_page + +flush_user_dcache_page: + .proc + .callinfo NO_CALLS + .entry + + ldil L%dcache_stride,%r1 + ldw R%dcache_stride(%r1),%r23 + +#ifdef __LP64__ + depdi,z 1,63-PAGE_SHIFT,1,%r25 +#else + depwi,z 1,31-PAGE_SHIFT,1,%r25 +#endif + add %r26,%r25,%r25 + sub %r25,%r23,%r25 + + +1: fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + CMPB<< %r26,%r25,1b + fdc,m %r23(%sr3,%r26) + + sync + bv %r0(%r2) + nop + .exit + + .procend + + .export flush_user_icache_page + +flush_user_icache_page: + .proc + .callinfo NO_CALLS + .entry + + ldil L%dcache_stride,%r1 + ldw R%dcache_stride(%r1),%r23 + +#ifdef __LP64__ + depdi,z 1,63-PAGE_SHIFT,1,%r25 +#else + depwi,z 1,31-PAGE_SHIFT,1,%r25 +#endif + add %r26,%r25,%r25 + sub %r25,%r23,%r25 + + +1: fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + CMPB<< %r26,%r25,1b + fic,m %r23(%sr3,%r26) + + sync + bv %r0(%r2) + nop + .exit + + .procend + .export purge_kernel_dcache_page ===== include/asm-parisc/cacheflush.h 1.6 vs edited ===== --- 1.6/include/asm-parisc/cacheflush.h Thu Oct 2 02:11:59 2003 +++ edited/include/asm-parisc/cacheflush.h Sat Apr 3 12:20:20 2004 @@ -12,7 +12,7 @@ #ifdef CONFIG_SMP #define flush_cache_mm(mm) flush_cache_all() #else -#define flush_cache_mm(mm) flush_cache_all_local() +extern void flush_cache_mm(struct mm_struct *); #endif #define flush_kernel_dcache_range(start,size) \ ===== include/asm-parisc/page.h 1.5 vs edited ===== --- 1.5/include/asm-parisc/page.h Sat Sep 27 16:43:45 2003 +++ edited/include/asm-parisc/page.h Sat Apr 3 19:47:09 2004 @@ -20,6 +20,8 @@ extern void purge_kernel_dcache_page(unsigned long); extern void copy_user_page_asm(void *to, void *from); extern void clear_user_page_asm(void *page, unsigned long vaddr); +extern void flush_user_dcache_page(unsigned long); +extern void flush_user_icache_page(unsigned long); static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, struct page *pg) ^ permalink raw reply [flat|nested] 50+ messages in thread
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-04-05 2:49 ` James Bottomley @ 2004-04-05 2:54 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-04-05 2:54 UTC (permalink / raw) To: James Bottomley; +Cc: parisc-linux-cvs, PARISC list And now with the correct patch attached. James ===== arch/parisc/kernel/cache.c 1.7 vs edited ===== --- 1.7/arch/parisc/kernel/cache.c Wed Dec 17 23:48:38 2003 +++ edited/arch/parisc/kernel/cache.c Sun Apr 4 20:10:40 2004 @@ -231,6 +231,7 @@ { struct mm_struct *mm = current->active_mm; struct list_head *l; + struct vm_area_struct *anyvma = NULL; flush_kernel_dcache_page(page_address(page)); @@ -242,7 +243,7 @@ struct vm_area_struct *mpnt; unsigned long off; - mpnt = list_entry(l, struct vm_area_struct, shared); + anyvma = mpnt = list_entry(l, struct vm_area_struct, shared); /* * If this VMA is not in our MM, we can ignore it. @@ -271,7 +272,7 @@ struct vm_area_struct *mpnt; unsigned long off; - mpnt = list_entry(l, struct vm_area_struct, shared); + anyvma = mpnt = list_entry(l, struct vm_area_struct, shared); if (mpnt->vm_mm != mm || !(mpnt->vm_flags & VM_MAYSHARE)) @@ -289,7 +290,15 @@ /* All user shared mappings should be equivalently mapped, * so once we've flushed one we should be ok */ - break; + return; + } + /* This is the problem case. We failed to find the page to be + * flushed in the current vma thus we have to flush it in some + * other user process */ + if (likely(anyvma)) { + unsigned long addr = anyvma->vm_start + + ((page->index - anyvma->vm_pgoff) << PAGE_SHIFT); + flush_user_cache_page_non_current(anyvma, addr); } } EXPORT_SYMBOL(__flush_dcache_page); ===== arch/parisc/kernel/pacache.S 1.4 vs edited ===== --- 1.4/arch/parisc/kernel/pacache.S Thu Mar 11 03:05:50 2004 +++ edited/arch/parisc/kernel/pacache.S Sun Apr 4 19:52:34 2004 @@ -574,6 +574,95 @@ .exit .procend + + .export flush_user_dcache_page + +flush_user_dcache_page: + .proc + .callinfo NO_CALLS + .entry + + ldil L%dcache_stride,%r1 + ldw R%dcache_stride(%r1),%r23 + +#ifdef __LP64__ + depdi,z 1,63-PAGE_SHIFT,1,%r25 +#else + depwi,z 1,31-PAGE_SHIFT,1,%r25 +#endif + add %r26,%r25,%r25 + sub %r25,%r23,%r25 + + +1: fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + fdc,m %r23(%sr3,%r26) + CMPB<< %r26,%r25,1b + fdc,m %r23(%sr3,%r26) + + sync + bv %r0(%r2) + nop + .exit + + .procend + + .export flush_user_icache_page + +flush_user_icache_page: + .proc + .callinfo NO_CALLS + .entry + + ldil L%dcache_stride,%r1 + ldw R%dcache_stride(%r1),%r23 + +#ifdef __LP64__ + depdi,z 1,63-PAGE_SHIFT,1,%r25 +#else + depwi,z 1,31-PAGE_SHIFT,1,%r25 +#endif + add %r26,%r25,%r25 + sub %r25,%r23,%r25 + + +1: fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + fic,m %r23(%sr3,%r26) + CMPB<< %r26,%r25,1b + fic,m %r23(%sr3,%r26) + + sync + bv %r0(%r2) + nop + .exit + + .procend + .export purge_kernel_dcache_page ===== include/asm-parisc/cache.h 1.5 vs edited ===== --- 1.5/include/asm-parisc/cache.h Tue Feb 3 23:43:00 2004 +++ edited/include/asm-parisc/cache.h Sun Apr 4 19:51:32 2004 @@ -52,6 +52,8 @@ extern void disable_sr_hashing_asm(int); /* low level support for above */ extern void free_sid(unsigned long); unsigned long alloc_sid(void); +extern void flush_user_dcache_page(unsigned long); +extern void flush_user_icache_page(unsigned long); struct seq_file; extern void show_cache_info(struct seq_file *m); ===== include/asm-parisc/cacheflush.h 1.6 vs edited ===== --- 1.6/include/asm-parisc/cacheflush.h Thu Oct 2 02:11:59 2003 +++ edited/include/asm-parisc/cacheflush.h Sun Apr 4 20:07:40 2004 @@ -111,26 +111,50 @@ } } +/* Private function to flush a page from the cache of a non-current + * process. cr25 contains the Page Directory of the current user + * process; we're going to hijack both it and the user space %sr3 to + * temporarily make the non-current process current. We have to do + * this because cache flushing may cause a non-access tlb miss which + * the handlers have to fill in from the pgd of the non-current + * process. */ +static inline void +flush_user_cache_page_non_current(struct vm_area_struct *vma, + unsigned long vmaddr) +{ + /* save the current process space and pgd */ + unsigned long space = mfsp(3), pgd = mfctl(25); + + /* we don't mind taking interrups since they may not + * do anything with user space, but we can't + * be preempted here */ + preempt_disable(); + + /* make us current */ + mtctl(__pa(vma->vm_mm->pgd), 25); + mtsp(vma->vm_mm->context, 3); + + flush_user_dcache_page(vmaddr); + if(vma->vm_flags & VM_EXEC) + flush_user_icache_page(vmaddr); + + /* put the old current process back */ + mtsp(space, 3); + mtctl(pgd, 25); + preempt_enable(); +} + static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) { - int sr3; + BUG_ON(!vma->vm_mm->context); - if (!vma->vm_mm->context) { - BUG(); - return; - } - - sr3 = mfsp(3); - if (vma->vm_mm->context == sr3) { - flush_user_dcache_range(vmaddr,vmaddr + PAGE_SIZE); + if (vma->vm_mm->context == mfsp(3)) { + flush_user_dcache_page(vmaddr); if (vma->vm_flags & VM_EXEC) - flush_user_icache_range(vmaddr,vmaddr + PAGE_SIZE); + flush_user_icache_page(vmaddr); } else { - if (vma->vm_flags & VM_EXEC) - flush_cache_all(); - else - flush_data_cache(); + flush_user_cache_page_non_current(vma, vmaddr); } } #endif ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040320210116.7A727494553@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040320210116.7A727494553@palinux.hppa> @ 2004-03-20 21:04 ` James Bottomley 2004-03-20 21:10 ` Helge Deller 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2004-03-20 21:04 UTC (permalink / raw) To: PARISC list, Helge Deller; +Cc: parisc-linux-cvs On Sat, 2004-03-20 at 16:01, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/03/20 14:01:16 > > Modified files: > drivers/input/keyboard: hpps2atkbd.h > > Log message: > Fix compile failure. > > This KEY_103RD is coming to us from the vanilla kernel, but it isn't > defined anywhere there Helge, is this fix OK? James ===== drivers/input/keyboard/hpps2atkbd.h 1.3 vs edited ===== --- 1.3/drivers/input/keyboard/hpps2atkbd.h Tue Mar 16 17:05:31 2004 +++ edited/drivers/input/keyboard/hpps2atkbd.h Tue Mar 16 19:23:14 2004 @@ -50,7 +50,7 @@ /* 60 */ KEY_DOWN, C_61, KEY_PAUSE, KEY_UP, KEY_DELETE, KEY_END, KEY_BACKSPACE, KEY_INSERT, /* 68 */ KEY_RESERVED, KEY_KP1, KEY_RIGHT, KEY_KP4, KEY_KP7, KEY_PAGEDOWN, KEY_HOME, KEY_PAGEUP, /* 70 */ KEY_KP0, KEY_KPDOT, KEY_KP2, KEY_KP5, KEY_KP6, KEY_KP8, KEY_ESC, KEY_NUMLOCK, -/* 78 */ KEY_F11, KEY_KPPLUS, KEY_KP3, KEY_KPMINUS, KEY_KPASTERISK,KEY_KP9, KEY_SCROLLLOCK,KEY_103RD, +/* 78 */ KEY_F11, KEY_KPPLUS, KEY_KP3, KEY_KPMINUS, KEY_KPASTERISK,KEY_KP9, KEY_SCROLLLOCK,KEY_102ND, /* 80 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, /* 88 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, /* 90 */ KEY_RESERVED, KEY_RIGHTALT, KEY_SYSRQ, KEY_RESERVED, KEY_RIGHTCTRL, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-03-20 21:04 ` James Bottomley @ 2004-03-20 21:10 ` Helge Deller 2004-03-20 21:13 ` Helge Deller 0 siblings, 1 reply; 50+ messages in thread From: Helge Deller @ 2004-03-20 21:10 UTC (permalink / raw) To: parisc-linux; +Cc: James Bottomley On Saturday 20 March 2004 22:04, James Bottomley wrote: > On Sat, 2004-03-20 at 16:01, James Bottomley wrote: > > CVSROOT: /var/cvs > > Module name: linux-2.6 > > Changes by: jejb 04/03/20 14:01:16 > > > > Modified files: > > drivers/input/keyboard: hpps2atkbd.h > > > > Log message: > > Fix compile failure. > > > > This KEY_103RD is coming to us from the vanilla kernel, but it isn't > > defined anywhere there > > Helge, is this fix OK? Hi James, keep the one from our CVS. I didn't sent the latest patches to Vojtech yet. Thanks, Helge ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-03-20 21:10 ` Helge Deller @ 2004-03-20 21:13 ` Helge Deller 0 siblings, 0 replies; 50+ messages in thread From: Helge Deller @ 2004-03-20 21:13 UTC (permalink / raw) To: parisc-linux; +Cc: James Bottomley On Saturday 20 March 2004 22:10, Helge Deller wrote: > On Saturday 20 March 2004 22:04, James Bottomley wrote: > > On Sat, 2004-03-20 at 16:01, James Bottomley wrote: > > > CVSROOT: /var/cvs > > > Module name: linux-2.6 > > > Changes by: jejb 04/03/20 14:01:16 > > > > > > Modified files: > > > drivers/input/keyboard: hpps2atkbd.h > > > > > > Log message: > > > Fix compile failure. > > > > > > This KEY_103RD is coming to us from the vanilla kernel, but it isn't > > > defined anywhere there > > > > Helge, is this fix OK? > > Hi James, > > keep the one from our CVS. Oops, sorry. Of course this is correct AFAICS. Helge ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb
@ 2004-02-06 7:31 Joel Soete
2004-02-06 17:50 ` Grant Grundler
2004-02-06 19:16 ` Randolph Chung
0 siblings, 2 replies; 50+ messages in thread
From: Joel Soete @ 2004-02-06 7:31 UTC (permalink / raw)
To: bame; +Cc: Randolph Chung, parisc-linux
Hi Paul,
>>
>> I am just curious to know the amount of memory on the Paul's b2k?
>>
>
>Mem: 505596k total
I only have 256Mb.
That was also a difference with c3k but here it is the only difference between
our b2k systems. Unfortunately I don't have any spare part to increase my
ram :(
Just in case Randolph has the opportunity to check the piminfo:
PROCESSOR PIM INFORMATION
----------------- Processor 0 HPMC Information ------------------
Timestamp =
Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26)
HPMC Chassis Codes = 2cbf0 2500b 2cbf5 2cbfc
General Registers 0 - 31
00-03 0000000000000000 000000001043e000 00000000000600d0 fffffff0f0000018
04-07 0000000000438000 0000000000439000 00000000fffffff0 00000000f0002f68
08-11 0000000000000027 00000000f0072848 000000000fff0000 000000001052c538
12-15 0000000000000000 00000000ffffffff 0000000000000000 00000000f0400004
16-19 00000000f00008c4 00000000f000017c 00000000f0000174 0000000000000000
20-23 0000000000000000 00000000fee003f8 00000000fee003fd 0000000000000000
24-27 0000000000000000 0000000000065e38 0000000000065e38 0000000000065e34
28-31 0000000000100000 0000000f4c7a3298 00000000004dc100 0000000000000060
Control Registers 0 - 31
00-03 0000000000000000 0000000000000000 0000000000000000 0000000000000000
04-07 0000000000000000 0000000000000000 0000000000000000 0000000000000000
08-11 0000000000000000 0000000000000000 0000000000000000 000000000000001f
12-15 0000000000000000 0000000000000000 0000000000000000 0000000000000000
16-19 0000000f4e0c5fee 0000000000000000 00000000001000e0 00000000702b0b30
20-23 0000000014340041 000000000f83e598 0000000000000008 0000000080000000
24-27 0000000000438000 0000000000438000 000000005fd50d56 000000007fdfdf2f
28-31 00000000ffbeffbe 00000000bfeb37dc 00000000104dc000 00000000104e0000
Space Registers 0 - 7
00-03 00000000 00000000 00000000 00000000
04-07 00000000 00000000 00000000 00000000
IIA Space = 0x0000000000000000
IIA Offset = 0x00000000001000e4
Check Type = 0x20000000
CPU State = 0x9e000004
Cache Check = 0x00000000
TLB Check = 0x00000000
Bus Check = 0x003010bb
Assists Check = 0x00000000
Assist State = 0x00000000
Path Info = 0x00031800
System Responder Address = 0xfffffffffed10200
System Requestor Address = 0xfffffffffffa0000
Floating-Point Registers 0 - 31
00-03 0000001f00000000 ffffffffffffffff ffffffffffffffff ffffffffffffffff
04-07 00003d09ffffffff 00000078ffffffff 00000000001c9c38 ddffffffffffffff
08-11 ffffffffffffffff bfffffffffffffff ffffffffffffffff ffffffffffffffff
12-15 ffffffffffffffff ffffffffffffffff ffffffffffffffff ffffbfefffffffef
16-19 ffffffffffffffff ffffffffffffffff ffffffffffffffff ffffffffffffffff
20-23 ffffffffffffffff fbfffffffffffdff ffffffffffffffff ffffff7fffffffff
24-27 ffffffffffffffff ffffffffffffffbf ffffffffffffffff ffffffffffffffff
28-31 ffffffffffffffff dfffffffffffffff ffffffffffffffff ffffffffffffffff
'9000/785 B,C,J Workstation Unarchitected (per-CPU)', rev 1, 140 bytes:
Check Summary = 0xcb81041000000000
Available Memory = 0x0000000010000000
CPU Diagnose Register 2 = 0x0301000000802204
CPU Status Register 0 = 0x2420c20000000000
CPU Status Register 1 = 0x8080000000000000
SADD LOG = 0xf813ec001043e598
Read Short LOG = 0xc18040fffee003fd
ERROR_STATUS = 0x0000000000000010
MEM_ADDR = 0x000001ff3fffffff
MEM_SYND = 0x0000000000000000
MEM_ADDR_CORR = 0x000001ff3fffffff
MEM_SYND_CORR = 0x0000000000000000
RUN_DATA_HIGH = 0xc1bff0fffed08040
RUN_DATA_LOW = 0xc1bff0fffed08040
RUN_CTRL = 0x0000021c00001418
RUN_ADDR = 0xc1bff0fffed08040
System Responder Path = 0x00ffffffffffffff
HPMC PIM Analysis Information:
Timestamp =
Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26)
'9000/785 B,C,J Workstation HPMC PIM Analysis (per-CPU)', rev 0, 1304 bytes:
A Data Miss Timeout occurred while CPU 0 was
requesting information.
Memory/IO Controller Error Analysis Information:
The Memory/IO Controller only observed the Broadcast Error. It did not log
any additional information about the HPMC.
----------------- Processor 0 LPMC Information ------------------
Check Type = 0x00000000
I/D Cache Parity Info = 0x00000000
Cache Check = 0x00000000
TLB Check = 0x00000000
Bus Check = 0x00000000
Assists Check = 0x00000000
Assist State = 0x00000000
Path Info = 0x00000000
System Responder Address = 0x0000000000000000
System Requestor Address = 0x0000000000000000
----------------- Processor 0 TOC Information -------------------
General Registers 0 - 31
00-03 0000000000000000 fffffff0f009d000 000000f0f000b618 00000000000f4240
04-07 0000000c6d9b6071 0000000000000004 0ffffff0f0408aa8 0000000000000002
08-11 00fffff000408ab0 00000000f0072848 000000000fff0000 00000000104f04d0
12-15 0000000000000000 00000000ffffffff 0000000000000000 00000000f0400004
16-19 00000000f00008c4 00000000f000017c 00000000f0000174 fffffff0f007ee38
20-23 fffffff0f05f0068 0000000000000004 0000000000000009 fffffff0f003d428
24-27 0000000013cf8409 000000003d090000 0000000017d78400 fffffff0f0412000
28-31 0000000017d78400 0000000000000008 fffffff0f0408d68 fffffff0f007eff8
Control Registers 0 - 31
00-03 0000000000000000 0000000000000000 0000000000000000 0000000000000000
04-07 0000000000000000 0000000000000000 0000000000000000 0000000000000000
08-11 0000000000000000 0000000000000000 0000960000009600 0000000000000005
12-15 0000000000000000 0000000000000000 000000f0f0003800 0000000000000000
16-19 0000000c816e9083 00000000000000f0 000000f0f000b628 00000000020008b8
20-23 000000009a37c3c1 c000000002008d10 000000ff08098f08 8000000000000000
24-27 000000000042c000 000000000042c000 00000000fffffff7 00000000fffffff7
28-31 00000000fffffff7 00000000fffffff7 0000000010495880 000000001049a000
Space Registers 0 - 7
00-03 00000000 00000000 00000000 00000000
04-07 00000000 00000000 00000000 00000000
IIA Space = 0x00000000000000f0
IIA Offset = 0x000000f0f000b620
CPU State = 0x9e000001
Memory Error Log Information:
Timestamp =
Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26)
'9000/785 B,C,J Workstation Memory Error Log', rev 0, 64 bytes:
No memory errors logged
I/O Module Error Log Information:
Timestamp =
Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26)
'9000/785 B,C,J Workstation IO Error Log', rev 0, 228 bytes:
Rope Word1 Word2 Word3
------ ------------ ------------
0 0x00000000 0x0e0cc009 0x00000000fed30048
1 0x00000000 0x1e0cc009 0x00000000fed32048
2 ---------- 0x2e0cc009 ------------------
3 ---------- 0x3e0cc009 ------------------
4 ---------- 0x4e0cc009 ------------------
5 ---------- 0x5e0cc009 ------------------
6 ---------- 0x6e0cc009 ------------------
7 ---------- 0x7e0cc009 ------------------
Thanks a lot for attention,
Joel
-------------------------------------------------------------------------
Tiscali ADSL: 12 mois à 29,50 €/mois! L'Internet rapide, c'est pour tout
le monde.
http://reg.tiscali.be/default.asp?lg=fr
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-06 7:31 [parisc-linux] " Joel Soete @ 2004-02-06 17:50 ` Grant Grundler 2004-02-06 18:06 ` bame 2004-02-06 19:16 ` Randolph Chung 1 sibling, 1 reply; 50+ messages in thread From: Grant Grundler @ 2004-02-06 17:50 UTC (permalink / raw) To: Joel Soete; +Cc: Randolph Chung, bame, parisc-linux On Fri, Feb 06, 2004 at 08:31:47AM +0100, Joel Soete wrote: > ----------------- Processor 0 HPMC Information ------------------ > > Timestamp = > Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26) > > HPMC Chassis Codes = 2cbf0 2500b 2cbf5 2cbfc > > General Registers 0 - 31 > 00-03 0000000000000000 000000001043e000 00000000000600d0 fffffff0f0000018 What does 00000000000600d0 point at? Is that the boot loader? > IIA Space = 0x0000000000000000 > IIA Offset = 0x00000000001000e4 Is the CPU still in real mode? ie haven't switched to virtual mode yet? > Check Type = 0x20000000 > CPU State = 0x9e000004 > Cache Check = 0x00000000 > TLB Check = 0x00000000 > Bus Check = 0x003010bb > Assists Check = 0x00000000 > Assist State = 0x00000000 > Path Info = 0x00031800 > System Responder Address = 0xfffffffffed10200 > System Requestor Address = 0xfffffffffffa0000 CPU is trying to get data from 0xfed10200 What lives there? > A Data Miss Timeout occurred while CPU 0 was > requesting information. Some device wasn't responding. > General Registers 0 - 31 > 00-03 0000000000000000 fffffff0f009d000 000000f0f000b618 00000000000f4240 looks like the box HPMC'd, and then TOC to recover. I think GR02 is a firmware address. ... > IIA Space = 0x00000000000000f0 > IIA Offset = 0x000000f0f000b620 > CPU State = 0x9e000001 > I/O Module Error Log Information: > > Timestamp = > Fri Feb 6 07:20:26 GMT 2004 (20:04:02:06:07:20:26) > > > '9000/785 B,C,J Workstation IO Error Log', rev 0, 228 bytes: > > Rope Word1 Word2 Word3 > ------ ------------ ------------ > 0 0x00000000 0x0e0cc009 0x00000000fed30048 > 1 0x00000000 0x1e0cc009 0x00000000fed32048 Note this is NOT the same address range that the CPU was trying to talk to. And it looks like all the ropes are happy. ("cc" is the status or error word, IIRC) If i had to guess, I would think Joel's box has a HW problem. But I really don't know what's going on. hth, grant ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-06 17:50 ` Grant Grundler @ 2004-02-06 18:06 ` bame 0 siblings, 0 replies; 50+ messages in thread From: bame @ 2004-02-06 18:06 UTC (permalink / raw) To: parisc-linux > > What does 00000000000600d0 point at? > Is that the boot loader? Yes, it's where the kernel would return to if it ever returned, so probably palo's made the call to the kernel at that point. ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-06 7:31 [parisc-linux] " Joel Soete 2004-02-06 17:50 ` Grant Grundler @ 2004-02-06 19:16 ` Randolph Chung 2004-02-06 17:08 ` Joel Soete 1 sibling, 1 reply; 50+ messages in thread From: Randolph Chung @ 2004-02-06 19:16 UTC (permalink / raw) To: Joel Soete; +Cc: parisc-linux > Just in case Randolph has the opportunity to check the piminfo: did you do clearpim before the run? The values in the pim info don't make a lot of sense.... did the box HPMC? did it hang and then you hit the TOC button? randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-06 19:16 ` Randolph Chung @ 2004-02-06 17:08 ` Joel Soete 2004-02-07 6:40 ` Randolph Chung 0 siblings, 1 reply; 50+ messages in thread From: Joel Soete @ 2004-02-06 17:08 UTC (permalink / raw) To: Randolph Chung; +Cc: parisc-linux Hi Randolph, > did you do clearpim before the run? Yes > The values in the pim info don't make a lot of sense.... Not more sense with previous one I got, that's why it takes me so much time to find a workaround ;) > did the box HPMC? Yes that's what showing the small lcd on the box and seems to be confirm by hpmc time stamp ;) > did it hang and then you hit the TOC button? NO. Just after the last advise of palo (... If this is the last message...) appears very quickly the message on the lcd: hpmc init... (even if I put printk() at the very begining of init code in main.c nothing is printed on the serial console. I also suspected a long time the compiler I used but recently I put this same kernel (scp) on the N4K-550 and it boot fine (but this system has 2Gb of ram) And because 2.4 64bits runing fine on this system (b2k) and the pb should be located very early at the begining of the kernel start, I had the idea to compare head64.S and vmlinux.lds.S and find back this 2.5 patch and try to revert it. But I very don't undurstand what happen in head64 to hope to help more efficiently :( (sorry) Thanks for your attention, Joel ------------------------------------------------------------------------- Tiscali ADSL: 12 mois à 29,50 €/mois! L'Internet rapide, c'est pour tout le monde. http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-06 17:08 ` Joel Soete @ 2004-02-07 6:40 ` Randolph Chung 2004-02-09 7:26 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: Randolph Chung @ 2004-02-07 6:40 UTC (permalink / raw) To: Joel Soete; +Cc: parisc-linux > And because 2.4 64bits runing fine on this system (b2k) and the pb should > be located very early at the begining of the kernel start, I had the idea > to compare head64.S and vmlinux.lds.S and find back this 2.5 patch and try > to revert it. But I very don't undurstand what happen in head64 to hope to > help more efficiently :( (sorry) Perhaps the problem is this.... in head64.S, we used to have: /* And the stack pointer too */ load32 PA(init_task_union+TASK_SZ_ALGN),%sp [...] /* Save the rfi target address */ std %r11, TASK_PT_GR11-TASK_SZ_ALGN(%sp) Since the pt_regs struct used to be part of the init_task_union, we do a store against the PA of init_task_union, and all is well. In the new code, init_task_union is a thread_info, and in order to store into the pt_regs we have to first dereference thread_info.task and then store into the resulting task pointer.... /* And the stack pointer too */ load32 PA(init_thread_union+THREAD_SZ_ALGN),%sp [...] /* Save the rfi target address */ ldo -THREAD_SZ_ALGN(%sp), %r1 ldd TI_TASK(%r1), %r1 std %r11, TASK_PT_GR11(%r1) so now we are storing into a VA of init_thread_union.task .... oops! So, can you try this patch? Index: arch/parisc/kernel/head64.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head64.S,v retrieving revision 1.3 diff -u -p -r1.3 head64.S --- arch/parisc/kernel/head64.S 17 Jan 2004 15:00:32 -0000 1.3 +++ arch/parisc/kernel/head64.S 7 Feb 2004 06:37:57 -0000 @@ -165,9 +165,9 @@ common_stext: #endif /* CONFIG_SMP */ /* Save the rfi target address */ - ldo -THREAD_SZ_ALGN(%sp), %r1 - ldd TI_TASK(%r1), %r1 - std %r11, TASK_PT_GR11(%r1) + ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10 + tophys_r1 %r10 + std %r11, TASK_PT_GR11(%r10) #ifndef CONFIG_PDC_NARROW /* Switch to wide mode; Superdome doesn't support narrow PDC @@ -197,9 +197,9 @@ common_stext: stext_pdc_ret: /* restore rfi target address*/ - ldo -THREAD_SZ_ALGN(%sp), %r1 - ldd TI_TASK(%r1), %r1 - ldd TASK_PT_GR11(%r1), %r11 + ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10 + tophys_r1 %r10 + ldd TASK_PT_GR11(%r10), %r11 /* PARANOID: clear user scratch/user space SR's */ mtsp %r0,%sr0 randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-07 6:40 ` Randolph Chung @ 2004-02-09 7:26 ` Joel Soete 0 siblings, 0 replies; 50+ messages in thread From: Joel Soete @ 2004-02-09 7:26 UTC (permalink / raw) To: Randolph Chung; +Cc: parisc-linux Hi Randolph, >So, can you try this patch? Yes, yes, yessss it works fine ;) Thanks agian for great help, Joel ------------------------------------------------------------------------- Tiscali ADSL: 12 mois à 29,50 €/mois! L'Internet rapide, c'est pour tout le monde. http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040204182455.1CC11494191@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040204182455.1CC11494191@palinux.hppa> @ 2004-02-05 9:20 ` Randolph Chung 2004-02-05 15:19 ` James Bottomley 2004-02-05 15:29 ` [parisc-linux] " Joel Soete 1 sibling, 1 reply; 50+ messages in thread From: Randolph Chung @ 2004-02-05 9:20 UTC (permalink / raw) To: parisc-linux > Modified files: > arch/parisc/kernel: vmlinux.lds.S > include/asm-parisc: uaccess.h > > Log message: > Make the exception table writeable (so it can actually be sorted) > and discard the interpreter section jejb, this doesn't work for me..... in arch/parisc/mm/init.c we mark everything from _stext to data_start as read-only, so i think we need something like this: Index: arch/parisc/kernel/vmlinux.lds.S =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/vmlinux.lds.S,v retrieving revision 1.6 diff -u -p -r1.6 vmlinux.lds.S --- arch/parisc/kernel/vmlinux.lds.S 4 Feb 2004 18:24:55 -0000 1.6 +++ arch/parisc/kernel/vmlinux.lds.S 5 Feb 2004 06:47:22 -0000 @@ -58,16 +58,17 @@ SECTIONS _etext = .; /* End of text section */ + RODATA + + /* writeable */ + data_start = .; + . = ALIGN(16); /* Exception table */ __start___ex_table = .; __ex_table : { *(__ex_table) } __stop___ex_table = .; - RODATA - - /* writeable */ .data : { /* Data */ - data_start = .; *(.data) CONSTRUCTORS } randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2004-02-05 9:20 ` [parisc-linux] " Randolph Chung @ 2004-02-05 15:19 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-02-05 15:19 UTC (permalink / raw) To: Randolph Chung; +Cc: PARISC list On Thu, 2004-02-05 at 04:20, Randolph Chung wrote: > > Modified files: > > arch/parisc/kernel: vmlinux.lds.S > > include/asm-parisc: uaccess.h > > > > Log message: > > Make the exception table writeable (so it can actually be sorted) > > and discard the interpreter section > > jejb, this doesn't work for me..... in arch/parisc/mm/init.c we mark > everything from _stext to data_start as read-only, so i think we need > something like this: OK, silly me for thinking we'd actually use the protection designation in the ELF headers... So with this patch it now all works? James ^ permalink raw reply [flat|nested] 50+ messages in thread
* [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040204182455.1CC11494191@palinux.hppa> 2004-02-05 9:20 ` [parisc-linux] " Randolph Chung @ 2004-02-05 15:29 ` Joel Soete 2004-02-05 20:31 ` Randolph Chung 1 sibling, 1 reply; 50+ messages in thread From: Joel Soete @ 2004-02-05 15:29 UTC (permalink / raw) To: parisc-linux, James Bottomley Hi James, >-- Original Message -- >To: parisc-linux-cvs@lists.parisc-linux.org >Date: Wed, 4 Feb 2004 11:24:55 -0700 (MST) >From: jejb@parisc-linux.org (James Bottomley) >Reply-To: parisc-linux@lists.parisc-linux.org >Subject: [parisc-linux-cvs] linux-2.6 jejb > > >CVSROOT: /var/cvs >Module name: linux-2.6 >Changes by: jejb 04/02/04 11:24:55 > >Modified files: > arch/parisc/kernel: vmlinux.lds.S > include/asm-parisc: uaccess.h > >Log message: >Make the exception table writeable (so it can actually be sorted) >and discard the interpreter section Unfortunately it doesn't help for the pb of 2.6.[12] running 64bits on b2k as decribe in a early mail (<http://lists.parisc-linux.org/pipermail/parisc-linux/2004-January/022238.html>) I always have to revert the mentioned patch to make it works?? I sure it is just a work around but I haven't enough knowledge (sorry) to fix it. I already test another patch which Randolph suggest me (<http://lists.parisc-linux.org/pipermail/parisc-linux/2004-February/022259.html>) but it doesn't work? Any idea? Thanks in advance for your attention, Joel ------------------------------------------------------------------------- Tiscali ADSL: 12 mois à 29,50 €/mois! L'Internet rapide, c'est pour tout le monde. http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-05 15:29 ` [parisc-linux] " Joel Soete @ 2004-02-05 20:31 ` Randolph Chung 2004-02-05 18:49 ` Joel Soete 0 siblings, 1 reply; 50+ messages in thread From: Randolph Chung @ 2004-02-05 20:31 UTC (permalink / raw) To: Joel Soete; +Cc: James Bottomley, parisc-linux Joel, can you try the kernel at http://www.tausq.org/joel/vmlinux ? It boots on my c3k and bame's b2k. If it works for you then pls check the config in the same directory and see if you can figure out which option is causing the crash..... btw, I assume you are building with gcc-3.0.4? randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] RE: [parisc-linux-cvs] linux-2.6 jejb 2004-02-05 20:31 ` Randolph Chung @ 2004-02-05 18:49 ` Joel Soete 0 siblings, 0 replies; 50+ messages in thread From: Joel Soete @ 2004-02-05 18:49 UTC (permalink / raw) To: Randolph Chung; +Cc: James Bottomley, parisc-linux Hi Randolph >Joel, can you try the kernel at http://www.tausq.org/joel/vmlinux ? It >boots on my c3k and bame's b2k. If it works for you then pls check the >config in the same directory and see if you can figure out which >option is causing the crash..... Thanks for your attention but it doesn't help: same behaviour (hpmc very early) :( > btw, I assume you are building with gcc-3.0.4? Doesn't matter which compiler I used gcc-3.0.4 or very last toolchain with last Carlos patch for gcc and glibc. I am just curious to know the amount of memory on the Paul's b2k? Thanks again for your attention and help, Joel ------------------------------------------------------------------------- Tiscali ADSL: 12 mois à 29,50 €/mois! L'Internet rapide, c'est pour tout le monde. http://reg.tiscali.be/default.asp?lg=fr ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20040113155603.CBCC249425A@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20040113155603.CBCC249425A@palinux.hppa> @ 2004-01-13 15:58 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2004-01-13 15:58 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Tue, 2004-01-13 at 10:56, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/01/13 08:56:03 > > Modified files: > . : Makefile > drivers/parisc : ccio-dma.c dino.c > include/asm-parisc: pci.h > > Log message: > Add Dino support for extended and non-contiguous PCI windows. > > The current code assumes the dino has a single 8MB window. However, > this isn't sufficient to support PCI video cards, which can have much > bigger windows. > > This code adds the ability to translate an arbitrary dino map (which must > still be correctly set up by firmware) into the PCI resource table. # This is a BitKeeper generated patch for the following project: # Project Name: Linux kernel tree # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: # ChangeSet 1.1531 -> 1.1532 # drivers/parisc/dino.c 1.13 -> 1.14 # drivers/parisc/ccio-dma.c 1.15 -> 1.16 # include/asm-parisc/pci.h 1.10 -> 1.11 # # The following is the BitKeeper ChangeSet Log # -------------------------------------------- # 04/01/13 jejb@raven.il.steeleye.com 1.1532 # Add support for extended and non-contiguous dino PCI windows # -------------------------------------------- # diff -Nru a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c --- a/drivers/parisc/ccio-dma.c Tue Jan 13 09:51:57 2004 +++ b/drivers/parisc/ccio-dma.c Tue Jan 13 09:51:57 2004 @@ -1627,11 +1627,11 @@ if (!ioc) { parent = &iomem_resource; - } else if ((ioc->mmio_region->start <= dev->hpa) && - (dev->hpa < ioc->mmio_region->end)) { + } else if ((ioc->mmio_region->start <= res->start) && + (res->end <= ioc->mmio_region->end)) { parent = ioc->mmio_region; - } else if (((ioc->mmio_region + 1)->start <= dev->hpa) && - (dev->hpa < (ioc->mmio_region + 1)->end)) { + } else if (((ioc->mmio_region + 1)->start <= res->start) && + (res->end <= (ioc->mmio_region + 1)->end)) { parent = ioc->mmio_region + 1; } else { return -EBUSY; diff -Nru a/drivers/parisc/dino.c b/drivers/parisc/dino.c --- a/drivers/parisc/dino.c Tue Jan 13 09:51:57 2004 +++ b/drivers/parisc/dino.c Tue Jan 13 09:51:57 2004 @@ -572,8 +572,16 @@ } else if(bus->parent == NULL) { /* must have a dino above it, reparent the resources * into the dino window */ + int i; + struct resource *res = &dino_dev->hba.lmmio_space; + bus->resource[0] = &(dino_dev->hba.io_space); - bus->resource[1] = &(dino_dev->hba.lmmio_space); + for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { + if(res[i].flags == 0) + break; + bus->resource[i+1] = &res[i]; + } + } else if(bus->self) { int i; @@ -740,9 +748,9 @@ static int __init dino_bridge_init(struct dino_device *dino_dev, const char *name) { - unsigned long io_addr, bpos; - int result; - struct resource *res; + unsigned long io_addr; + int result, i, count=0; + struct resource *res, *prevres = NULL; /* * Decoding IO_ADDR_EN only works for Built-in Dino * since PDC has already initialized this. @@ -754,21 +762,51 @@ return -ENODEV; } - for (bpos = 0; (io_addr & (1 << bpos)) == 0; bpos++) - ; - res = &dino_dev->hba.lmmio_space; - res->flags = IORESOURCE_MEM; + for (i = 0; i < 32; i++) { + unsigned long start, end; + + if((io_addr & (1 << i)) == 0) + continue; - res->start = (unsigned long)(signed int)(0xf0000000 | (bpos << 23)); - res->end = res->start + 8 * 1024 * 1024 - 1; + start = (unsigned long)(signed int)(0xf0000000 | (i << 23)); + end = start + 8 * 1024 * 1024 - 1; - result = ccio_request_resource(dino_dev->hba.dev, res); - if (result < 0) { - printk(KERN_ERR "%s: failed to claim PCI Bus address space!\n", name); - return result; + DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, + start, end); + + if(prevres && prevres->end + 1 == start) { + prevres->end = end; + } else { + if(count >= DINO_MAX_LMMIO_RESOURCES) { + printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); + break; + } + prevres = res; + res->start = start; + res->end = end; + res->flags = IORESOURCE_MEM; + res->name = kmalloc(64, GFP_KERNEL); + if(res->name) + snprintf((char *)res->name, 64, "%s LMMIO %d", + name, count); + res++; + count++; + } } + res = &dino_dev->hba.lmmio_space; + + for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { + if(res[i].flags == 0) + break; + + result = ccio_request_resource(dino_dev->hba.dev, &res[i]); + if (result < 0) { + printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end); + return result; + } + } return 0; } @@ -849,10 +887,8 @@ res = &dino_dev->hba.io_space; if (dev->id.hversion == 0x680 || is_card_dino(&dev->id)) { res->name = "Dino I/O Port"; - dino_dev->hba.lmmio_space.name = "Dino LMMIO"; } else { res->name = "Cujo I/O Port"; - dino_dev->hba.lmmio_space.name = "Cujo LMMIO"; } res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); diff -Nru a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h --- a/include/asm-parisc/pci.h Tue Jan 13 09:51:57 2004 +++ b/include/asm-parisc/pci.h Tue Jan 13 09:51:57 2004 @@ -56,6 +56,11 @@ struct resource lmmio_space; /* bus addresses < 4Gb */ struct resource elmmio_space; /* additional bus addresses < 4Gb */ struct resource gmmio_space; /* bus addresses > 4Gb */ + /* NOTE: Dino code assumes it can use *all* of the lmmio_space, + * elmmio_space and gmmio_space as a contiguous array of + * resources. This #define represents the array size */ + #define DINO_MAX_LMMIO_RESOURCES 3 + unsigned long lmmio_space_offset; /* CPU view - PCI view */ void * iommu; /* IOMMU this device is under */ /* REVISIT - spinlock to protect resources? */ ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20030924175431.D51BC49408B@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20030924175431.D51BC49408B@palinux.hppa> @ 2003-09-24 18:01 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2003-09-24 18:01 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Wed, 2003-09-24 at 12:54, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 03/09/24 11:54:31 > > Modified files: > . : Makefile > arch/parisc/kernel: signal.c > include/asm-parisc: rt_sigframe.h > > Log message: > Make signals work with ELF64 binaries > > For those who want to try this at home, there's a mini test suite at > http://www.parisc-linux.org/~jejb/64bit.tar.gz > > NOTE: The signal handler has become really ugly. However, since it's > completely broken for context returns with ELF32 binaries on ELF64 kernels > there didn't seem to be a lot of point making it nicer until we tackle that > problem as well Index: arch/parisc/kernel/signal.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/signal.c,v retrieving revision 1.10 diff -u -r1.10 signal.c --- arch/parisc/kernel/signal.c 19 Sep 2003 01:03:56 -0000 1.10 +++ arch/parisc/kernel/signal.c 24 Sep 2003 17:50:48 -0000 @@ -26,6 +26,7 @@ #include <linux/stddef.h> #include <linux/compat.h> #include <linux/elf.h> +#include <linux/personality.h> #include <asm/ucontext.h> #include <asm/rt_sigframe.h> #include <asm/uaccess.h> @@ -170,11 +171,17 @@ struct rt_sigframe *frame; struct siginfo si; sigset_t set; - unsigned long usp = regs->gr[30]; + unsigned long usp = (regs->gr[30] & ~(0x01UL)); + unsigned long sigframe_size = PARISC_RT_SIGFRAME_SIZE; +#ifdef __LP64__ + if(personality(current->personality) == PER_LINUX32) + sigframe_size = PARISC_RT_SIGFRAME_SIZE32; +#endif + /* Unwind the user stack to get the rt_sigframe structure. */ frame = (struct rt_sigframe *) - (usp - PARISC_RT_SIGFRAME_SIZE); + (usp - sigframe_size); DBG(("in sys_rt_sigreturn, frame is %p\n", frame)); if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) @@ -276,11 +283,11 @@ { struct rt_sigframe *frame; unsigned long rp, usp; - Elf32_Addr haddr; + unsigned long haddr, sigframe_size; struct siginfo si; int err = 0; - usp = regs->gr[30]; + usp = (regs->gr[30] & ~(0x01UL)); frame = get_sigframe(ka, usp, sizeof(*frame)); DBG(("setup_rt_frame 1: frame %p info %p\n", frame, info)); @@ -325,25 +332,59 @@ haddr = A(ka->sa.sa_handler); /* The sa_handler may be a pointer to a function descriptor */ - if (haddr & PA_PLABEL_FDESC) { - Elf32_Fdesc fdesc; - Elf32_Fdesc *ufdesc = (Elf32_Fdesc *)A(haddr & ~3); +#ifdef __LP64__ + if(personality(current->personality) == PER_LINUX32) { +#endif + if (haddr & PA_PLABEL_FDESC) { + Elf32_Fdesc fdesc; + Elf32_Fdesc *ufdesc = (Elf32_Fdesc *)A(haddr & ~3); - err = __copy_from_user(&fdesc, ufdesc, sizeof(fdesc)); + err = __copy_from_user(&fdesc, ufdesc, sizeof(fdesc)); + + if (err) + goto give_sigsegv; + haddr = fdesc.addr; + regs->gr[19] = fdesc.gp; + } +#ifdef __LP64__ + } else { + Elf64_Fdesc fdesc; + Elf64_Fdesc *ufdesc = (Elf64_Fdesc *)A(haddr & ~3); + + err = __copy_from_user(&fdesc, ufdesc, sizeof(fdesc)); + if (err) goto give_sigsegv; - + haddr = fdesc.addr; regs->gr[19] = fdesc.gp; + DBG(("64 bit signal, exe=%#lx, r19=%#lx, in_syscall=%d\n", + haddr, regs->gr[19], in_syscall)); } +#endif /* The syscall return path will create IAOQ values from r31. */ - if (in_syscall) + sigframe_size = PARISC_RT_SIGFRAME_SIZE; +#ifdef __LP64__ + if(personality(current->personality) == PER_LINUX32) + sigframe_size = PARISC_RT_SIGFRAME_SIZE32; +#endif + if (in_syscall) { regs->gr[31] = haddr; - else { - regs->gr[0] = USER_PSW; +#ifdef __LP64__ + if(personality(current->personality) == PER_LINUX) + sigframe_size |= 1; +#endif + } else { + unsigned long psw = USER_PSW; +#ifdef __LP64__ + if(personality(current->personality) == PER_LINUX) + psw |= PSW_W; +#endif + + regs->gr[0] = psw; regs->iaoq[0] = haddr | 3; regs->iaoq[1] = regs->iaoq[0] + 4; } @@ -352,11 +393,13 @@ regs->gr[26] = sig; /* signal number */ regs->gr[25] = A(&frame->info); /* siginfo pointer */ regs->gr[24] = A(&frame->uc); /* ucontext pointer */ + DBG(("making sigreturn frame: %#lx + %#x = %#lx\n", - regs->gr[30], PARISC_RT_SIGFRAME_SIZE, - regs->gr[30] + PARISC_RT_SIGFRAME_SIZE)); + regs->gr[30], sigframe_size, + regs->gr[30] + sigframe_size)); /* Raise the user stack pointer to make a proper call frame. */ - regs->gr[30] = (A(frame) + PARISC_RT_SIGFRAME_SIZE); + regs->gr[30] = (A(frame) + sigframe_size); + DBG(("SIG deliver (%s:%d): frame=0x%p sp=%#lx iaoq=%#lx/%#lx rp=%#lx\n", current->comm, current->pid, frame, regs->gr[30], Index: include/asm-parisc/rt_sigframe.h =================================================================== RCS file: /var/cvs/linux-2.6/include/asm-parisc/rt_sigframe.h,v retrieving revision 1.1 diff -u -r1.1 rt_sigframe.h --- include/asm-parisc/rt_sigframe.h 29 Jul 2003 17:02:04 -0000 1.1 +++ include/asm-parisc/rt_sigframe.h 24 Sep 2003 17:51:16 -0000 @@ -13,7 +13,20 @@ * which Linux/parisc uses is sp-20 for the saved return pointer...) * Then, the stack pointer must be rounded to a cache line (64 bytes). */ +#define SIGFRAME32 64 +#define FUNCTIONCALLFRAME32 48 +#define PARISC_RT_SIGFRAME_SIZE32 \ + (((sizeof(struct rt_sigframe) + FUNCTIONCALLFRAME32) + SIGFRAME32) & -SIGFRAME32) + +#ifdef __LP64__ +#define SIGFRAME 128 +#define FUNCTIONCALLFRAME 96 #define PARISC_RT_SIGFRAME_SIZE \ - (((sizeof(struct rt_sigframe) + 48) + 63) & -64) + (((sizeof(struct rt_sigframe) + FUNCTIONCALLFRAME) + SIGFRAME) & -SIGFRAME) +#else +#define SIGFRAME SIGFRAME32 +#define FUNCTIONCALLFRAME FUNCTIONCALLFRAME32 +#define PARISC_RT_SIGFRAME_SIZE PARISC_RT_SIGFRAME_SIZE32 +#endif #endif ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20030919010356.148684940A4@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20030919010356.148684940A4@palinux.hppa> @ 2003-09-19 1:06 ` James Bottomley 2003-09-19 11:24 ` Randolph Chung 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2003-09-19 1:06 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Thu, 2003-09-18 at 20:03, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 03/09/18 19:03:56 > > Modified files: > . : Makefile > arch/parisc/kernel: module.c signal.c > include/asm-parisc: elf.h > > Log message: > Clean up signal handling code: > > - remove the less than helpful comments (and replace them with > meaningful ones > - get rid of the HACK macros > - Unify the PLABEL function descriptor handling with modules.c ===== arch/parisc/kernel/module.c 1.8 vs edited ===== --- 1.8/arch/parisc/kernel/module.c Wed Sep 10 00:44:18 2003 +++ edited/arch/parisc/kernel/module.c Thu Sep 18 16:01:11 2003 @@ -73,10 +73,7 @@ Elf32_Addr addr; }; -struct fdesc_entry { - Elf32_Addr addr; - Elf32_Addr gp; -}; +#define Elf_Fdesc Elf32_Fdesc struct stub_entry { Elf32_Word insns[2]; /* each stub entry has two insns */ @@ -86,11 +83,7 @@ Elf64_Addr addr; }; -struct fdesc_entry { - Elf64_Addr dummy[2]; - Elf64_Addr addr; - Elf64_Addr gp; -}; +#define Elf_Fdesc Elf64_Fdesc struct stub_entry { Elf64_Word insns[4]; /* each stub entry has four insns */ @@ -276,7 +269,7 @@ me->core_size = ALIGN(me->core_size, 16); me->arch.fdesc_offset = me->core_size; - me->core_size += fdescs * sizeof(struct fdesc_entry); + me->core_size += fdescs * sizeof(Elf_Fdesc); me->core_size = ALIGN(me->core_size, 16); me->arch.stub_offset = me->core_size; @@ -322,7 +315,7 @@ #ifdef __LP64__ static Elf_Addr get_fdesc(struct module *me, unsigned long value) { - struct fdesc_entry *fdesc = me->module_core + me->arch.fdesc_offset; + Elf_Fdesc *fdesc = me->module_core + me->arch.fdesc_offset; if (!value) { printk(KERN_ERR "%s: zero OPD requested!\n", me->name); @@ -664,7 +657,7 @@ *loc64 = get_fdesc(me, val+addend); DEBUGP("FDESC for %s at %p points to %lx\n", strtab + sym->st_name, *loc64, - ((struct fdesc_entry *)*loc64)->addr); + ((Elf_Fdesc *)*loc64)->addr); } else { /* if the symbol is not local to this * module then val+addend is a pointer @@ -696,10 +689,10 @@ Elf_Sym *newptr, *oldptr; Elf_Shdr *symhdr = NULL; #ifdef DEBUG - struct fdesc_entry *entry; + Elf_Fdesc *entry; u32 *addr; - entry = (struct fdesc_entry *)me->init; + entry = (Elf_Fdesc *)me->init; printk("FINALIZE, ->init FPTR is %p, GP %lx ADDR %lx\n", entry, entry->gp, entry->addr); addr = (u32 *)entry->addr; ===== arch/parisc/kernel/signal.c 1.13 vs edited ===== --- 1.13/arch/parisc/kernel/signal.c Wed Sep 10 00:44:19 2003 +++ edited/arch/parisc/kernel/signal.c Thu Sep 18 17:49:36 2003 @@ -25,6 +25,7 @@ #include <linux/unistd.h> #include <linux/stddef.h> #include <linux/compat.h> +#include <linux/elf.h> #include <asm/ucontext.h> #include <asm/rt_sigframe.h> #include <asm/uaccess.h> @@ -41,8 +42,11 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -/* Use this to get at 32-bit user passed pointers. - * See sys_sparc32.c for description about these. */ +/* gcc will complain if a pointer is cast to an integer of different + * size. If you really need to do this (and we do for an ELF32 user + * application in an ELF64 kernel) then you have to do a cast to an + * integer of the same size first. The A() macro accomplishes + * this. */ #define A(__x) ((unsigned long)(__x)) int do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall); @@ -271,7 +275,8 @@ sigset_t *set, struct pt_regs *regs, int in_syscall) { struct rt_sigframe *frame; - unsigned long rp, usp, haddr; + unsigned long rp, usp; + Elf32_Addr haddr; struct siginfo si; int err = 0; @@ -308,64 +313,50 @@ } #endif -#undef CACHE_FLUSHING_IS_NOT_BROKEN -#ifdef CACHE_FLUSHING_IS_NOT_BROKEN + flush_user_dcache_range((unsigned long) &frame->tramp[0], + (unsigned long) &frame->tramp[4]); flush_user_icache_range((unsigned long) &frame->tramp[0], (unsigned long) &frame->tramp[4]); -#else - /* It should *always* be cache line-aligned, but the compiler - sometimes screws up. */ - asm volatile("fdc 0(%%sr3,%0)\n\t" - "fdc %1(%%sr3,%0)\n\t" - "sync\n\t" - "fic 0(%%sr3,%0)\n\t" - "fic %1(%%sr3,%0)\n\t" - "sync\n\t" - : : "r" (frame->tramp), "r" (L1_CACHE_BYTES)); -#endif rp = (unsigned long) frame->tramp; if (err) goto give_sigsegv; -/* Much more has to happen with signals than this -- but it'll at least */ -/* provide a pointer to some places which definitely need a look. */ -#define HACK u32 - - haddr = (HACK)A(ka->sa.sa_handler); - /* ARGH! Fucking brain damage. You don't want to know. */ - if (haddr & 2) { - HACK *plabel; - HACK ltp; - - plabel = (HACK *) (haddr & ~3); - err |= __get_user(haddr, plabel); - err |= __get_user(ltp, plabel + 1); + haddr = A(ka->sa.sa_handler); + /* The sa_handler may be a pointer to a function descriptor */ + if (haddr & PA_PLABEL_FDESC) { + Elf32_Fdesc fdesc; + Elf32_Fdesc *ufdesc = (Elf32_Fdesc *)A(haddr & ~3); + + err = __copy_from_user(&fdesc, ufdesc, sizeof(fdesc)); + if (err) goto give_sigsegv; - regs->gr[19] = ltp; + + haddr = fdesc.addr; + regs->gr[19] = fdesc.gp; } /* The syscall return path will create IAOQ values from r31. */ if (in_syscall) - regs->gr[31] = (HACK) haddr; + regs->gr[31] = haddr; else { regs->gr[0] = USER_PSW; - regs->iaoq[0] = (HACK) haddr | 3; + regs->iaoq[0] = haddr | 3; regs->iaoq[1] = regs->iaoq[0] + 4; } regs->gr[2] = rp; /* userland return pointer */ regs->gr[26] = sig; /* signal number */ - regs->gr[25] = (HACK)A(&frame->info); /* siginfo pointer */ - regs->gr[24] = (HACK)A(&frame->uc); /* ucontext pointer */ + regs->gr[25] = A(&frame->info); /* siginfo pointer */ + regs->gr[24] = A(&frame->uc); /* ucontext pointer */ DBG(("making sigreturn frame: %#lx + %#x = %#lx\n", regs->gr[30], PARISC_RT_SIGFRAME_SIZE, regs->gr[30] + PARISC_RT_SIGFRAME_SIZE)); /* Raise the user stack pointer to make a proper call frame. */ - regs->gr[30] = ((HACK)A(frame) + PARISC_RT_SIGFRAME_SIZE); + regs->gr[30] = (A(frame) + PARISC_RT_SIGFRAME_SIZE); DBG(("SIG deliver (%s:%d): frame=0x%p sp=%#lx iaoq=%#lx/%#lx rp=%#lx\n", current->comm, current->pid, frame, regs->gr[30], ===== include/asm-parisc/elf.h 1.8 vs edited ===== --- 1.8/include/asm-parisc/elf.h Wed Sep 10 00:44:23 2003 +++ edited/include/asm-parisc/elf.h Thu Sep 18 16:07:25 2003 @@ -144,6 +144,30 @@ #define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ #define R_PARISC_HIRESERVE 255 +#define PA_PLABEL_FDESC 0x02 /* bit set if PLABEL points to + * a function descriptor, not + * an address */ + +/* The following are PA function descriptors + * + * addr: the absolute address of the function + * gp: either the data pointer (r27) for non-PIC code or the + * the PLT pointer (r19) for PIC code */ + +/* Format for the Elf32 Function descriptor */ +typedef struct elf32_fdesc { + __u32 addr; + __u32 gp; +} Elf32_Fdesc; + +/* Format for the Elf64 Function descriptor */ +typedef struct elf64_fdesc { + __u64 dummy[2]; /* FIXME: nothing uses these, why waste + * the space */ + __u64 addr; + __u64 gp; +} Elf64_Fdesc; + /* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ #define PT_HP_TLS (PT_LOOS + 0x0) ^ permalink raw reply [flat|nested] 50+ messages in thread
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2003-09-19 1:06 ` James Bottomley @ 2003-09-19 11:24 ` Randolph Chung 2003-09-19 14:02 ` James Bottomley 0 siblings, 1 reply; 50+ messages in thread From: Randolph Chung @ 2003-09-19 11:24 UTC (permalink / raw) To: James Bottomley; +Cc: PARISC list, parisc-linux-cvs > -#undef CACHE_FLUSHING_IS_NOT_BROKEN > -#ifdef CACHE_FLUSHING_IS_NOT_BROKEN > + flush_user_dcache_range((unsigned long) &frame->tramp[0], > + (unsigned long) &frame->tramp[4]); > flush_user_icache_range((unsigned long) &frame->tramp[0], > (unsigned long) &frame->tramp[4]); we also have a flush_icache_user_range range macro that does this (flush dcache + icache). The kernel seems to use both..... randolph -- Randolph Chung Debian GNU/Linux Developer, hppa/ia64 ports http://www.tausq.org/ ^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2003-09-19 11:24 ` Randolph Chung @ 2003-09-19 14:02 ` James Bottomley 2003-09-19 18:24 ` Jim Hull 0 siblings, 1 reply; 50+ messages in thread From: James Bottomley @ 2003-09-19 14:02 UTC (permalink / raw) To: Randolph Chung; +Cc: PARISC list On Fri, 2003-09-19 at 06:24, Randolph Chung wrote: > we also have a flush_icache_user_range range macro that does this (flush > dcache + icache). The kernel seems to use both..... Well, I just took the least line of resistance. But it does beg the question: I think all of the PA arch docs require the dcache to be flushed before the icache for all icache flushing, so is there any point exporting an API that only flushes the icache? James ^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb 2003-09-19 14:02 ` James Bottomley @ 2003-09-19 18:24 ` Jim Hull 0 siblings, 0 replies; 50+ messages in thread From: Jim Hull @ 2003-09-19 18:24 UTC (permalink / raw) To: 'James Bottomley', 'Randolph Chung'; +Cc: 'PARISC list' James Bottomley wrote: > But it does beg the question: I think all of the PA arch docs require > the dcache to be flushed before the icache for all icache flushing, so > is there any point exporting an API that only flushes the icache? Not true. If you know that the line can't be in the d-cache, then flushing the i-cache is sufficient (and vice-versa). See "Data Cache Move-In", "Instruction Cache Move-In", and "Cache Flushing" in Appendix F of "PA-RISC 2.0 Architecture" (aka, "The Kane Book"), for details. Now, whether pa-linux keeps track of whether a line could be in only the d- or i-cache, with sufficient accuracy to avoid the other flush, I have no idea. HP-UX does attempt to track this, but doing so in every case can be really tricky, and tracking down the data (or instruction) corruption bugs when you miss some obscure case is a nightmare (and I have the scars to prove it :). -- Jim HP PA-RISC/Itanium Processor Architect ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20030903200300.8B7B7494064@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20030903200300.8B7B7494064@palinux.hppa> @ 2003-09-03 20:07 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2003-09-03 20:07 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Wed, 2003-09-03 at 16:03, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 03/09/03 14:03:00 > > Modified files: > . : Makefile > drivers/parisc : ccio-dma.c dino.c > > Log message: > Add card mode dino support for machines with a CCIO. > > This is rather simplistic: basically it simply tries to expand the > existing ccio window by the dino card mode size (currently 8MB). This could > easily fail if there's no room on either side. > > Unfortunately, the correct fix (to reprogram the ccio to take into account > card mode dinos before beginning bus scanning) is rather complex. > > Also fixed the allocation failure case to delete the devices on the bus > so drivers don't try attaching to them. Index: ccio-dma.c =================================================================== RCS file: /var/cvs/linux-2.6/drivers/parisc/ccio-dma.c,v retrieving revision 1.3 diff -u -p -r1.3 ccio-dma.c --- ccio-dma.c 2 Sep 2003 18:42:42 -0000 1.3 +++ ccio-dma.c 3 Sep 2003 19:59:34 -0000 @@ -1534,13 +1534,74 @@ static void __init ccio_init_resources(s (unsigned long)&ioc->ioc_hpa->io_io_low_hv); } -static void expand_ioc_area(struct ioc *ioc, unsigned long size, - unsigned long min, unsigned long max, unsigned long align) +static int expand_resource(struct resource *res, unsigned long size, + unsigned long align) { -#ifdef NASTY_HACK_FOR_K_CLASS - __raw_writel(0xfffff600, (unsigned long)&(ioc->ioc_hpa->io_io_high)); - ioc->mmio_region[0].end = 0xf5ffffff; -#endif + struct resource *temp_res; + unsigned long start = res->start; + unsigned long end ; + + /* see if we can expand above */ + end = (res->end + size + align - 1) & ~(align - 1);; + + temp_res = __request_region(res->parent, res->end, end - res->end, + "expansion"); + if(!temp_res) { + /* now try below */ + start = ((res->start - size + align) & ~(align - 1)) - align; + end = res->end; + temp_res = __request_region(res->parent, start, size, + "expansion"); + if(!temp_res) { + return -ENOMEM; + } + } + release_resource(temp_res); + temp_res = res->parent; + release_resource(res); + res->start = start; + res->end = end; + + /* This could be caused by some sort of race. Basically, if + * this tripped something stole the region we just reserved + * and then released to check for expansion */ + BUG_ON(request_resource(temp_res, res) != 0); + + return 0; +} + +static void expand_ioc_area(struct resource *parent, struct ioc *ioc, + unsigned long size, unsigned long min, + unsigned long max, unsigned long align) +{ + if(ioc == NULL) + /* no IOC, so nothing to expand */ + return; + + if (expand_resource(parent, size, align) != 0) { + printk(KERN_ERR "Unable to expand %s window by 0x%lx\n", + parent->name, size); + return; + } + + /* OK, we have the memory, now expand the window */ + if (parent == &ioc->mmio_region[0]) { + __raw_writel(((parent->start)>>16) | 0xffff0000, + (unsigned long)&(ioc->ioc_hpa->io_io_low)); + __raw_writel(((parent->end)>>16) | 0xffff0000, + (unsigned long)&(ioc->ioc_hpa->io_io_high)); + } else if (parent == &ioc->mmio_region[1]) { + __raw_writel(((parent->start)>>16) | 0xffff0000, + (unsigned long)&(ioc->ioc_hpa->io_io_low_hv)); + __raw_writel(((parent->end)>>16) | 0xffff0000, + (unsigned long)&(ioc->ioc_hpa->io_io_high_hv)); + } else { + /* This should be impossible. It means + * expand_ioc_area got called with a resource that + * didn't belong to the ioc + */ + BUG(); + } } static struct resource *ccio_get_resource(struct ioc* ioc, @@ -1574,7 +1635,7 @@ int ccio_allocate_resource(const struct alignf_data)) return 0; - expand_ioc_area(ioc, size, min, max, align); + expand_ioc_area(parent, ioc, size, min, max, align); return allocate_resource(parent, res, size, min, max, align, alignf, alignf_data); } Index: dino.c =================================================================== RCS file: /var/cvs/linux-2.6/drivers/parisc/dino.c,v retrieving revision 1.3 diff -u -p -r1.3 dino.c --- dino.c 3 Sep 2003 16:51:12 -0000 1.3 +++ dino.c 3 Sep 2003 19:59:36 -0000 @@ -480,7 +480,18 @@ dino_card_setup(struct pci_bus *bus, uns (unsigned long) 0xfffffffff0000000UL | _8MB, 0xffffffffffffffffUL &~ _8MB, _8MB, NULL, NULL) < 0) { - printk(KERN_WARNING "Dino: Failed to allocate memory region\n"); + struct list_head *ln, *tmp_ln; + + printk(KERN_ERR "Dino: cannot attach bus %s\n", + bus->dev->bus_id); + /* kill the bus, we can't do anything with it */ + list_for_each_safe(ln, tmp_ln, &bus->devices) { + struct pci_dev *dev = pci_dev_b(ln); + + list_del(&dev->global_list); + list_del(&dev->bus_list); + } + return; } bus->resource[1] = res; @@ -526,7 +537,6 @@ dino_card_fixup(struct pci_dev *dev) ** The additional "-1" adjusts for skewing the IRQ<->slot. */ dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); - printk("DINO CONFIG READ GIVES irq_pin %d\n", irq_pin); dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; /* Shouldn't really need to do this but it's in case someone tries ^ permalink raw reply [flat|nested] 50+ messages in thread
[parent not found: <20030903165113.138BF494064@palinux.hppa>]
* [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb [not found] <20030903165113.138BF494064@palinux.hppa> @ 2003-09-03 16:56 ` James Bottomley 0 siblings, 0 replies; 50+ messages in thread From: James Bottomley @ 2003-09-03 16:56 UTC (permalink / raw) To: PARISC list; +Cc: parisc-linux-cvs On Wed, 2003-09-03 at 12:51, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 03/09/03 10:51:13 > > Modified files: > . : Makefile > drivers/net/tulip: eeprom.c tulip.h tulip_core.c > drivers/parisc : dino.c > > Log message: > Fix card mode dino support and make HSC FX (tulip) card work Patch is in two parts: dino bit just corrects some thinkos in the card mode dino code and adds the actual dino device to the prints (useful for debugging if you have more than one dino). The tulip fix simply adds the card to the tulip card table and makes it all work. I've tested this on my C360...however, I had to hack the ccio window to get that to work...I need more time to make this code better. James ===== drivers/net/tulip/eeprom.c 1.9 vs edited ===== --- 1.9/drivers/net/tulip/eeprom.c Mon Oct 28 23:14:42 2002 +++ edited/drivers/net/tulip/eeprom.c Wed Sep 3 11:41:24 2003 @@ -93,8 +93,13 @@ #ifdef __hppa__ unsigned char *ee_data = tp->eeprom; - if (ee_data[0] == 0x3c && ee_data[1] == 0x10 && - (ee_data[2] == 0x63 || ee_data[2] == 0x61) && ee_data[3] == 0x10) { + /* NOTE: The 3x5 FF cards the ee_data is trying to recognise + * need to be brought properly under the tulip initialisation + * structure */ + + if ((tp->flags & NEEDS_FAKE_MEDIA_TABLE) + || (ee_data[0] == 0x3c && ee_data[1] == 0x10 && + (ee_data[2] == 0x63 || ee_data[2] == 0x61) && ee_data[3] == 0x10)) { static unsigned char leafdata[] = { 0x01, /* phy number */ ===== drivers/net/tulip/tulip.h 1.15 vs edited ===== --- 1.15/drivers/net/tulip/tulip.h Sun May 25 22:14:37 2003 +++ edited/drivers/net/tulip/tulip.h Wed Sep 3 11:27:00 2003 @@ -64,6 +64,8 @@ COMET_MAC_ADDR = 0x0800, HAS_PCI_MWI = 0x1000, HAS_PHY_IRQ = 0x2000, + HAS_SWAPPED_SEEPROM = 0x4000, + NEEDS_FAKE_MEDIA_TABLE = 0x8000, }; @@ -86,6 +88,7 @@ I21145, DM910X, CONEXANT, + HP_D21140, }; ===== drivers/net/tulip/tulip_core.c 1.48 vs edited ===== --- 1.48/drivers/net/tulip/tulip_core.c Tue Aug 19 22:53:17 2003 +++ edited/drivers/net/tulip/tulip_core.c Wed Sep 3 11:42:48 2003 @@ -191,10 +191,17 @@ /* RS7112 */ { "Conexant LANfinity", 256, 0x0001ebef, HAS_MII | HAS_ACPI, tulip_timer }, + + /* HP_D21140 */ + { "HSC 100BaseTX Workstation single port (Digital DS21140 Tulip)", 128, + 0x0001ebef, HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI + | HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE, tulip_timer }, + }; static struct pci_device_id tulip_pci_tbl[] = { + { 0x1011, 0x0009, 0x103c, 0x1062, 0, 0, HP_D21140 }, { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 }, { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 }, { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 }, @@ -1459,9 +1466,10 @@ int sa_offset = 0; int ee_addr_size = tulip_read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; - for (i = 0; i < sizeof(tp->eeprom)/2; i++) - ((u16 *)ee_data)[i] = - le16_to_cpu(tulip_read_eeprom(ioaddr, i, ee_addr_size)); + for (i = 0; i < sizeof(tp->eeprom)/2; i++) { + u16 data = tulip_read_eeprom(ioaddr, i, ee_addr_size); + ((u16 *)ee_data)[i] = (tp->flags & HAS_SWAPPED_SEEPROM) ? data : le16_to_cpu(data); + } /* DEC now has a specification (see Notes) but early board makers just put the address in the first EEPROM locations. */ ===== drivers/parisc/dino.c 1.10 vs edited ===== --- 1.10/drivers/parisc/dino.c Sun Aug 24 06:50:06 2003 +++ edited/drivers/parisc/dino.c Wed Sep 3 11:48:51 2003 @@ -401,23 +401,7 @@ { int irq; - /* - * Perform a binary search on set bits. - * `Less than Fatal' and PS2 interrupts aren't supported. - */ - if (mask & 0xf) { - if (mask & 0x3) { - irq = (mask & 0x1) ? 0 : 1; /* PCI INT A, B */ - } else { - irq = (mask & 0x4) ? 2 : 3; /* PCI INT C, D */ - } - } else { - if (mask & 0x30) { - irq = (mask & 0x10) ? 4 : 5; /* PCI INT E, F */ - } else { - irq = (mask & 0x40) ? 6 : 10; /* GSC, RS232 */ - } - } + irq = __ffs(mask); mask &= ~(1<<irq); @@ -479,9 +463,18 @@ int i; struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->dev)); struct resource *res; + char name[128]; + int size; res = &dino_dev->hba.lmmio_space; res->flags = IORESOURCE_MEM; + size = snprintf(name, sizeof(name), "Dino LMMIO (%s)", bus->dev->bus_id); + res->name = kmalloc(size+1, GFP_KERNEL); + if(res->name) + strcpy((char *)res->name, name); + else + res->name = dino_dev->hba.lmmio_space.name; + if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, (unsigned long) 0xfffffffff0000000UL | _8MB, @@ -521,7 +514,7 @@ ** Set Latency Timer to 0xff (not a shared bus) ** Set CACHELINE_SIZE. */ - dino_cfg_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 16, 0xff00 | L1_CACHE_BYTES/4); + dino_cfg_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); /* ** Program INT_LINE for card-mode devices. @@ -532,13 +525,14 @@ ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. ** The additional "-1" adjusts for skewing the IRQ<->slot. */ - dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 8, &irq_pin); + dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); + printk("DINO CONFIG READ GIVES irq_pin %d\n", irq_pin); dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; /* Shouldn't really need to do this but it's in case someone tries ** to bypass PCI services and look at the card themselves. */ - dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 8, dev->irq); + dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); } @@ -818,8 +812,15 @@ { struct dino_device *dino_dev; // Dino specific control struct const char *version = "unknown"; - const char *name = "Dino"; + const int name_len = 32; + char *name; int is_cujo = 0; + + name = kmalloc(name_len, GFP_KERNEL); + if(name) + snprintf(name, name_len, "Dino %s", dev->dev.bus_id); + else + name = "Dino"; if (is_card_dino(&dev->id)) { version = "3.x (card mode)"; ^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2004-05-06 13:27 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz follow: Atom feed
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[not found] <20040228212407.DB126494190@palinux.hppa>
2004-02-28 22:21 ` [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb Joel Soete
2004-02-28 22:42 ` James Bottomley
2004-02-29 9:39 ` Joel Soete
2004-03-04 16:39 ` Joel Soete
[not found] <20040505204811.27F0C4945E4@palinux.hppa>
2004-05-05 20:50 ` James Bottomley
2004-05-06 5:05 ` Randolph Chung
2004-05-06 5:22 ` Randolph Chung
2004-05-06 9:33 ` M. Grabert
2004-05-06 13:25 ` Kyle McMartin
[not found] <20040502161601.DC7C24945C7@palinux.hppa>
2004-05-03 20:51 ` James Bottomley
[not found] <20040501200312.40BB74945E1@palinux.hppa>
2004-05-01 20:09 ` James Bottomley
2004-05-03 8:57 ` Joel Soete
[not found] <20040501160556.D07DC4945CA@palinux.hppa>
2004-05-01 16:13 ` James Bottomley
[not found] <20040430162037.9D2B94945CD@palinux.hppa>
2004-04-30 16:25 ` James Bottomley
[not found] <20040427171140.706074945BD@palinux.hppa>
2004-04-27 17:15 ` James Bottomley
[not found] <20040425145051.10F5C4942B8@palinux.hppa>
2004-04-25 14:55 ` James Bottomley
[not found] <20040414174535.81173494194@palinux.hppa>
2004-04-14 17:53 ` James Bottomley
[not found] <20040412154800.D31F6494194@palinux.hppa>
2004-04-12 15:55 ` James Bottomley
[not found] <20040407004901.031D3494194@palinux.hppa>
2004-04-07 0:54 ` James Bottomley
2004-04-08 6:15 ` Joel Soete
2004-04-08 12:36 ` James Bottomley
[not found] <20040406213446.CB675494194@palinux.hppa>
2004-04-06 21:37 ` James Bottomley
[not found] <20040405174131.84BF1494194@palinux.hppa>
2004-04-06 13:21 ` Carlos O'Donell
2004-04-06 14:18 ` James Bottomley
2004-04-06 15:40 ` Randolph Chung
[not found] <20040405024740.9330F494194@palinux.hppa>
2004-04-05 2:49 ` James Bottomley
2004-04-05 2:54 ` James Bottomley
[not found] <20040320210116.7A727494553@palinux.hppa>
2004-03-20 21:04 ` James Bottomley
2004-03-20 21:10 ` Helge Deller
2004-03-20 21:13 ` Helge Deller
2004-02-06 7:31 [parisc-linux] " Joel Soete
2004-02-06 17:50 ` Grant Grundler
2004-02-06 18:06 ` bame
2004-02-06 19:16 ` Randolph Chung
2004-02-06 17:08 ` Joel Soete
2004-02-07 6:40 ` Randolph Chung
2004-02-09 7:26 ` Joel Soete
[not found] <20040204182455.1CC11494191@palinux.hppa>
2004-02-05 9:20 ` [parisc-linux] " Randolph Chung
2004-02-05 15:19 ` James Bottomley
2004-02-05 15:29 ` [parisc-linux] " Joel Soete
2004-02-05 20:31 ` Randolph Chung
2004-02-05 18:49 ` Joel Soete
[not found] <20040113155603.CBCC249425A@palinux.hppa>
2004-01-13 15:58 ` [parisc-linux] " James Bottomley
[not found] <20030924175431.D51BC49408B@palinux.hppa>
2003-09-24 18:01 ` James Bottomley
[not found] <20030919010356.148684940A4@palinux.hppa>
2003-09-19 1:06 ` James Bottomley
2003-09-19 11:24 ` Randolph Chung
2003-09-19 14:02 ` James Bottomley
2003-09-19 18:24 ` Jim Hull
[not found] <20030903200300.8B7B7494064@palinux.hppa>
2003-09-03 20:07 ` James Bottomley
[not found] <20030903165113.138BF494064@palinux.hppa>
2003-09-03 16:56 ` James Bottomley
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