* [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
@ 2022-06-01 7:27 ZhenGuo Yin
2022-06-01 11:48 ` Christian König
2022-06-01 14:16 ` Alex Deucher
0 siblings, 2 replies; 5+ messages in thread
From: ZhenGuo Yin @ 2022-06-01 7:27 UTC (permalink / raw)
To: amd-gfx; +Cc: ZhenGuo Yin, jingwen.chen2
The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.
Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c5f46d264b23..8331e0c5e18e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3784,7 +3784,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0), 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -3799,7 +3799,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+ tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0));
if (tmp == 0xDEADBEEF)
break;
if (amdgpu_emu_mode == 1)
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
2022-06-01 7:27 [PATCH] drm/amdgpu: fix scratch register access method in SRIOV ZhenGuo Yin
@ 2022-06-01 11:48 ` Christian König
2022-06-01 14:16 ` Alex Deucher
1 sibling, 0 replies; 5+ messages in thread
From: Christian König @ 2022-06-01 11:48 UTC (permalink / raw)
To: ZhenGuo Yin, amd-gfx; +Cc: jingwen.chen2
Am 01.06.22 um 09:27 schrieb ZhenGuo Yin:
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Maybe better but the register offset into a local constant then.
Apart from that looks good to me.
Regards,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c5f46d264b23..8331e0c5e18e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3784,7 +3784,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> unsigned i;
> int r;
>
> - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
> + WREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0), 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
> @@ -3799,7 +3799,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> amdgpu_ring_commit(ring);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
> + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0));
> if (tmp == 0xDEADBEEF)
> break;
> if (amdgpu_emu_mode == 1)
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
2022-06-01 7:27 [PATCH] drm/amdgpu: fix scratch register access method in SRIOV ZhenGuo Yin
2022-06-01 11:48 ` Christian König
@ 2022-06-01 14:16 ` Alex Deucher
1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-06-01 14:16 UTC (permalink / raw)
To: ZhenGuo Yin; +Cc: Jingwen Chen, amd-gfx list
On Wed, Jun 1, 2022 at 3:27 AM ZhenGuo Yin <zhenguo.yin@amd.com> wrote:
>
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Missing your signed-off-by.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c5f46d264b23..8331e0c5e18e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3784,7 +3784,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> unsigned i;
> int r;
>
> - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
> + WREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0), 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
> @@ -3799,7 +3799,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> amdgpu_ring_commit(ring);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
> + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0));
> if (tmp == 0xDEADBEEF)
> break;
> if (amdgpu_emu_mode == 1)
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
@ 2022-07-18 19:32 Gavin Wan
2022-07-18 19:40 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: Gavin Wan @ 2022-07-18 19:32 UTC (permalink / raw)
To: amd-gfx; +Cc: Gavin Wan
The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.
Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
Change-Id: I888cb3b96856583e764b35a098bcf8bff01ad90c
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5349ca4d19e3..c6e0f9313a7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -987,23 +987,23 @@ static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
+ uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
uint32_t tmp = 0;
unsigned i;
int r;
- WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+ WREG32(scratch, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
return r;
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
- PACKET3_SET_UCONFIG_REG_START);
+ amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+ tmp = RREG32(scratch);
if (tmp == 0xDEADBEEF)
break;
udelay(1);
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
2022-07-18 19:32 Gavin Wan
@ 2022-07-18 19:40 ` Christian König
0 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2022-07-18 19:40 UTC (permalink / raw)
To: Gavin Wan, amd-gfx
Am 18.07.22 um 21:32 schrieb Gavin Wan:
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
>
> Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
> Change-Id: I888cb3b96856583e764b35a098bcf8bff01ad90c
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5349ca4d19e3..c6e0f9313a7f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -987,23 +987,23 @@ static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> + uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
> uint32_t tmp = 0;
> unsigned i;
> int r;
>
> - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
> + WREG32(scratch, 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 3);
> if (r)
> return r;
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> - amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
> - PACKET3_SET_UCONFIG_REG_START);
> + amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
> amdgpu_ring_write(ring, 0xDEADBEEF);
> amdgpu_ring_commit(ring);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
> + tmp = RREG32(scratch);
> if (tmp == 0xDEADBEEF)
> break;
> udelay(1);
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-07-18 19:40 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2022-06-01 7:27 [PATCH] drm/amdgpu: fix scratch register access method in SRIOV ZhenGuo Yin
2022-06-01 11:48 ` Christian König
2022-06-01 14:16 ` Alex Deucher
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2022-07-18 19:32 Gavin Wan
2022-07-18 19:40 ` Christian König
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