From: Nishanth Menon <nm@ti.com>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: linux-omap <linux-omap@vger.kernel.org>,
linux-arm <linux-arm-kernel@lists.infradead.org>,
Jean Pihet <jean.pihet@newoldbits.com>,
Kevin <khilman@deeprootsystems.com>, Tony <tony@atomide.com>
Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Date: Mon, 20 Dec 2010 07:33:09 -0600 [thread overview]
Message-ID: <4D0F5B15.1020309@ti.com> (raw)
In-Reply-To: <e6ba48e58d90204a23a5e948700a5166@mail.gmail.com>
Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
[..]
> So may be you could update the change log something like below.
>
> While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> The reset behavior is implementation specific as per ARMv7 TRM and
> hence $L2 needs to be invalidated before it's use. Since the
> AUXCTRL register is also reconfigured, disable L2 cache before
> invalidating it and re-enables it afterwards. This is as per
> Cortex-A8 ARM documentation.
> Currently this is identified as being needed on OMAP3630 as the
> disable/enable is done from "public side" while, on OMAP3430, this
> is done in the "secure side".
Thanks, will update the rev5 patch with this commit log.
--
Regards,
Nishanth Menon
WARNING: multiple messages have this Message-ID (diff)
From: nm@ti.com (Nishanth Menon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Date: Mon, 20 Dec 2010 07:33:09 -0600 [thread overview]
Message-ID: <4D0F5B15.1020309@ti.com> (raw)
In-Reply-To: <e6ba48e58d90204a23a5e948700a5166@mail.gmail.com>
Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
[..]
> So may be you could update the change log something like below.
>
> While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> The reset behavior is implementation specific as per ARMv7 TRM and
> hence $L2 needs to be invalidated before it's use. Since the
> AUXCTRL register is also reconfigured, disable L2 cache before
> invalidating it and re-enables it afterwards. This is as per
> Cortex-A8 ARM documentation.
> Currently this is identified as being needed on OMAP3630 as the
> disable/enable is done from "public side" while, on OMAP3430, this
> is done in the "secure side".
Thanks, will update the rev5 patch with this commit log.
--
Regards,
Nishanth Menon
next prev parent reply other threads:[~2010-12-20 13:33 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-18 22:53 [PATCH v4 0/7] OMAP: idle path errata fixes Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:43 ` Santosh Shilimkar
2010-12-20 6:43 ` Santosh Shilimkar
2010-12-20 10:19 ` Jean Pihet
2010-12-20 10:19 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:47 ` Santosh Shilimkar
2010-12-20 6:47 ` Santosh Shilimkar
2010-12-20 14:16 ` Nishanth Menon
2010-12-20 14:16 ` Nishanth Menon
2010-12-20 10:23 ` Jean Pihet
2010-12-20 10:23 ` Jean Pihet
2010-12-20 11:33 ` Peter 'p2' De Schrijver
2010-12-20 14:21 ` Nishanth Menon
2010-12-20 14:21 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 3/7] omap3: pm: introduce errata handling Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 10:18 ` Jean Pihet
2010-12-20 10:18 ` Jean Pihet
2010-12-20 14:39 ` Nishanth Menon
2010-12-20 14:39 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:59 ` Santosh Shilimkar
2010-12-20 6:59 ` Santosh Shilimkar
2010-12-20 11:23 ` Nishanth Menon
2010-12-20 11:23 ` Nishanth Menon
2010-12-20 12:15 ` Santosh Shilimkar
2010-12-20 12:15 ` Santosh Shilimkar
2010-12-20 10:27 ` Jean Pihet
2010-12-20 10:27 ` Jean Pihet
2010-12-20 14:45 ` Nishanth Menon
2010-12-20 14:45 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 7:13 ` Santosh Shilimkar
2010-12-20 7:13 ` Santosh Shilimkar
2010-12-20 11:44 ` Nishanth Menon
2010-12-20 11:44 ` Nishanth Menon
2010-12-20 12:14 ` Santosh Shilimkar
2010-12-20 12:14 ` Santosh Shilimkar
2010-12-20 13:08 ` Nishanth Menon
2010-12-20 13:08 ` Nishanth Menon
2010-12-20 13:29 ` Santosh Shilimkar
2010-12-20 13:29 ` Santosh Shilimkar
2010-12-20 13:33 ` Nishanth Menon [this message]
2010-12-20 13:33 ` Nishanth Menon
2010-12-20 13:37 ` Santosh Shilimkar
2010-12-20 13:37 ` Santosh Shilimkar
2010-12-20 10:28 ` Jean Pihet
2010-12-20 10:28 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 7:16 ` Santosh Shilimkar
2010-12-20 7:16 ` Santosh Shilimkar
2010-12-20 10:28 ` Jean Pihet
2010-12-20 10:28 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2 Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:51 ` Santosh Shilimkar
2010-12-20 6:51 ` Santosh Shilimkar
2010-12-20 10:26 ` Jean Pihet
2010-12-20 10:26 ` Jean Pihet
2010-12-20 11:22 ` Nishanth Menon
2010-12-20 11:22 ` Nishanth Menon
2010-12-20 19:05 ` Kevin Hilman
2010-12-20 19:05 ` Kevin Hilman
2010-12-20 19:07 ` Nishanth Menon
2010-12-20 19:07 ` Nishanth Menon
2010-12-20 10:17 ` [PATCH v4 0/7] OMAP: idle path errata fixes Jean Pihet
2010-12-20 10:17 ` Jean Pihet
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