From: Stephen Boyd <sboyd@codeaurora.org>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: David Brown <davidb@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/4] msm: scm: Get cacheline size from CTR
Date: Thu, 24 Feb 2011 11:50:39 -0800 [thread overview]
Message-ID: <4D66B68F.6010706@codeaurora.org> (raw)
In-Reply-To: <4D66B236.4030003@ru.mvista.com>
On 02/24/2011 11:32 AM, Sergei Shtylyov wrote:
> Stephen Boyd wrote:
>
>> @@ -207,6 +204,14 @@ static int __scm_call(const struct scm_command
>> *cmd)
>> return ret;
>> }
>>
>> +static inline u32 dcache_line_size(void)
>> +{
>> + u32 ctr;
>> +
>> + asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
>> + return 4 << ((ctr >> 16) & 0xf);
>> +}
>
> Won't generic cache_line_size() macro do instead? It's defined as
> L1_CACHE_BYTES.
>
Interesting. It would be the same value (32) but I'm not sure how
multi-platform friendly that will be since L1_CACHE_BYTES is (1 <<
CONFIG_ARM_L1_CACHE_SHIFT). I suppose we can punt supporting platforms
with different cache line sizes in one kernel for another day.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] msm: scm: Get cacheline size from CTR
Date: Thu, 24 Feb 2011 11:50:39 -0800 [thread overview]
Message-ID: <4D66B68F.6010706@codeaurora.org> (raw)
In-Reply-To: <4D66B236.4030003@ru.mvista.com>
On 02/24/2011 11:32 AM, Sergei Shtylyov wrote:
> Stephen Boyd wrote:
>
>> @@ -207,6 +204,14 @@ static int __scm_call(const struct scm_command
>> *cmd)
>> return ret;
>> }
>>
>> +static inline u32 dcache_line_size(void)
>> +{
>> + u32 ctr;
>> +
>> + asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
>> + return 4 << ((ctr >> 16) & 0xf);
>> +}
>
> Won't generic cache_line_size() macro do instead? It's defined as
> L1_CACHE_BYTES.
>
Interesting. It would be the same value (32) but I'm not sure how
multi-platform friendly that will be since L1_CACHE_BYTES is (1 <<
CONFIG_ARM_L1_CACHE_SHIFT). I suppose we can punt supporting platforms
with different cache line sizes in one kernel for another day.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-02-24 19:50 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-24 18:44 [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 18:44 ` [PATCH 1/4] msm: scm: Mark inline asm as volatile Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-25 11:56 ` Will Deacon
2011-02-25 11:56 ` Will Deacon
2011-02-25 11:56 ` Will Deacon
2011-02-25 19:05 ` Stephen Boyd
2011-02-25 19:05 ` Stephen Boyd
2011-02-26 18:12 ` David Brown
2011-02-26 18:12 ` David Brown
2011-02-26 19:43 ` Nicolas Pitre
2011-02-26 19:43 ` Nicolas Pitre
2011-02-27 17:41 ` David Brown
2011-02-27 17:41 ` David Brown
2011-02-28 2:21 ` Nicolas Pitre
2011-02-28 2:21 ` Nicolas Pitre
2011-02-27 11:10 ` Will Deacon
2011-02-27 11:10 ` Will Deacon
2011-02-27 17:38 ` David Brown
2011-02-27 17:38 ` David Brown
2011-03-01 10:30 ` Will Deacon
2011-03-01 10:30 ` Will Deacon
2011-02-24 18:44 ` [PATCH 2/4] msm: scm: Fix improper register assignment Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-25 13:23 ` Will Deacon
2011-02-25 13:23 ` Will Deacon
2011-02-25 19:22 ` Stephen Boyd
2011-02-25 19:22 ` Stephen Boyd
2011-02-26 5:09 ` Saravana Kannan
2011-02-26 5:09 ` Saravana Kannan
2011-02-26 8:47 ` Russell King - ARM Linux
2011-02-26 8:47 ` Russell King - ARM Linux
2011-02-26 17:58 ` David Brown
2011-02-26 17:58 ` David Brown
2011-02-26 20:04 ` Nicolas Pitre
2011-02-26 20:04 ` Nicolas Pitre
2011-03-01 10:37 ` Will Deacon
2011-03-01 10:37 ` Will Deacon
2011-03-01 21:29 ` Saravana Kannan
2011-03-01 21:29 ` Saravana Kannan
2011-03-02 0:02 ` Nicolas Pitre
2011-03-02 0:02 ` Nicolas Pitre
2011-03-01 13:54 ` Will Deacon
2011-03-01 13:54 ` Will Deacon
2011-02-24 18:44 ` [PATCH 3/4] msm: scm: Check for interruption immediately Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 18:44 ` [PATCH 4/4] msm: scm: Get cacheline size from CTR Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 19:01 ` Thomas Gleixner
2011-02-24 19:01 ` Thomas Gleixner
2011-02-24 19:44 ` Stephen Boyd
2011-02-24 19:44 ` Stephen Boyd
2011-02-24 19:56 ` Thomas Gleixner
2011-02-24 19:56 ` Thomas Gleixner
2011-03-01 4:21 ` Stephen Boyd
2011-03-01 4:21 ` Stephen Boyd
2011-02-24 19:32 ` Sergei Shtylyov
2011-02-24 19:32 ` Sergei Shtylyov
2011-02-24 19:50 ` Stephen Boyd [this message]
2011-02-24 19:50 ` Stephen Boyd
2011-02-24 19:55 ` Russell King - ARM Linux
2011-02-24 19:55 ` Russell King - ARM Linux
2011-03-09 19:29 ` [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-03-09 19:29 ` Stephen Boyd
2011-03-10 20:06 ` David Brown
2011-03-10 20:06 ` David Brown
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