From: Stephen Boyd <sboyd@codeaurora.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: David Brown <davidb@codeaurora.org>,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Russell King - ARM Linux <linux@arm.linux.org.uk>
Subject: Re: [PATCH 4/4] msm: scm: Get cacheline size from CTR
Date: Mon, 28 Feb 2011 20:21:00 -0800 [thread overview]
Message-ID: <4D6C742C.40507@codeaurora.org> (raw)
In-Reply-To: <alpine.LFD.2.00.1102242056010.2701@localhost6.localdomain6>
On 02/24/2011 11:56 AM, Thomas Gleixner wrote:
> On Thu, 24 Feb 2011, Stephen Boyd wrote:
>
>>
>> I definitely don't want to do it for every loop. I'm fine with getting
>> it every scm_call() invocation though.
>>
>> For now, I'll pull the end and cacheline_size variables out of the
>> do-while loop.
>
> Why not do it correct right away and retrieve it in an __init
> function?
That would require an early_initcall, so hopefully that is fine.
I wonder why the generic arm v7 cache operations don't do the same thing
and store the dcache line size somewhere. Every dma operation is
essentially calling dcache_line_size(). Perhaps some generic arm code
should be determining the dcache line size really early on and storing
it in the proc_info_list? Then both the dma code and scm code could
query the processor for the dcache line size with something like
cpu_dcache_line_size?
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] msm: scm: Get cacheline size from CTR
Date: Mon, 28 Feb 2011 20:21:00 -0800 [thread overview]
Message-ID: <4D6C742C.40507@codeaurora.org> (raw)
In-Reply-To: <alpine.LFD.2.00.1102242056010.2701@localhost6.localdomain6>
On 02/24/2011 11:56 AM, Thomas Gleixner wrote:
> On Thu, 24 Feb 2011, Stephen Boyd wrote:
>
>>
>> I definitely don't want to do it for every loop. I'm fine with getting
>> it every scm_call() invocation though.
>>
>> For now, I'll pull the end and cacheline_size variables out of the
>> do-while loop.
>
> Why not do it correct right away and retrieve it in an __init
> function?
That would require an early_initcall, so hopefully that is fine.
I wonder why the generic arm v7 cache operations don't do the same thing
and store the dcache line size somewhere. Every dma operation is
essentially calling dcache_line_size(). Perhaps some generic arm code
should be determining the dcache line size really early on and storing
it in the proc_info_list? Then both the dma code and scm code could
query the processor for the dcache line size with something like
cpu_dcache_line_size?
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-03-01 4:21 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-24 18:44 [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 18:44 ` [PATCH 1/4] msm: scm: Mark inline asm as volatile Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-25 11:56 ` Will Deacon
2011-02-25 11:56 ` Will Deacon
2011-02-25 11:56 ` Will Deacon
2011-02-25 19:05 ` Stephen Boyd
2011-02-25 19:05 ` Stephen Boyd
2011-02-26 18:12 ` David Brown
2011-02-26 18:12 ` David Brown
2011-02-26 19:43 ` Nicolas Pitre
2011-02-26 19:43 ` Nicolas Pitre
2011-02-27 17:41 ` David Brown
2011-02-27 17:41 ` David Brown
2011-02-28 2:21 ` Nicolas Pitre
2011-02-28 2:21 ` Nicolas Pitre
2011-02-27 11:10 ` Will Deacon
2011-02-27 11:10 ` Will Deacon
2011-02-27 17:38 ` David Brown
2011-02-27 17:38 ` David Brown
2011-03-01 10:30 ` Will Deacon
2011-03-01 10:30 ` Will Deacon
2011-02-24 18:44 ` [PATCH 2/4] msm: scm: Fix improper register assignment Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-25 13:23 ` Will Deacon
2011-02-25 13:23 ` Will Deacon
2011-02-25 19:22 ` Stephen Boyd
2011-02-25 19:22 ` Stephen Boyd
2011-02-26 5:09 ` Saravana Kannan
2011-02-26 5:09 ` Saravana Kannan
2011-02-26 8:47 ` Russell King - ARM Linux
2011-02-26 8:47 ` Russell King - ARM Linux
2011-02-26 17:58 ` David Brown
2011-02-26 17:58 ` David Brown
2011-02-26 20:04 ` Nicolas Pitre
2011-02-26 20:04 ` Nicolas Pitre
2011-03-01 10:37 ` Will Deacon
2011-03-01 10:37 ` Will Deacon
2011-03-01 21:29 ` Saravana Kannan
2011-03-01 21:29 ` Saravana Kannan
2011-03-02 0:02 ` Nicolas Pitre
2011-03-02 0:02 ` Nicolas Pitre
2011-03-01 13:54 ` Will Deacon
2011-03-01 13:54 ` Will Deacon
2011-02-24 18:44 ` [PATCH 3/4] msm: scm: Check for interruption immediately Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 18:44 ` [PATCH 4/4] msm: scm: Get cacheline size from CTR Stephen Boyd
2011-02-24 18:44 ` Stephen Boyd
2011-02-24 19:01 ` Thomas Gleixner
2011-02-24 19:01 ` Thomas Gleixner
2011-02-24 19:44 ` Stephen Boyd
2011-02-24 19:44 ` Stephen Boyd
2011-02-24 19:56 ` Thomas Gleixner
2011-02-24 19:56 ` Thomas Gleixner
2011-03-01 4:21 ` Stephen Boyd [this message]
2011-03-01 4:21 ` Stephen Boyd
2011-02-24 19:32 ` Sergei Shtylyov
2011-02-24 19:32 ` Sergei Shtylyov
2011-02-24 19:50 ` Stephen Boyd
2011-02-24 19:50 ` Stephen Boyd
2011-02-24 19:55 ` Russell King - ARM Linux
2011-02-24 19:55 ` Russell King - ARM Linux
2011-03-09 19:29 ` [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-03-09 19:29 ` Stephen Boyd
2011-03-10 20:06 ` David Brown
2011-03-10 20:06 ` David Brown
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