[PATCH] Ivybridge fixes

[PATCH] Ivybridge fixes

[Eugeni Dodonov]

The combination of those 4 workarounds seem to solve random hand-hangs observed
in GLBenchmark Egypt and (much more rarely) in World of Padman and Unigine
demos.

Eugeni Dodonov (4):
  drm/i915: gen7: implement rczunit workaround
  drm/i915: gen7: add two more IVB workarounds
  drm/i915: gen7: work around a system hang on IVB
  drm/i915: gen7: another IVB workaround

 drivers/gpu/drm/i915/i915_reg.h      |   17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   23 +++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

-- 
1.7.8.1

[PATCH 1/4] drm/i915: gen7: implement rczunit workaround

[Eugeni Dodonov]

This is yet another workaround related to clock gating which we need on Gen7.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3afb78..80fd6b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3618,6 +3618,7 @@
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 
 #define GEN6_UCGCTL2				0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b3b51c4..a72100f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8416,8 +8416,12 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	 *
 	 * According to the spec, bit 11 (RCCUNIT) must also be set,
 	 * but we didn't debug actual testcases to find it out.
+	 *
+	 * The bit 13 (RCZUNIT) must also be set, to implement the
+	 * WaDisableRCZUnitClockGating workaround.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
+		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.7.8.1

[PATCH 2/4] drm/i915: gen7: add two more IVB workarounds

[Eugeni Dodonov]

This adds two cache-related workarounds for Ivy Bridge which can lead to 3D
ring hangs and corruptions.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80fd6b5..92274b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3028,6 +3028,13 @@
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1			0x7010
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a72100f..49e5870 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8445,6 +8445,12 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 		   ILK_DPARB_CLK_GATE  |
 		   ILK_DPFD_CLK_GATE);
 
+	/* IVB workarounds */
+	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+			GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+			GEN7_WA_L3_CHICKEN_MODE);
+
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
-- 
1.7.8.1

[PATCH 3/4] drm/i915: gen7: work around a system hang on IVB

[Eugeni Dodonov]

This adds the workaround for WaCatErrorRejectionIssue which could result in a
system hang..

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    4 ++++
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92274b1..4f25cd5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3035,6 +3035,10 @@
 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
 
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 49e5870..f7e86b8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8451,6 +8451,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
 			GEN7_WA_L3_CHICKEN_MODE);
 
+	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
-- 
1.7.8.1

[PATCH 4/4] drm/i915: gen7: another IVB workaround

[Eugeni Dodonov]

Add the WaDisableEUInstructionShootdown workaround for Ivy Bridge.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    5 +++++
 drivers/gpu/drm/i915/intel_display.c |    9 +++++++++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4f25cd5..9ba7406 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3039,6 +3039,11 @@
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
 
+/* WaDisableEUInstructionShootdown */
+#define GEN7_ROW_CHICKEN_MMIO_TDL			 0xE4F0
+#define GEN7_ROW_CHICKEN_MMIO_TDL_GT2		0xF4F0
+#define GEN7_ROW_CHICKEN_DISABLE_EU_INSTR_SHOOTDOWN  ((1 << 8) | (1 << 9))
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f7e86b8..1a87574 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8455,6 +8455,15 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
+	/* WaDisableEUInstructionShootdown */
+	I915_WRITE(GEN7_ROW_CHICKEN_MMIO_TDL,
+			I915_READ(GEN7_ROW_CHICKEN_MMIO_TDL) |
+			GEN7_ROW_CHICKEN_DISABLE_EU_INSTR_SHOOTDOWN);
+
+	I915_WRITE(GEN7_ROW_CHICKEN_MMIO_TDL_GT2,
+			I915_READ(GEN7_ROW_CHICKEN_MMIO_TDL_GT2) |
+			GEN7_ROW_CHICKEN_DISABLE_EU_INSTR_SHOOTDOWN);
+
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
-- 
1.7.8.1

Re: [PATCH 2/4] drm/i915: gen7: add two more IVB workarounds

[Kenneth Graunke]

On 02/03/2012 12:22 PM, Eugeni Dodonov wrote:
> This adds two cache-related workarounds for Ivy Bridge which can lead to 3D
> ring hangs and corruptions.
>
> Signed-off-by: Eugeni Dodonov<eugeni.dodonov@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
>   drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>   2 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80fd6b5..92274b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3028,6 +3028,13 @@
>   #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>   #define  DISP_FBC_WM_DIS		(1<<15)
>
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1			0x7010
> +#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C

I'm skeptical of this value.  Your mask doesn't match the bits you're 
setting:

Actual chicken bits - bitdecode(0x3C4FFF8C & 0x0000ffff):
[2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15]

Mask bits - bitdecode(0x3C4FFF8C >> 16):
[0, 1, 2, 3, 6, 10, 11, 12, 13]

Also, this is an awful lot of workarounds!  I doubt we need all of them. 
  On the BSpec Workaround page, I see a recommendation to set bits 10 
and 26, but I don't see a rationale for the other ones.  Is that sufficient?

I'd also prefer to see these broken down into separate #defines for each 
bit rather than setting a magical value.

> +#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +

This WA looks good and matches the docs (vol1i L3 URB > L3 Register 
Space (Bspec) > config space for L3 > L3CHMD - l3chicken mode).

>   /* PCH */
>
>   /* south display engine interrupt */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a72100f..49e5870 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8445,6 +8445,12 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>   		   ILK_DPARB_CLK_GATE  |
>   		   ILK_DPFD_CLK_GATE);
>
> +	/* IVB workarounds */
> +	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> +			GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> +			GEN7_WA_L3_CHICKEN_MODE);
> +
>   	for_each_pipe(pipe) {
>   		I915_WRITE(DSPCNTR(pipe),
>   			   I915_READ(DSPCNTR(pipe)) |

Re: [PATCH 2/4] drm/i915: gen7: add two more IVB workarounds

[Kenneth Graunke]

On 02/03/2012 12:22 PM, Eugeni Dodonov wrote:
> This adds two cache-related workarounds for Ivy Bridge which can lead to 3D
> ring hangs and corruptions.
>
> Signed-off-by: Eugeni Dodonov<eugeni.dodonov@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
>   drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>   2 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80fd6b5..92274b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3028,6 +3028,13 @@
>   #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>   #define  DISP_FBC_WM_DIS		(1<<15)
>
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1			0x7010
> +#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
> +
> +#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +
>   /* PCH */
>
>   /* south display engine interrupt */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a72100f..49e5870 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8445,6 +8445,12 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>   		   ILK_DPARB_CLK_GATE  |
>   		   ILK_DPFD_CLK_GATE);
>
> +	/* IVB workarounds */
> +	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> +			GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> +			GEN7_WA_L3_CHICKEN_MODE);
> +
>   	for_each_pipe(pipe) {
>   		I915_WRITE(DSPCNTR(pipe),
>   			   I915_READ(DSPCNTR(pipe)) |

Also, shouldn't these be in the ivybridge_init_clock_gating function, 
not gen6?  These are clearly Gen7 registers.

Re: [PATCH 3/4] drm/i915: gen7: work around a system hang on IVB

[Kenneth Graunke]

On 02/03/2012 12:22 PM, Eugeni Dodonov wrote:
> This adds the workaround for WaCatErrorRejectionIssue which could result in a
> system hang..
>
> Signed-off-by: Eugeni Dodonov<eugeni.dodonov@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |    4 ++++
>   drivers/gpu/drm/i915/intel_display.c |    4 ++++
>   2 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 92274b1..4f25cd5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3035,6 +3035,10 @@
>   #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
>   #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
>
> +/* WaCatErrorRejectionIssue */
> +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> +#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> +
>   /* PCH */
>
>   /* south display engine interrupt */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 49e5870..f7e86b8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8451,6 +8451,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>   	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
>   			GEN7_WA_L3_CHICKEN_MODE);
>
> +	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> +
>   	for_each_pipe(pipe) {
>   		I915_WRITE(DSPCNTR(pipe),
>   			   I915_READ(DSPCNTR(pipe)) |

Ditto: shouldn't this be in ivybridge_init_clock_gating?

This does match the docs (vol1g GT Interface Register [IVB] > GT 
Interface Register DevIVB > MBCunit Config Space > SQCM - SQ Chicken Modes).

Assuming it gets in a Gen7-specific location...
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

[PATCH 0/3] Ivy Bridge hard-hang fixes

[Eugeni Dodonov]

Hi,

this is a set of patches which should fix hard-hangs for Ivy Bridge in
different workloads, among which GLBenchmark Egypt is the most notable one.

It also seems to solve random hard-hangs in other applications (the ones I've
seen the most are in World of Padman, Unigine games and Nexuiz).


Eugeni Dodonov (3):
  drm/i915: gen7: implement rczunit workaround
  drm/i915: gen7: add two more IVB workarounds
  drm/i915: gen7: work around a system hang on IVB

 drivers/gpu/drm/i915/i915_reg.h      |   12 ++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   25 ++++++++++++++++++++++---
 2 files changed, 34 insertions(+), 3 deletions(-)

-- 
1.7.8.4

[PATCH 1/3] drm/i915: gen7: implement rczunit workaround

[Eugeni Dodonov]

This is yet another workaround related to clock gating which we need on
Ivy Bridge.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   14 +++++++++++---
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3afb78..80fd6b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3618,6 +3618,7 @@
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 
 #define GEN6_UCGCTL2				0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f1744aa..1defd42 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8396,6 +8396,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+	u32 gstate;
 
 	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 
@@ -8416,10 +8417,17 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	 *
 	 * According to the spec, bit 11 (RCCUNIT) must also be set,
 	 * but we didn't debug actual testcases to find it out.
+	 *
+	 * The bit 13 (RCZUNIT) must also be set, to implement the
+	 * WaDisableRCZUnitClockGating workaround on Ivy Bridge.
 	 */
-	I915_WRITE(GEN6_UCGCTL2,
-		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
+	gstate = GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
+		GEN6_RCCUNIT_CLOCK_GATE_DISABLE;
+
+	if (IS_IVYBRIDGE(dev))
+		gstate |= GEN6_RCZUNIT_CLOCK_GATE_DISABLE;
+
+	I915_WRITE(GEN6_UCGCTL2, gstate);
 
 	/*
 	 * According to the spec the following bits should be
-- 
1.7.8.4

[PATCH 2/3] drm/i915: gen7: add two more IVB workarounds

[Eugeni Dodonov]

This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80fd6b5..92274b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3028,6 +3028,13 @@
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1			0x7010
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1defd42..eee0e75 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8475,6 +8475,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+			GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+			GEN7_WA_L3_CHICKEN_MODE);
+
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
-- 
1.7.8.4

[PATCH 3/3] drm/i915: gen7: work around a system hang on IVB

[Eugeni Dodonov]

This adds the workaround for WaCatErrorRejectionIssue which could result
in a system hang.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    4 ++++
 drivers/gpu/drm/i915/intel_display.c |    5 +++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92274b1..4f25cd5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3035,6 +3035,10 @@
 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
 
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eee0e75..08c3292 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8481,6 +8481,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
 			GEN7_WA_L3_CHICKEN_MODE);
 
+	/* This is required by WaCatErrorRejectionIssue */
+	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
-- 
1.7.8.4

Re: [PATCH 2/3] drm/i915: gen7: add two more IVB workarounds

[Kenneth Graunke]

On 02/05/2012 02:47 PM, Eugeni Dodonov wrote:
> This adds two cache-related workarounds for Ivy Bridge which can lead to
> 3D ring hangs and corruptions.
>
> Signed-off-by: Eugeni Dodonov<eugeni.dodonov@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
>   drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>   2 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80fd6b5..92274b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3028,6 +3028,13 @@
>   #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>   #define  DISP_FBC_WM_DIS		(1<<15)
>
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1			0x7010
> +#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
> +
> +#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +
>   /* PCH */
>
>   /* south display engine interrupt */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1defd42..eee0e75 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8475,6 +8475,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>   		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>   		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> +	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
> +	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> +			GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> +			GEN7_WA_L3_CHICKEN_MODE);
> +
>   	for_each_pipe(pipe) {
>   		I915_WRITE(DSPCNTR(pipe),
>   			   I915_READ(DSPCNTR(pipe)) |

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Re: [PATCH 0/3] Ivy Bridge hard-hang fixes

[Keith Packard]

[-- Attachment #1.1: Type: text/plain, Size: 901 bytes --]

On Sun,  5 Feb 2012 20:47:03 -0200, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> Hi,
> 
> this is a set of patches which should fix hard-hangs for Ivy Bridge in
> different workloads, among which GLBenchmark Egypt is the most notable one.
> 
> It also seems to solve random hard-hangs in other applications (the ones I've
> seen the most are in World of Padman, Unigine games and Nexuiz).
> 
> 
> Eugeni Dodonov (3):
>   drm/i915: gen7: implement rczunit workaround
>   drm/i915: gen7: add two more IVB workarounds
>   drm/i915: gen7: work around a system hang on IVB

Would be nice if the summary lines for these patches was a bit more
descriptive...

Also, 3/3 has a Rb line from Ken, but I don't see the mail from him with
that.

These look like -fixes material; is there someone already reviewing 1/3
so I can get them upstreamed soon?

-- 
keith.packard@intel.com

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Re: [PATCH 1/3] drm/i915: gen7: implement rczunit workaround

[Kenneth Graunke]

On 02/05/2012 02:47 PM, Eugeni Dodonov wrote:
> This is yet another workaround related to clock gating which we need on
> Ivy Bridge.
>
> Signed-off-by: Eugeni Dodonov<eugeni.dodonov@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |    1 +
>   drivers/gpu/drm/i915/intel_display.c |   14 +++++++++++---
>   2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3afb78..80fd6b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3618,6 +3618,7 @@
>   #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>
>   #define GEN6_UCGCTL2				0x9404
> +# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1<<  13)
>   # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1<<  12)
>   # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1<<  11)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f1744aa..1defd42 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8396,6 +8396,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	int pipe;
>   	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> +	u32 gstate;
>
>   	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
>
> @@ -8416,10 +8417,17 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>   	 *
>   	 * According to the spec, bit 11 (RCCUNIT) must also be set,
>   	 * but we didn't debug actual testcases to find it out.
> +	 *
> +	 * The bit 13 (RCZUNIT) must also be set, to implement the
> +	 * WaDisableRCZUnitClockGating workaround on Ivy Bridge.
>   	 */
> -	I915_WRITE(GEN6_UCGCTL2,
> -		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> -		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> +	gstate = GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> +		GEN6_RCCUNIT_CLOCK_GATE_DISABLE;
> +
> +	if (IS_IVYBRIDGE(dev))
> +		gstate |= GEN6_RCZUNIT_CLOCK_GATE_DISABLE;
> +
> +	I915_WRITE(GEN6_UCGCTL2, gstate);
>
>   	/*
>   	 * According to the spec the following bits should be

Nack.  gen6_init_clock_gating won't get run on Ivybridge...

Re: [PATCH 0/3] Ivy Bridge hard-hang fixes

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 466 bytes --]

On Mon, Feb 6, 2012 at 21:25, Keith Packard <keithp@keithp.com> wrote:

>  Would be nice if the summary lines for these patches was a bit more
> descriptive...
>

Yes, makes sense, I'll update it.


>
> Also, 3/3 has a Rb line from Ken, but I don't see the mail from him with
> that.
>

It is from Message-ID: <4F2C80BC.8060302@whitecape.org>

I'll update patch1 with Ken's comments and resend with better summaries.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 3/3] drm/i915: gen7: work around a system hang on IVB

[Eric Anholt]

[-- Attachment #1.1: Type: text/plain, Size: 1324 bytes --]

On Sun,  5 Feb 2012 20:47:06 -0200, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This adds the workaround for WaCatErrorRejectionIssue which could result
> in a system hang.
> 
> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    4 ++++
>  drivers/gpu/drm/i915/intel_display.c |    5 +++++
>  2 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 92274b1..4f25cd5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3035,6 +3035,10 @@
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
>  
> +/* WaCatErrorRejectionIssue */
> +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> +#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

In the BSpec, this is "SQCM" and they say "9030" not "9030h" like normal,
so it was hard to search for.  Also, I'm not sure what SQINTMOB is
supposed to mean.  The bit is named "Rejection FifoFlush Disable" in the
docs I can find.

I'd like to see the names fixed up so that we can find them again later,
but other than that,

Reviewed-by: Eric Anholt <eric@anholt.net>

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Re: [PATCH 2/3] drm/i915: gen7: add two more IVB workarounds

[Eric Anholt]

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On Sun,  5 Feb 2012 20:47:05 -0200, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This adds two cache-related workarounds for Ivy Bridge which can lead to
> 3D ring hangs and corruptions.

Reviewed-by: Eric Anholt <eric@anholt.net>

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