[PATCH V2 01/14] MIPS: add clkdev.h

All of lore.kernel.org
 help / color / mirror / Atom feed

* [PATCH V2 01/14] MIPS: add clkdev.h
@ 2012-02-23 16:03 John Crispin
  2012-02-23 16:03 ` [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection John Crispin
                   ` (12 more replies)
  0 siblings, 13 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

For clkdev to work on MIPS we need this file

include/linux/clkdev.h:#include <asm/clkdev.h>

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/clkdev.h |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/clkdev.h

diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
new file mode 100644
index 0000000..2624754
--- /dev/null
+++ b/arch/mips/include/asm/clkdev.h
@@ -0,0 +1,25 @@
+/*
+ *  based on arch/arm/include/asm/clkdev.h
+ *
+ *  Copyright (C) 2008 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Helper for the clk API to assist looking up a struct clk.
+ */
+#ifndef __ASM_CLKDEV_H
+#define __ASM_CLKDEV_H
+
+#include <linux/slab.h>
+
+#define __clk_get(clk)	({ 1; })
+#define __clk_put(clk)	do { } while (0)
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+	return kzalloc(size, GFP_KERNEL);
+}
+
+#endif
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 03/14] MIPS: lantiq: convert to clkdev api John Crispin
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

Add additional functions for runtime soc detection. We need these for the
serial driver.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |   16 ++++++++++++++--
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    5 +++++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 1a4b836..fd7f9fd 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -149,8 +149,20 @@ extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
 #define LTQ_EIU_BASE_ADDR	0
 #define LTQ_EBU_PCC_ISTAT	0
 
-#define ltq_is_ar9()	0
-#define ltq_is_vr9()	0
+static inline int ltq_is_ar9(void)
+{
+	return 0;
+}
+
+static inline int ltq_is_vr9(void)
+{
+	return 0;
+}
+
+static inline int ltq_is_falcon(void)
+{
+	return 1;
+}
 
 #endif /* CONFIG_SOC_FALCON */
 #endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 4213926..1b60181 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -186,5 +186,10 @@ static inline int ltq_is_vr9(void)
 	return (ltq_get_soc_type() == SOC_TYPE_VR9);
 }
 
+static inline int ltq_is_falcon(void)
+{
+	return 0;
+}
+
 #endif /* CONFIG_SOC_TYPE_XWAY */
 #endif /* _LTQ_XWAY_H__ */
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 03/14] MIPS: lantiq: convert to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
  2012-02-23 16:03 ` [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 04/14] MIPS: lantiq: convert xway " John Crispin
                   ` (10 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

* Change setup from HAVE_CLK -> HAVE_MACH_CLKDEV/CLKDEV_LOOKUP
* Add clk_activate/clk_deactivate
* Add better error paths to the clk_*() functions
* Change the way our static clocks are referenced

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/Kconfig                          |    3 +-
 arch/mips/include/asm/mach-lantiq/lantiq.h |   20 ++----
 arch/mips/lantiq/clk.c                     |   96 +++++++++++++++------------
 arch/mips/lantiq/clk.h                     |   52 ++++++++++++++-
 arch/mips/lantiq/prom.c                    |    1 -
 5 files changed, 111 insertions(+), 61 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c4c1312..b106c9e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -228,7 +228,8 @@ config LANTIQ
 	select ARCH_REQUIRE_GPIOLIB
 	select SWAP_IO_SPACE
 	select BOOT_RAW
-	select HAVE_CLK
+	select HAVE_MACH_CLKDEV
+	select CLKDEV_LOOKUP
 	select MIPS_MACHINE
 
 config LASAT
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index d90eef3..52f1cdf 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -9,6 +9,7 @@
 #define _LANTIQ_H__
 
 #include <linux/irq.h>
+#include <linux/clk.h>
 #include <linux/ioport.h>
 
 /* generic reg access */
@@ -24,18 +25,6 @@ static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem *r)
 extern unsigned int ltq_get_cpu_ver(void);
 extern unsigned int ltq_get_soc_type(void);
 
-/* clock speeds */
-#define CLOCK_60M	60000000
-#define CLOCK_83M	83333333
-#define CLOCK_100M	100000000
-#define CLOCK_111M	111111111
-#define CLOCK_133M	133333333
-#define CLOCK_167M	166666667
-#define CLOCK_200M	200000000
-#define CLOCK_266M	266666666
-#define CLOCK_333M	333333333
-#define CLOCK_400M	400000000
-
 /* spinlock all ebu i/o */
 extern spinlock_t ebu_lock;
 
@@ -48,6 +37,13 @@ extern void ltq_disable_irq(struct irq_data *data);
 extern void ltq_mask_and_ack_irq(struct irq_data *data);
 extern void ltq_enable_irq(struct irq_data *data);
 
+/* clock handling */
+extern int clk_activate(struct clk *clk);
+extern void clk_deactivate(struct clk *clk);
+extern struct clk *clk_get_cpu(void);
+extern struct clk *clk_get_fpi(void);
+extern struct clk *clk_get_io(void);
+
 /* find out what caused the last cpu reset */
 extern int ltq_reset_cause(void);
 
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 39eef7f..84a201e 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/list.h>
 
@@ -24,33 +25,29 @@
 #include "clk.h"
 #include "prom.h"
 
-struct clk {
-	const char *name;
-	unsigned long rate;
-	unsigned long (*get_rate) (void);
-};
+/* lantiq socs have 3 static clocks */
+static struct clk cpu_clk_generic[3];
 
-static struct clk *cpu_clk;
-static int cpu_clk_cnt;
+void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
+{
+	cpu_clk_generic[0].rate = cpu;
+	cpu_clk_generic[1].rate = fpi;
+	cpu_clk_generic[2].rate = io;
+}
 
-/* lantiq socs have 3 static clocks */
-static struct clk cpu_clk_generic[] = {
-	{
-		.name = "cpu",
-		.get_rate = ltq_get_cpu_hz,
-	}, {
-		.name = "fpi",
-		.get_rate = ltq_get_fpi_hz,
-	}, {
-		.name = "io",
-		.get_rate = ltq_get_io_region_clock,
-	},
-};
-
-void clk_init(void)
+struct clk *clk_get_cpu(void)
+{
+	return &cpu_clk_generic[0];
+}
+
+struct clk *clk_get_fpi(void)
 {
-	cpu_clk = cpu_clk_generic;
-	cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
+	return &cpu_clk_generic[1];
+}
+
+struct clk *clk_get_io(void)
+{
+	return &cpu_clk_generic[2];
 }
 
 static inline int clk_good(struct clk *clk)
@@ -73,36 +70,49 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-struct clk *clk_get(struct device *dev, const char *id)
+int clk_enable(struct clk *clk)
 {
-	int i;
+	if (unlikely(!clk_good(clk)))
+		return -1;
+
+	if (clk->enable)
+		return clk->enable(clk);
 
-	for (i = 0; i < cpu_clk_cnt; i++)
-		if (!strcmp(id, cpu_clk[i].name))
-			return &cpu_clk[i];
-	BUG();
-	return ERR_PTR(-ENOENT);
+	return -1;
 }
-EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_enable);
 
-void clk_put(struct clk *clk)
+void clk_disable(struct clk *clk)
 {
-	/* not used */
+	if (unlikely(!clk_good(clk)))
+		return;
+
+	if (clk->disable)
+		clk->disable(clk);
 }
-EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_disable);
 
-int clk_enable(struct clk *clk)
+int clk_activate(struct clk *clk)
 {
-	/* not used */
-	return 0;
+	if (unlikely(!clk_good(clk)))
+		return -1;
+
+	if (clk->activate)
+		return clk->activate(clk);
+
+	return -1;
 }
-EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_activate);
 
-void clk_disable(struct clk *clk)
+void clk_deactivate(struct clk *clk)
 {
-	/* not used */
+	if (unlikely(!clk_good(clk)))
+		return;
+
+	if (clk->deactivate)
+		clk->deactivate(clk);
 }
-EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_deactivate);
 
 static inline u32 ltq_get_counter_resolution(void)
 {
@@ -126,7 +136,7 @@ void __init plat_time_init(void)
 
 	ltq_soc_init();
 
-	clk = clk_get(0, "cpu");
+	clk = clk_get_cpu();
 	mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
 	write_c0_compare(read_c0_count());
 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
index 3328925..d047768 100644
--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
@@ -9,10 +9,54 @@
 #ifndef _LTQ_CLK_H__
 #define _LTQ_CLK_H__
 
-extern void clk_init(void);
+#include <linux/clkdev.h>
 
-extern unsigned long ltq_get_cpu_hz(void);
-extern unsigned long ltq_get_fpi_hz(void);
-extern unsigned long ltq_get_io_region_clock(void);
+/* clock speeds */
+#define CLOCK_60M	60000000
+#define CLOCK_62_5M	62500000
+#define CLOCK_83M	83333333
+#define CLOCK_83_5M	83500000
+#define CLOCK_98_304M	98304000
+#define CLOCK_100M	100000000
+#define CLOCK_111M	111111111
+#define CLOCK_125M	125000000
+#define CLOCK_133M	133333333
+#define CLOCK_150M	150000000
+#define CLOCK_166M	166666666
+#define CLOCK_167M	166666667
+#define CLOCK_196_608M	196608000
+#define CLOCK_200M	200000000
+#define CLOCK_250M	250000000
+#define CLOCK_266M	266666666
+#define CLOCK_300M	300000000
+#define CLOCK_333M	333333333
+#define CLOCK_393M	393215332
+#define CLOCK_400M	400000000
+#define CLOCK_500M	500000000
+#define CLOCK_600M	600000000
+
+struct clk {
+	struct clk_lookup cl;
+	unsigned long rate;
+	unsigned long (*get_rate) (void);
+	unsigned int module;
+	unsigned int bits;
+	int (*enable) (struct clk *clk);
+	void (*disable) (struct clk *clk);
+	int (*activate) (struct clk *clk);
+	void (*deactivate) (struct clk *clk);
+	void (*reboot) (struct clk *clk);
+};
+
+extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
+					unsigned long io);
+
+extern unsigned long ltq_danube_cpu_hz(void);
+extern unsigned long ltq_danube_fpi_hz(void);
+extern unsigned long ltq_danube_io_region_clock(void);
+
+extern unsigned long ltq_vr9_cpu_hz(void);
+extern unsigned long ltq_vr9_fpi_hz(void);
+extern unsigned long ltq_vr9_io_region_clock(void);
 
 #endif
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index ee63a33..b002bc7 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource);
 void __init prom_init(void)
 {
 	ltq_soc_detect(&soc_info);
-	clk_init();
 	snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 		soc_info.name, soc_info.rev_type);
 	soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 04/14] MIPS: lantiq: convert xway to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
  2012-02-23 16:03 ` [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection John Crispin
  2012-02-23 16:03 ` [PATCH V2 03/14] MIPS: lantiq: convert to clkdev api John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 05/14] MIPS: lantiq: convert falcon " John Crispin
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

Unify xway/ase clock code and add clkdev hooks to sysctrl.c

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   13 --
 arch/mips/lantiq/xway/Makefile                     |    6 +-
 arch/mips/lantiq/xway/clk-ase.c                    |   48 ----
 arch/mips/lantiq/xway/clk-xway.c                   |  223 -------------------
 arch/mips/lantiq/xway/clk.c                        |  227 ++++++++++++++++++++
 arch/mips/lantiq/xway/sysctrl.c                    |  104 ++++++++-
 6 files changed, 325 insertions(+), 296 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
 delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
 create mode 100644 arch/mips/lantiq/xway/clk.c

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 1b60181..2208a9db 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -81,15 +81,6 @@
 #define LTQ_PMU_BASE_ADDR	0x1F102000
 #define LTQ_PMU_SIZE		0x1000
 
-#define PMU_DMA			0x0020
-#define PMU_EPHY		0x0080
-#define PMU_USB			0x8041
-#define PMU_LED			0x0800
-#define PMU_GPT			0x1000
-#define PMU_PPE			0x2000
-#define PMU_FPI			0x4000
-#define PMU_SWITCH		0x10000000
-
 /* ETOP - ethernet */
 #define LTQ_ETOP_BASE_ADDR	0x1E180000
 #define LTQ_ETOP_SIZE		0x40000
@@ -167,10 +158,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r)
 	ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r);
 }
 
-extern void ltq_pmu_enable(unsigned int module);
-extern void ltq_pmu_disable(unsigned int module);
-extern void ltq_cgu_enable(unsigned int clk);
-
 static inline int ltq_is_ase(void)
 {
 	return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6678402..4dcb96f 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,7 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
 
-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+obj-$(CONFIG_SOC_XWAY) += prom-xway.o
+obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
 
 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
deleted file mode 100644
index 6522583..0000000
--- a/arch/mips/lantiq/xway/clk-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-/* cgu registers */
-#define LTQ_CGU_SYS	0x0010
-
-unsigned int ltq_get_io_region_clock(void)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
-	if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
-		return CLOCK_266M;
-	else
-		return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
deleted file mode 100644
index 696b1a3..0000000
--- a/arch/mips/lantiq/xway/clk-xway.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-static unsigned int ltq_ram_clocks[] = {
-	CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
-
-#define BASIC_FREQUENCY_1	35328000
-#define BASIC_FREQUENCY_2	36000000
-#define BASIS_REQUENCY_USB	12000000
-
-#define GET_BITS(x, msb, lsb) \
-	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-
-#define LTQ_CGU_PLL0_CFG	0x0004
-#define LTQ_CGU_PLL1_CFG	0x0008
-#define LTQ_CGU_PLL2_CFG	0x000C
-#define LTQ_CGU_SYS		0x0010
-#define LTQ_CGU_UPDATE		0x0014
-#define LTQ_CGU_IF_CLK		0x0018
-#define LTQ_CGU_OSC_CON		0x001C
-#define LTQ_CGU_SMD		0x0020
-#define LTQ_CGU_CT1SR		0x0028
-#define LTQ_CGU_CT2SR		0x002C
-#define LTQ_CGU_PCMCR		0x0030
-#define LTQ_CGU_PCI_CR		0x0034
-#define LTQ_CGU_PD_PC		0x0038
-#define LTQ_CGU_FMR		0x003C
-
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE	\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
-#define CGU_PLL0_BYPASS			\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
-#define CGU_PLL0_CFG_DSMSEL		\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN		\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
-#define CGU_PLL1_SRC			\
-	(ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE	\
-	(ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
-#define CGU_SYS_FPI_SEL			(1 << 6)
-#define CGU_SYS_DDR_SEL			0x3
-#define CGU_PLL0_SRC			(1 << 29)
-
-#define CGU_PLL0_CFG_PLLK	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
-#define CGU_PLL0_CFG_PLLN	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
-#define CGU_PLL0_CFG_PLLM	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
-#define CGU_PLL2_SRC		GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
-#define CGU_PLL2_CFG_INPUT_DIV	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
-
-static unsigned int ltq_get_pll0_fdiv(void);
-
-static inline unsigned int get_input_clock(int pll)
-{
-	switch (pll) {
-	case 0:
-		if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
-			return BASIS_REQUENCY_USB;
-		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			return BASIC_FREQUENCY_1;
-		else
-			return BASIC_FREQUENCY_2;
-	case 1:
-		if (CGU_PLL1_SRC)
-			return BASIS_REQUENCY_USB;
-		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			return BASIC_FREQUENCY_1;
-		else
-			return BASIC_FREQUENCY_2;
-	case 2:
-		switch (CGU_PLL2_SRC) {
-		case 0:
-			return ltq_get_pll0_fdiv();
-		case 1:
-			return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
-				BASIC_FREQUENCY_1 :
-				BASIC_FREQUENCY_2;
-		case 2:
-			return BASIS_REQUENCY_USB;
-		}
-	default:
-		return 0;
-	}
-}
-
-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
-{
-	u64 res, clock = get_input_clock(pll);
-
-	res = num * clock;
-	do_div(res, den);
-	return res;
-}
-
-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = ((N + 1) << 10) + K;
-	unsigned int den = (M + 1) << 10;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = ((N + 1) << 11) + K + 512;
-	unsigned int den = (M + 1) << 11;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = K >= 512 ?
-		((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
-	unsigned int den = (M + 1) << 12;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
-	unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
-{
-	if (!dsmsel)
-		return mash_dsm(pll, M, N, K);
-	else if (!phase_div_en)
-		return mash_dsm(pll, M, N, K);
-	else
-		return ssff_dsm_2(pll, M, N, K);
-}
-
-static inline unsigned int ltq_get_pll0_fosc(void)
-{
-	if (CGU_PLL0_BYPASS)
-		return get_input_clock(0);
-	else
-		return !CGU_PLL0_CFG_FRAC_EN
-			? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
-				CGU_PLL0_CFG_DSMSEL,
-				CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
-				CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
-				CGU_PLL0_PHASE_DIVIDER_ENABLE);
-}
-
-static unsigned int ltq_get_pll0_fdiv(void)
-{
-	unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
-
-	return (ltq_get_pll0_fosc() + (div >> 1)) / div;
-}
-
-unsigned int ltq_get_io_region_clock(void)
-{
-	unsigned int ret = ltq_get_pll0_fosc();
-
-	switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
-	default:
-	case 0:
-		return (ret + 1) / 2;
-	case 1:
-		return (ret * 2 + 2) / 5;
-	case 2:
-		return (ret + 1) / 3;
-	case 3:
-		return (ret + 2) / 4;
-	}
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
-	unsigned int ret = ltq_get_io_region_clock();
-
-	if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
-		ret >>= 1;
-	return ret;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
-	switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
-	case 0:
-		return CLOCK_333M;
-	case 4:
-		return DDR_HZ;
-	case 8:
-		return DDR_HZ << 1;
-	default:
-		return DDR_HZ >> 1;
-	}
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
-	unsigned int ddr_clock = DDR_HZ;
-
-	if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
-		return ddr_clock >> 1;
-	return ddr_clock;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
new file mode 100644
index 0000000..f3b50fc
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk.c
@@ -0,0 +1,227 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq_soc.h>
+
+#include "../clk.h"
+
+static unsigned int ltq_ram_clocks[] = {
+	CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
+
+#define BASIC_FREQUENCY_1	35328000
+#define BASIC_FREQUENCY_2	36000000
+#define BASIS_REQUENCY_USB	12000000
+
+#define GET_BITS(x, msb, lsb) \
+	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+
+/* legacy xway clock */
+#define LTQ_CGU_PLL0_CFG	0x0004
+#define LTQ_CGU_PLL1_CFG	0x0008
+#define LTQ_CGU_PLL2_CFG	0x000C
+#define LTQ_CGU_SYS		0x0010
+#define LTQ_CGU_UPDATE		0x0014
+#define LTQ_CGU_IF_CLK		0x0018
+#define LTQ_CGU_OSC_CON		0x001C
+#define LTQ_CGU_SMD		0x0020
+#define LTQ_CGU_CT1SR		0x0028
+#define LTQ_CGU_CT2SR		0x002C
+#define LTQ_CGU_PCMCR		0x0030
+#define LTQ_CGU_PCI_CR		0x0034
+#define LTQ_CGU_PD_PC		0x0038
+#define LTQ_CGU_FMR		0x003C
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE	\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS			\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL		\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN		\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC			\
+	(ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE	\
+	(ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_SYS_FPI_SEL			(1 << 6)
+#define CGU_SYS_DDR_SEL			0x3
+#define CGU_PLL0_SRC			(1 << 29)
+
+#define CGU_PLL0_CFG_PLLK	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
+#define CGU_PLL0_CFG_PLLN	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
+#define CGU_PLL0_CFG_PLLM	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
+#define CGU_PLL2_SRC		GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
+#define CGU_PLL2_CFG_INPUT_DIV	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
+
+/* vr9 clock */
+#define LTQ_CGU_SYS_VR9	0x0c
+#define LTQ_CGU_IF_CLK_VR9	0x24
+
+
+static unsigned int ltq_get_pll0_fdiv(void);
+
+static inline unsigned int get_input_clock(int pll)
+{
+	switch (pll) {
+	case 0:
+		if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+			return BASIS_REQUENCY_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_FREQUENCY_1;
+		else
+			return BASIC_FREQUENCY_2;
+	case 1:
+		if (CGU_PLL1_SRC)
+			return BASIS_REQUENCY_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_FREQUENCY_1;
+		else
+			return BASIC_FREQUENCY_2;
+	case 2:
+		switch (CGU_PLL2_SRC) {
+		case 0:
+			return ltq_get_pll0_fdiv();
+		case 1:
+			return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+				BASIC_FREQUENCY_1 :
+				BASIC_FREQUENCY_2;
+		case 2:
+			return BASIS_REQUENCY_USB;
+		}
+	default:
+		return 0;
+	}
+}
+
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
+{
+	u64 res, clock = get_input_clock(pll);
+
+	res = num * clock;
+	do_div(res, den);
+	return res;
+}
+
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 10) + K;
+	unsigned int den = (M + 1) << 10;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 11) + K + 512;
+	unsigned int den = (M + 1) << 11;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = K >= 512 ?
+		((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
+	unsigned int den = (M + 1) << 12;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
+{
+	if (!dsmsel)
+		return mash_dsm(pll, M, N, K);
+	else if (!phase_div_en)
+		return mash_dsm(pll, M, N, K);
+	else
+		return ssff_dsm_2(pll, M, N, K);
+}
+
+static inline unsigned int ltq_get_pll0_fosc(void)
+{
+	if (CGU_PLL0_BYPASS)
+		return get_input_clock(0);
+	else
+		return !CGU_PLL0_CFG_FRAC_EN
+			? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
+				CGU_PLL0_CFG_DSMSEL,
+				CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
+				CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
+				CGU_PLL0_PHASE_DIVIDER_ENABLE);
+}
+
+static unsigned int ltq_get_pll0_fdiv(void)
+{
+	unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+
+	return (ltq_get_pll0_fosc() + (div >> 1)) / div;
+}
+
+unsigned long ltq_danube_io_region_clock(void)
+{
+	unsigned int ret = ltq_get_pll0_fosc();
+
+	switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
+	default:
+	case 0:
+		return (ret + 1) / 2;
+	case 1:
+		return (ret * 2 + 2) / 5;
+	case 2:
+		return (ret + 1) / 3;
+	case 3:
+		return (ret + 2) / 4;
+	}
+}
+
+unsigned long ltq_danube_fpi_bus_clock(int fpi)
+{
+	unsigned long ret = ltq_danube_io_region_clock();
+
+	if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
+		ret >>= 1;
+	return ret;
+}
+
+unsigned long ltq_danube_cpu_hz(void)
+{
+	switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
+	case 0:
+		return CLOCK_333M;
+	case 4:
+		return DDR_HZ;
+	case 8:
+		return DDR_HZ << 1;
+	default:
+		return DDR_HZ >> 1;
+	}
+}
+
+unsigned long ltq_danube_fpi_hz(void)
+{
+	unsigned long ddr_clock = DDR_HZ;
+
+	if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
+		return ddr_clock >> 1;
+	return ddr_clock;
+}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 38c122f..22d076e 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -8,17 +8,48 @@
 
 #include <linux/ioport.h>
 #include <linux/export.h>
+#include <linux/clkdev.h>
 
 #include <lantiq_soc.h>
 
+#include "../clk.h"
 #include "../devices.h"
 
 /* clock control register */
 #define LTQ_CGU_IFCCR	0x0018
+/* system clock register */
+#define LTQ_CGU_SYS     0x0010
 
 /* the enable / disable registers */
 #define LTQ_PMU_PWDCR	0x1C
 #define LTQ_PMU_PWDSR	0x20
+#define LTQ_PMU_PWDCR1	0x24
+#define LTQ_PMU_PWDSR1	0x28
+
+#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
+#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
+
+/* CGU - clock generation unit */
+#define CGU_EPHY		0x10
+
+/* PMU - power management unit */
+#define PMU_DMA			0x0020
+#define PMU_SPI			0x0100
+#define PMU_EPHY		0x0080
+#define PMU_USB			0x8041
+#define PMU_STP			0x0800
+#define PMU_GPT			0x1000
+#define PMU_PPE			0x2000
+#define PMU_FPI			0x4000
+#define PMU_SWITCH		0x10000000
+#define PMU_AHBS		0x2000
+#define PMU_AHBM		0x8000
+#define PMU_PCIE_CLK            0x80000000
+
+#define PMU1_PCIE_PHY		0x0001
+#define PMU1_PCIE_CTL		0x0002
+#define PMU1_PCIE_MSI		0x0020
+#define PMU1_PCIE_PDI		0x0010
 
 #define ltq_pmu_w32(x, y)	ltq_w32((x), ltq_pmu_membase + (y))
 #define ltq_pmu_r32(x)		ltq_r32(ltq_pmu_membase + (x))
@@ -36,28 +67,64 @@ void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 static void __iomem *ltq_pmu_membase;
 
-void ltq_cgu_enable(unsigned int clk)
+static int ltq_cgu_enable(struct clk *clk)
 {
-	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
+	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
+	return 0;
 }
 
-void ltq_pmu_enable(unsigned int module)
+static void ltq_cgu_disable(struct clk *clk)
+{
+	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
+}
+
+static int ltq_pmu_enable(struct clk *clk)
 {
 	int err = 1000000;
 
-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
-	do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
+	ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits,
+		PWDCR(clk->module));
+	do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits));
 
 	if (!err)
 		panic("activating PMU module failed!");
+
+	return 0;
 }
-EXPORT_SYMBOL(ltq_pmu_enable);
 
-void ltq_pmu_disable(unsigned int module)
+static void ltq_pmu_disable(struct clk *clk)
 {
-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
+	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
+}
+
+static inline void clkdev_add_pmu(const char *dev, const char *con,
+	unsigned int module, unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.con_id = con;
+	clk->cl.clk = clk;
+	clk->enable = ltq_pmu_enable;
+	clk->disable = ltq_pmu_disable;
+	clk->module = module;
+	clk->bits = bits;
+	clkdev_add(&clk->cl);
+}
+
+static inline void clkdev_add_cgu(const char *dev, const char *con,
+					unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.con_id = con;
+	clk->cl.clk = clk;
+	clk->enable = ltq_cgu_enable;
+	clk->disable = ltq_cgu_disable;
+	clk->bits = bits;
+	clkdev_add(&clk->cl);
 }
-EXPORT_SYMBOL(ltq_pmu_disable);
 
 void __init ltq_soc_init(void)
 {
@@ -75,4 +142,23 @@ void __init ltq_soc_init(void)
 
 	/* make sure to unprotect the memory region where flash is located */
 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+
+	/* add our clocks */
+	clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
+	clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
+	clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
+	clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
+	if (ltq_is_ase()) {
+		if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
+			clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
+		else
+			clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
+		clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
+		clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
+	} else {
+		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
+					ltq_danube_io_region_clock());
+		if (ltq_is_ar9())
+			clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
+	}
 }
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 05/14] MIPS: lantiq: convert falcon to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (2 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 04/14] MIPS: lantiq: convert xway " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 06/14] MIPS: lantiq: convert dma driver " John Crispin
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

Unify sysctrl/clock code and add clkdev hooks to sysctrl.c

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |    8 +-
 arch/mips/lantiq/falcon/Makefile                   |    2 +-
 arch/mips/lantiq/falcon/clk.c                      |   44 -------
 arch/mips/lantiq/falcon/sysctrl.c                  |  129 ++++++++++++--------
 4 files changed, 80 insertions(+), 103 deletions(-)
 delete mode 100644 arch/mips/lantiq/falcon/clk.c

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index fd7f9fd..06f4c8f 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -95,6 +95,7 @@
 
 /* Activation Status Register */
 #define ACTS_ASC1_ACT	0x00000800
+#define ACTS_I2C_ACT	0x00004000
 #define ACTS_P0		0x00010000
 #define ACTS_P1		0x00010000
 #define ACTS_P2		0x00020000
@@ -106,13 +107,6 @@
 #define ACTS_PADCTRL3	0x00200000
 #define ACTS_PADCTRL4	0x00400000
 
-extern void ltq_sysctl_activate(int module, unsigned int mask);
-extern void ltq_sysctl_deactivate(int module, unsigned int mask);
-extern void ltq_sysctl_clken(int module, unsigned int mask);
-extern void ltq_sysctl_clkdis(int module, unsigned int mask);
-extern void ltq_sysctl_reboot(int module, unsigned int mask);
-extern int ltq_gpe_is_activated(unsigned int mask);
-
 /* global register ranges */
 extern void __iomem *ltq_ebu_membase;
 extern void __iomem *ltq_sys1_membase;
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index 56b22eb..3634154 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1,2 +1,2 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-y := prom.o reset.o sysctrl.o devices.o gpio.o
 obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
deleted file mode 100644
index afe1b52..0000000
--- a/arch/mips/lantiq/falcon/clk.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/ioport.h>
-#include <linux/export.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-
-/* CPU0 Clock Control Register */
-#define LTQ_SYS1_CPU0CC		0x0040
-/* clock divider bit */
-#define LTQ_CPU0CC_CPUDIV	0x0001
-
-unsigned int
-ltq_get_io_region_clock(void)
-{
-	return CLOCK_200M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int
-ltq_get_cpu_hz(void)
-{
-	if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
-		return CLOCK_200M;
-	else
-		return CLOCK_400M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int
-ltq_get_fpi_hz(void)
-{
-	return CLOCK_100M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 905a142..900f0e5 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -9,11 +9,13 @@
 
 #include <linux/ioport.h>
 #include <linux/export.h>
+#include <linux/clkdev.h>
 #include <asm/delay.h>
 
 #include <lantiq_soc.h>
 
 #include "devices.h"
+#include "../clk.h"
 
 /* infrastructure control register */
 #define SYS1_INFRAC		0x00bc
@@ -38,6 +40,10 @@
 #define LTQ_SYSCTL_DEACT	0x0028
 /* reboot Register */
 #define LTQ_SYSCTL_RBT		0x002c
+/* CPU0 Clock Control Register */
+#define LTQ_SYS1_CPU0CC         0x0040
+/* clock divider bit */
+#define LTQ_CPU0CC_CPUDIV       0x0001
 
 static struct resource ltq_sysctl_res[] = {
 	MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
@@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase;
 #define ltq_status_r32(x)	ltq_r32(ltq_status_membase + (x))
 
 static inline void
-ltq_sysctl_wait(int module, unsigned int mask,
+ltq_sysctl_wait(struct clk *clk,
 		unsigned int test, unsigned int reg)
 {
 	int err = 1000000;
 
-	do {} while (--err && ((ltq_reg_r32(module, reg)
-					& mask) != test));
+	do {} while (--err && ((ltq_reg_r32(clk->module, reg)
+					& clk->bits) != test));
 	if (!err)
-		pr_err("module de/activation failed %d %08X %08X\n",
-							module, mask, test);
+		pr_err("module de/activation failed %d %08X %08X %08X\n",
+				clk->module, clk->bits, test,
+				ltq_reg_r32(clk->module, reg) & clk->bits);
 }
 
-void
-ltq_sysctl_activate(int module, unsigned int mask)
+static int
+ltq_sysctl_activate(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
+	return 0;
 }
-EXPORT_SYMBOL(ltq_sysctl_activate);
 
-void
-ltq_sysctl_deactivate(int module, unsigned int mask)
+static void
+ltq_sysctl_deactivate(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
-	ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT);
+	ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS);
 }
-EXPORT_SYMBOL(ltq_sysctl_deactivate);
 
-void
-ltq_sysctl_clken(int module, unsigned int mask)
+static int
+ltq_sysctl_clken(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS);
+	return 0;
 }
-EXPORT_SYMBOL(ltq_sysctl_clken);
 
-void
-ltq_sysctl_clkdis(int module, unsigned int mask)
+static void
+ltq_sysctl_clkdis(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
-	ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+	ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS);
 }
-EXPORT_SYMBOL(ltq_sysctl_clkdis);
 
-void
-ltq_sysctl_reboot(int module, unsigned int mask)
+static void
+ltq_sysctl_reboot(struct clk *clk)
 {
 	unsigned int act;
-
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
-	if ((~act & mask) != 0)
-		ltq_sysctl_activate(module, ~act & mask);
-	ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+	unsigned int bits;
+
+	act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT);
+	bits = ~act & clk->bits;
+	if (bits != 0) {
+		ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN);
+		ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT);
+		ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS);
+	}
+	ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
 }
-EXPORT_SYMBOL(ltq_sysctl_reboot);
 
 /* enable the ONU core */
 static void
@@ -167,6 +161,24 @@ ltq_gpe_enable(void)
 	udelay(1);
 }
 
+static inline void
+clkdev_add_sys(const char *dev, unsigned int module,
+				unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.con_id = NULL;
+	clk->cl.clk = clk;
+	clk->module = module;
+	clk->activate = ltq_sysctl_activate;
+	clk->deactivate = ltq_sysctl_deactivate;
+	clk->enable = ltq_sysctl_clken;
+	clk->disable = ltq_sysctl_clkdis;
+	clk->reboot = ltq_sysctl_reboot;
+	clkdev_add(&clk->cl);
+}
+
 void __init
 ltq_soc_init(void)
 {
@@ -180,4 +192,19 @@ ltq_soc_init(void)
 	ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
 
 	ltq_gpe_enable();
+
+	/* get our 3 static rates for cpu, fpi and io clocks */
+	if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
+		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
+	else
+		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
+
+	/* add our clock domains */
+	clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0);
+	clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
+	clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2);
+	clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3);
+	clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4);
+	clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT);
+	clkdev_add_sys("falcon_i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
 }
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 06/14] MIPS: lantiq: convert dma driver to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (3 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 05/14] MIPS: lantiq: convert falcon " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp " John Crispin
                   ` (7 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/dma.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 6cf883b..ce86529 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/export.h>
+#include <linux/clk.h>
 
 #include <lantiq_soc.h>
 #include <xway_dma.h>
@@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port);
 int __init
 ltq_dma_init(void)
 {
+	struct clk *clk;
 	int i;
 
 	/* remap dma register range */
@@ -224,7 +226,9 @@ ltq_dma_init(void)
 		panic("Failed to remap dma memory");
 
 	/* power up and reset the dma engine */
-	ltq_pmu_enable(PMU_DMA);
+	clk = clk_get_sys("ltq_dma", NULL);
+	WARN_ON(!clk);
+	clk_enable(clk);
 	ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
 
 	/* disable all interrupts */
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp driver to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (4 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 06/14] MIPS: lantiq: convert dma driver " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-24 10:46   ` Sergei Shtylyov
  2012-02-23 16:03 ` [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio " John Crispin
                   ` (6 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/gpio_stp.c |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index e6b4809..8e07958 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -15,6 +15,7 @@
 #include <linux/mutex.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
 
 #include <lantiq_soc.h>
 
@@ -78,8 +79,10 @@ static struct gpio_chip ltq_stp_chip = {
 	.owner = THIS_MODULE,
 };
 
-static int ltq_stp_hw_init(void)
+static int ltq_stp_hw_init(struct device *dev)
 {
+	struct clk *clk;
+
 	/* sane defaults */
 	ltq_stp_w32(0, LTQ_STP_AR);
 	ltq_stp_w32(0, LTQ_STP_CPU0);
@@ -105,7 +108,9 @@ static int ltq_stp_hw_init(void)
 	 */
 	ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
 
-	ltq_pmu_enable(PMU_LED);
+	clk = clk_get(dev, NULL);
+	WARN_ON(!clk);
+	clk_enable(clk);
 	return 0;
 }
 
@@ -138,7 +143,7 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
 	}
 	ret = gpiochip_add(&ltq_stp_chip);
 	if (!ret)
-		ret = ltq_stp_hw_init();
+		ret = ltq_stp_hw_init(&pdev->dev);
 
 	return ret;
 }
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp driver to clkdev api
  2012-02-23 16:03 ` [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp " John Crispin
@ 2012-02-24 10:46   ` Sergei Shtylyov
  0 siblings, 0 replies; 21+ messages in thread
From: Sergei Shtylyov @ 2012-02-24 10:46 UTC (permalink / raw)
  To: John Crispin; +Cc: Ralf Baechle, linux-mips

Hello.

On 23-02-2012 20:03, John Crispin wrote:

> Update from old pmu_{dis,en}able() to ckldev api.

> Signed-off-by: John Crispin<blogic@openwrt.org>
[...]

> diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
> index e6b4809..8e07958 100644
> --- a/arch/mips/lantiq/xway/gpio_stp.c
> +++ b/arch/mips/lantiq/xway/gpio_stp.c
[...]
> @@ -105,7 +108,9 @@ static int ltq_stp_hw_init(void)
>   	 */
>   	ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
>
> -	ltq_pmu_enable(PMU_LED);
> +	clk = clk_get(dev, NULL);
> +	WARN_ON(!clk);

    clk_get() returns error, not NULL.

WBR, Sergei

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (5 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-24 10:45   ` Sergei Shtylyov
  2012-02-23 16:03 ` [PATCH V2 09/14] SERIAL: MIPS: lantiq: convert serial driver " John Crispin
                   ` (5 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

The falcon gpio clocks used to be enabled when registering the platform device.
Move this code into the driver and use clkdev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/falcon/devices.c |    5 -----
 arch/mips/lantiq/falcon/gpio.c    |    9 +++++++++
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index 4f47b44..6cd7a88 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -111,9 +111,6 @@ falcon_register_gpio(void)
 		falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
 	platform_device_register_simple("falcon_gpio", 2,
 		falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
-	ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
-	ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
-		ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
 }
 
 void __init
@@ -123,6 +120,4 @@ falcon_register_gpio_extra(void)
 		falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
 	platform_device_register_simple("falcon_gpio", 4,
 		falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
-	ltq_sysctl_activate(SYSCTL_SYS1,
-		ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
 }
diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
index b7611d7..89c9896 100644
--- a/arch/mips/lantiq/falcon/gpio.c
+++ b/arch/mips/lantiq/falcon/gpio.c
@@ -71,6 +71,7 @@ struct falcon_gpio_port {
 	void __iomem *port;
 	unsigned int irq_base;
 	unsigned int chained_irq;
+	struct clk *clk;
 };
 
 static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
@@ -332,6 +333,14 @@ falcon_gpio_probe(struct platform_device *pdev)
 		goto err;
 	}
 
+	gpio_port->clk = clk_get(&pdev->dev, NULL);
+	if (!gpio_port->clk) {
+		dev_err(&pdev->dev, "Could not get clock\n");
+		ret = -ENOENT;
+		goto err;
+	}
+	clk_enable(gpio_port->clk);
+
 	if (irq > 0) {
 		/* irq_chip support */
 		gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio to clkdev api
  2012-02-23 16:03 ` [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio " John Crispin
@ 2012-02-24 10:45   ` Sergei Shtylyov
  0 siblings, 0 replies; 21+ messages in thread
From: Sergei Shtylyov @ 2012-02-24 10:45 UTC (permalink / raw)
  To: John Crispin; +Cc: Ralf Baechle, linux-mips

Hello.

On 23-02-2012 20:03, John Crispin wrote:

> The falcon gpio clocks used to be enabled when registering the platform device.
> Move this code into the driver and use clkdev api.

> Signed-off-by: John Crispin<blogic@openwrt.org>
[...]

> diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
> index b7611d7..89c9896 100644
> --- a/arch/mips/lantiq/falcon/gpio.c
> +++ b/arch/mips/lantiq/falcon/gpio.c
[...]
> @@ -332,6 +333,14 @@ falcon_gpio_probe(struct platform_device *pdev)
>   		goto err;
>   	}
>
> +	gpio_port->clk = clk_get(&pdev->dev, NULL);
> +	if (!gpio_port->clk) {

    clk_get() returns error, not NULL. So you should use IS_ERR(gpio_port->clk).

> +		dev_err(&pdev->dev, "Could not get clock\n");
> +		ret = -ENOENT;

	ret = PTR_ERR(gpio_port->clk);

WBR, Sergei

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V2 09/14] SERIAL: MIPS: lantiq: convert serial driver to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (6 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart " John Crispin
                   ` (4 subsequent siblings)
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin, linux-serial

Reference the FPI clock via its new access function.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-serial@vger.kernel.org
---
 drivers/tty/serial/lantiq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 96c1cac..99fb70f 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev)
 	if (lqasc_port[pdev->id] != NULL)
 		return -EBUSY;
 
-	clk = clk_get(&pdev->dev, "fpi");
+	clk = clk_get_fpi();
 	if (IS_ERR(clk)) {
 		pr_err("failed to get fpi clk\n");
 		return -ENOENT;
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (7 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 09/14] SERIAL: MIPS: lantiq: convert serial driver " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-24 10:53   ` Sergei Shtylyov
  2012-02-23 16:03 ` [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver " John Crispin
                   ` (3 subsequent siblings)
  12 siblings, 1 reply; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

On Falcon SoCs we have a secondary serial port that can be used to help
debug the voice core. For the port to work several clocking bits need to
be activated. We convert the code to clkdev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/falcon/prom.c |   11 +----------
 drivers/tty/serial/lantiq.c    |   23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
index b50d6f9..2a4eea17 100644
--- a/arch/mips/lantiq/falcon/prom.c
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -27,9 +27,6 @@
 #define TYPE_SHIFT	26
 #define TYPE_MASK	0x3C000000
 
-#define MUXC_SIF_RX_PIN		112
-#define MUXC_SIF_TX_PIN		113
-
 /* this parameter allows us enable/disable asc1 via commandline */
 static int register_asc1;
 static int __init
@@ -46,14 +43,8 @@ ltq_soc_setup(void)
 	ltq_register_asc(0);
 	ltq_register_wdt();
 	falcon_register_gpio();
-	if (register_asc1) {
+	if (register_asc1)
 		ltq_register_asc(1);
-		if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
-			pr_err("failed to request asc1-rx");
-		if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
-			pr_err("failed to request asc1-tx");
-		ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
-	}
 }
 
 void __init
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 99fb70f..cf88afd 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -107,6 +107,9 @@
 #define ASCFSTAT_TXFREEMASK	0x3F000000
 #define ASCFSTAT_TXFREEOFF	24
 
+#define MUXC_SIF_RX_PIN         112
+#define MUXC_SIF_TX_PIN         113
+
 static void lqasc_tx_chars(struct uart_port *port);
 static struct ltq_uart_port *lqasc_port[MAXPORTS];
 static struct uart_driver lqasc_reg;
@@ -114,6 +117,7 @@ static DEFINE_SPINLOCK(ltq_asc_lock);
 
 struct ltq_uart_port {
 	struct uart_port	port;
+	struct clk		*fpiclk;
 	struct clk		*clk;
 	unsigned int		tx_irq;
 	unsigned int		rx_irq;
@@ -316,7 +320,7 @@ lqasc_startup(struct uart_port *port)
 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 	int retval;
 
-	port->uartclk = clk_get_rate(ltq_port->clk);
+	port->uartclk = clk_get_rate(ltq_port->fpiclk);
 
 	ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
 		port->membase + LTQ_ASC_CLC);
@@ -529,6 +533,19 @@ lqasc_request_port(struct uart_port *port)
 		if (port->membase == NULL)
 			return -ENOMEM;
 	}
+
+	if (ltq_is_falcon() && (port->line == 1)) {
+		struct ltq_uart_port *ltq_port = lqasc_port[pdev->id];
+		if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN,
+				3, 0, "asc1-rx") ||
+			ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN,
+				3, 1, "asc1-tx"))
+			return -EBUSY;
+		ltq_port->clk = clk_get(&pdev->dev, NULL);
+		if (!ltq_port->clk)
+			return -ENOENT;
+		clk_enable(ltq_port->clk);
+	}
 	return 0;
 }
 
@@ -630,7 +647,7 @@ lqasc_console_setup(struct console *co, char *options)
 
 	port = &ltq_port->port;
 
-	port->uartclk = clk_get_rate(ltq_port->clk);
+	port->uartclk = clk_get_rate(ltq_port->fpiclk);
 
 	if (options)
 		uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -715,7 +732,7 @@ lqasc_probe(struct platform_device *pdev)
 	port->irq	= tx_irq; /* unused, just to be backward-compatibe */
 	port->mapbase	= mmres->start;
 
-	ltq_port->clk	= clk;
+	ltq_port->fpiclk = clk;
 
 	ltq_port->tx_irq = tx_irq;
 	ltq_port->rx_irq = rx_irq;
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart to clkdev api
  2012-02-23 16:03 ` [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart " John Crispin
@ 2012-02-24 10:53   ` Sergei Shtylyov
  0 siblings, 0 replies; 21+ messages in thread
From: Sergei Shtylyov @ 2012-02-24 10:53 UTC (permalink / raw)
  To: John Crispin; +Cc: Ralf Baechle, linux-mips

Hello.

On 23-02-2012 20:03, John Crispin wrote:

> On Falcon SoCs we have a secondary serial port that can be used to help
> debug the voice core. For the port to work several clocking bits need to
> be activated. We convert the code to clkdev api.

    You also convert to new ltq_gpio_request() here. I don't think you should 
mix these two things up in one patch.

> Signed-off-by: John Crispin<blogic@openwrt.org>
[...]

> diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
> index 99fb70f..cf88afd 100644
> --- a/drivers/tty/serial/lantiq.c
> +++ b/drivers/tty/serial/lantiq.c
[...]
> @@ -529,6 +533,19 @@ lqasc_request_port(struct uart_port *port)
>   		if (port->membase == NULL)
>   			return -ENOMEM;
>   	}
> +
> +	if (ltq_is_falcon()&&  (port->line == 1)) {
> +		struct ltq_uart_port *ltq_port = lqasc_port[pdev->id];
> +		if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN,
> +				3, 0, "asc1-rx") ||
> +			ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN,
> +				3, 1, "asc1-tx"))
> +			return -EBUSY;
> +		ltq_port->clk = clk_get(&pdev->dev, NULL);
> +		if (!ltq_port->clk)

    clk_get() returns error code, not NULL. Use IS_ERR() and PTR_ERR().

WBR, Sergei

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (8 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-24  8:28   ` David Miller
  2012-02-24 10:55   ` Sergei Shtylyov
  2012-02-23 16:03 ` [PATCH V2 12/14] WDT: MIPS: lantiq: convert watchdog " John Crispin
                   ` (2 subsequent siblings)
  12 siblings, 2 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin, netdev

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: netdev@vger.kernel.org
---
 drivers/net/ethernet/lantiq_etop.c |   47 ++++++++++++++++++++++++++++++-----
 1 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index e5ec8b1..6b2e4b4 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -36,6 +36,7 @@
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/module.h>
+#include <linux/clk.h>
 
 #include <asm/checksum.h>
 
@@ -148,6 +149,11 @@ struct ltq_etop_priv {
 	int tx_free[MAX_DMA_CHAN >> 1];
 
 	spinlock_t lock;
+
+	struct clk *clk_ppe;
+	struct clk *clk_switch;
+	struct clk *clk_ephy;
+	struct clk *clk_ephycgu;
 };
 
 static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
@@ -281,16 +287,27 @@ ltq_etop_hw_exit(struct net_device *dev)
 	struct ltq_etop_priv *priv = netdev_priv(dev);
 	int i;
 
-	ltq_pmu_disable(PMU_PPE);
+	clk_disable(priv->clk_ppe);
+
+	if (ltq_has_gbit())
+		clk_disable(priv->clk_switch);
+
+	if (ltq_is_ase()) {
+		clk_disable(priv->clk_ephy);
+		clk_disable(priv->clk_ephycgu);
+	}
+
 	for (i = 0; i < MAX_DMA_CHAN; i++)
 		if (IS_TX(i) || IS_RX(i))
 			ltq_etop_free_channel(dev, &priv->ch[i]);
 }
 
 static void
-ltq_etop_gbit_init(void)
+ltq_etop_gbit_init(struct net_device *dev)
 {
-	ltq_pmu_enable(PMU_SWITCH);
+	struct ltq_etop_priv *priv = netdev_priv(dev);
+
+	clk_enable(priv->clk_switch);
 
 	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 	/** Disable MDIO auto polling mode */
@@ -313,10 +330,10 @@ ltq_etop_hw_init(struct net_device *dev)
 	int err = 0;
 	int i;
 
-	ltq_pmu_enable(PMU_PPE);
+	clk_enable(priv->clk_ppe);
 
 	if (ltq_has_gbit()) {
-		ltq_etop_gbit_init();
+		ltq_etop_gbit_init(dev);
 		/* force the etops link to the gbit to MII */
 		mii_mode = PHY_INTERFACE_MODE_MII;
 	}
@@ -334,11 +351,11 @@ ltq_etop_hw_init(struct net_device *dev)
 
 	default:
 		if (ltq_is_ase()) {
-			ltq_pmu_enable(PMU_EPHY);
+			clk_enable(priv->clk_ephy);
 			/* disable external MII */
 			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 			/* enable clock for internal PHY */
-			ltq_cgu_enable(CGU_EPHY);
+			clk_enable(priv->clk_ephycgu);
 			/* we need to write this magic to the internal phy to
 			   make it work */
 			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
@@ -886,6 +903,22 @@ ltq_etop_probe(struct platform_device *pdev)
 	priv->pdev = pdev;
 	priv->pldata = dev_get_platdata(&pdev->dev);
 	priv->netdev = dev;
+
+	priv->clk_ppe = clk_get(&pdev->dev, NULL);
+	if (!priv->clk_ppe)
+		return -ENOENT;
+	if (ltq_has_gbit()) {
+		priv->clk_switch = clk_get(&pdev->dev, "switch");
+		if (!priv->clk_switch)
+			return -ENOENT;
+	}
+	if (ltq_is_ase()) {
+		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
+		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
+		if (!priv->clk_ephy || !priv->clk_ephycgu)
+			return -ENOENT;
+	}
+
 	spin_lock_init(&priv->lock);
 
 	for (i = 0; i < MAX_DMA_CHAN; i++) {
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api
  2012-02-23 16:03 ` [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver " John Crispin
@ 2012-02-24  8:28   ` David Miller
  2012-02-24  8:40     ` John Crispin
  2012-02-24 10:55   ` Sergei Shtylyov
  1 sibling, 1 reply; 21+ messages in thread
From: David Miller @ 2012-02-24  8:28 UTC (permalink / raw)
  To: blogic; +Cc: ralf, linux-mips, netdev

From: John Crispin <blogic@openwrt.org>
Date: Thu, 23 Feb 2012 17:03:10 +0100

> Update from old pmu_{dis,en}able() to ckldev api.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>

Come on guys, don't do crap like this.

When you have a 14 patch series, and I only see one or two of them
I have no idea what in the world you want me to do with these patches.

Are they dependent upon the previous patches that weren't sent to me?

Are they not and I can just apply them as-is?

Could I apply them as-is, but you want them to go via the MIPS tree
for some reason and just want my ACK?

Nobody knows because you didn't bother to say one way or another
and that is extremely irritating because as a result I have to
ask you all of these stupid questions and write this rediculious
email.

I'm just ignoring every single one of these MIPS patches, sorry.

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api
  2012-02-24  8:28   ` David Miller
@ 2012-02-24  8:40     ` John Crispin
  2012-02-24  8:53       ` David Miller
  0 siblings, 1 reply; 21+ messages in thread
From: John Crispin @ 2012-02-24  8:40 UTC (permalink / raw)
  To: David Miller; +Cc: ralf, linux-mips, netdev

On 24/02/12 09:28, David Miller wrote:
> From: John Crispin <blogic@openwrt.org>
> Date: Thu, 23 Feb 2012 17:03:10 +0100
>
>> Update from old pmu_{dis,en}able() to ckldev api.
>>
>> Signed-off-by: John Crispin <blogic@openwrt.org>
> Come on guys, don't do crap like this.
>
> When you have a 14 patch series, and I only see one or two of them
> I have no idea what in the world you want me to do with these patches.
>
> Are they dependent upon the previous patches that weren't sent to me?
>
> Are they not and I can just apply them as-is?
>
> Could I apply them as-is, but you want them to go via the MIPS tree
> for some reason and just want my ACK?
>
> Nobody knows because you didn't bother to say one way or another
> and that is extremely irritating because as a result I have to
> ask you all of these stupid questions and write this rediculious
> email.
>
> I'm just ignoring every single one of these MIPS patches, sorry.

Hi,

you are right, totally stupid of me to waste other peoples time like this.

I forgot the following things
* mention that i would welcome a ack'ed by from you
* mention that these patches should go via MIPS with the other patches
in the series
* I should have put in the commit messages, that you were CC'ed on, what
the rest of the series does
* on the last "fix locking issues" patch I also forgot to CC Ralf and MIPS


One question if I may ask
* do you want to be CC'ed for a full series even if only 1 patch relates
to netdev or should I simply think more about the commit message so it
is apparent what i expect ?

again, sorry for wasting your time with stupidity ... I will clean up
the mess I made during today ...

hope you accept my apology,
John

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api
  2012-02-24  8:40     ` John Crispin
@ 2012-02-24  8:53       ` David Miller
  0 siblings, 0 replies; 21+ messages in thread
From: David Miller @ 2012-02-24  8:53 UTC (permalink / raw)
  To: blogic; +Cc: ralf, linux-mips, netdev

From: John Crispin <blogic@openwrt.org>
Date: Fri, 24 Feb 2012 09:40:34 +0100

> One question if I may ask
> * do you want to be CC'ed for a full series even if only 1 patch relates
> to netdev or should I simply think more about the commit message so it
> is apparent what i expect ?

Only post the networking patches and mention the situation at hand
in this kind of case.

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver to clkdev api
  2012-02-23 16:03 ` [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver " John Crispin
  2012-02-24  8:28   ` David Miller
@ 2012-02-24 10:55   ` Sergei Shtylyov
  1 sibling, 0 replies; 21+ messages in thread
From: Sergei Shtylyov @ 2012-02-24 10:55 UTC (permalink / raw)
  To: John Crispin; +Cc: Ralf Baechle, linux-mips, netdev

Hello.

On 23-02-2012 20:03, John Crispin wrote:

> Update from old pmu_{dis,en}able() to ckldev api.

> Signed-off-by: John Crispin<blogic@openwrt.org>
> Cc: netdev@vger.kernel.org
[...]

> diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
> index e5ec8b1..6b2e4b4 100644
> --- a/drivers/net/ethernet/lantiq_etop.c
> +++ b/drivers/net/ethernet/lantiq_etop.c
[...]
> @@ -886,6 +903,22 @@ ltq_etop_probe(struct platform_device *pdev)
>   	priv->pdev = pdev;
>   	priv->pldata = dev_get_platdata(&pdev->dev);
>   	priv->netdev = dev;
> +
> +	priv->clk_ppe = clk_get(&pdev->dev, NULL);
> +	if (!priv->clk_ppe)
> +		return -ENOENT;
> +	if (ltq_has_gbit()) {
> +		priv->clk_switch = clk_get(&pdev->dev, "switch");
> +		if (!priv->clk_switch)

    clk_get() doesn't retirn NULL, it returns error code.

> +			return -ENOENT;
> +	}
> +	if (ltq_is_ase()) {
> +		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
> +		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
> +		if (!priv->clk_ephy || !priv->clk_ephycgu)

    Same here.

WBR, Sergei

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V2 12/14] WDT: MIPS: lantiq: convert watchdog driver to clkdev api
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (9 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 13/14] MIPS: lantiq: unify xway prom code John Crispin
  2012-02-23 16:03 ` [PATCH V2 14/14] MIPS: lantiq: add vr9 support John Crispin
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin, linux-watchdog

Refrence the IO region clock via its new access function.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-watchdog@vger.kernel.org
---
 drivers/watchdog/lantiq_wdt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index 9c8b10c..fa4866b 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev)
 	}
 
 	/* we do not need to enable the clock as it is always running */
-	clk = clk_get(&pdev->dev, "io");
+	clk = clk_get_io();
 	WARN_ON(!clk);
 	ltq_io_region_clk_rate = clk_get_rate(clk);
 	clk_put(clk);
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 13/14] MIPS: lantiq: unify xway prom code
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (10 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 12/14] WDT: MIPS: lantiq: convert watchdog " John Crispin
@ 2012-02-23 16:03 ` John Crispin
  2012-02-23 16:03 ` [PATCH V2 14/14] MIPS: lantiq: add vr9 support John Crispin
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin

The xway prom-ase.c and prom-xway.c files are redundant. Unify the 2 files.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/Makefile    |    5 +--
 arch/mips/lantiq/xway/prom-ase.c  |   48 ----------------------
 arch/mips/lantiq/xway/prom-xway.c |   64 ------------------------------
 arch/mips/lantiq/xway/prom.c      |   79 +++++++++++++++++++++++++++++++++++++
 4 files changed, 80 insertions(+), 116 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/prom-ase.c
 delete mode 100644 arch/mips/lantiq/xway/prom-xway.c
 create mode 100644 arch/mips/lantiq/xway/prom.c

diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 4dcb96f..89f0a11 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,4 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
-
-obj-$(CONFIG_SOC_XWAY) += prom-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
+obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
 
 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
deleted file mode 100644
index 3f86a3b..0000000
--- a/arch/mips/lantiq/xway/prom-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-#include "../prom.h"
-
-#define SOC_AMAZON_SE	"Amazon_SE"
-
-#define PART_SHIFT	12
-#define PART_MASK	0x0FFFFFFF
-#define REV_SHIFT	28
-#define REV_MASK	0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
-	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
-	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
-	sprintf(i->rev_type, "1.%d", i->rev);
-	switch (i->partnum) {
-	case SOC_ID_AMAZON_SE:
-		i->name = SOC_AMAZON_SE;
-		i->type = SOC_TYPE_AMAZON_SE;
-		break;
-
-	default:
-		unreachable();
-		break;
-	}
-}
-
-void __init ltq_soc_setup(void)
-{
-	ltq_register_ase_asc();
-	ltq_register_gpio();
-	ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
deleted file mode 100644
index d823a92..0000000
--- a/arch/mips/lantiq/xway/prom-xway.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-#include "../prom.h"
-
-#define SOC_DANUBE	"Danube"
-#define SOC_TWINPASS	"Twinpass"
-#define SOC_AR9		"AR9"
-
-#define PART_SHIFT	12
-#define PART_MASK	0x0FFFFFFF
-#define REV_SHIFT	28
-#define REV_MASK	0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
-	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
-	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
-	sprintf(i->rev_type, "1.%d", i->rev);
-	switch (i->partnum) {
-	case SOC_ID_DANUBE1:
-	case SOC_ID_DANUBE2:
-		i->name = SOC_DANUBE;
-		i->type = SOC_TYPE_DANUBE;
-		break;
-
-	case SOC_ID_TWINPASS:
-		i->name = SOC_TWINPASS;
-		i->type = SOC_TYPE_DANUBE;
-		break;
-
-	case SOC_ID_ARX188:
-	case SOC_ID_ARX168:
-	case SOC_ID_ARX182:
-		i->name = SOC_AR9;
-		i->type = SOC_TYPE_AR9;
-		break;
-
-	default:
-		unreachable();
-		break;
-	}
-}
-
-void __init ltq_soc_setup(void)
-{
-	ltq_register_asc(0);
-	ltq_register_asc(1);
-	ltq_register_gpio();
-	ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
new file mode 100644
index 0000000..0929acb
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom.c
@@ -0,0 +1,79 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/export.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+#include "devices.h"
+
+#define SOC_DANUBE	"Danube"
+#define SOC_TWINPASS	"Twinpass"
+#define SOC_AR9		"AR9"
+#define SOC_VR9		"VR9"
+
+#define PART_SHIFT	12
+#define PART_MASK	0x0FFFFFFF
+#define REV_SHIFT	28
+#define REV_MASK	0xF0000000
+
+#define SOC_AMAZON_SE	"Amazon_SE"
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+	sprintf(i->rev_type, "1.%d", i->rev);
+	switch (i->partnum) {
+	case SOC_ID_DANUBE1:
+	case SOC_ID_DANUBE2:
+		i->name = SOC_DANUBE;
+		i->type = SOC_TYPE_DANUBE;
+		break;
+
+	case SOC_ID_TWINPASS:
+		i->name = SOC_TWINPASS;
+		i->type = SOC_TYPE_DANUBE;
+		break;
+
+	case SOC_ID_ARX188:
+	case SOC_ID_ARX168:
+	case SOC_ID_ARX182:
+		i->name = SOC_AR9;
+		i->type = SOC_TYPE_AR9;
+		break;
+
+	case SOC_ID_AMAZON_SE:
+		i->name = SOC_AMAZON_SE;
+		i->type = SOC_TYPE_AMAZON_SE;
+#ifdef CONFIG_PCI
+		panic("ase is only supported for non pci kernels");
+#endif
+		break;
+
+	default:
+		unreachable();
+		break;
+	}
+}
+
+void __init ltq_soc_setup(void)
+{
+	if (ltq_is_ase()) {
+		ltq_register_ase_asc();
+	} else {
+		ltq_register_asc(0);
+		ltq_register_asc(1);
+	}
+	ltq_register_gpio();
+	ltq_register_wdt();
+}
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH V2 14/14] MIPS: lantiq: add vr9 support
  2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
                   ` (11 preceding siblings ...)
  2012-02-23 16:03 ` [PATCH V2 13/14] MIPS: lantiq: unify xway prom code John Crispin
@ 2012-02-23 16:03 ` John Crispin
  12 siblings, 0 replies; 21+ messages in thread
From: John Crispin @ 2012-02-23 16:03 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, John Crispin, Daniel Schwierzeck

VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
This patch adds the clkdev init code and SoC detection for the VR9.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    3 +
 arch/mips/lantiq/xway/clk.c                        |   83 ++++++++++++++++++++
 arch/mips/lantiq/xway/prom.c                       |    6 ++
 arch/mips/lantiq/xway/sysctrl.c                    |   12 +++-
 4 files changed, 103 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 2208a9db..efd238b 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -21,6 +21,9 @@
 #define SOC_ID_ARX188		0x16C
 #define SOC_ID_ARX168		0x16D
 #define SOC_ID_ARX182		0x16F
+#define SOC_ID_VRX288		0x1C0 /* VRX288 v1.1 */
+#define SOC_ID_VRX268		0x1C2 /* VRX268 v1.1 */
+#define SOC_ID_GRX288		0x1C9 /* GRX288 v1.1 */
 
 /* SoC Types */
 #define SOC_TYPE_DANUBE		0x01
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index f3b50fc..3635c9f 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
 		return ddr_clock >> 1;
 	return ddr_clock;
 }
+
+unsigned long ltq_vr9_cpu_hz(void)
+{
+	unsigned int cpu_sel;
+	unsigned long clk;
+
+	cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
+
+	switch (cpu_sel) {
+	case 0:
+		clk = CLOCK_600M;
+		break;
+	case 1:
+		clk = CLOCK_500M;
+		break;
+	case 2:
+		clk = CLOCK_393M;
+		break;
+	case 3:
+		clk = CLOCK_333M;
+		break;
+	case 5:
+	case 6:
+		clk = CLOCK_196_608M;
+		break;
+	case 7:
+		clk = CLOCK_167M;
+		break;
+	case 4:
+	case 8:
+	case 9:
+		clk = CLOCK_125M;
+		break;
+	default:
+		clk = 0;
+		break;
+	}
+
+	return clk;
+}
+
+unsigned long ltq_vr9_fpi_hz(void)
+{
+	unsigned int ocp_sel, cpu_clk;
+	unsigned long clk;
+
+	cpu_clk = ltq_vr9_cpu_hz();
+	ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
+
+	switch (ocp_sel) {
+	case 0:
+		/* OCP ratio 1 */
+		clk = cpu_clk;
+		break;
+	case 2:
+		/* OCP ratio 2 */
+		clk = cpu_clk / 2;
+		break;
+	case 3:
+		/* OCP ratio 2.5 */
+		clk = (cpu_clk * 2) / 5;
+		break;
+	case 4:
+		/* OCP ratio 3 */
+		clk = cpu_clk / 3;
+		break;
+	default:
+		clk = 0;
+		break;
+	}
+
+	return clk;
+}
+
+unsigned long ltq_vr9_io_region_clock(void)
+{
+	return ltq_vr9_fpi_hz();
+}
+
+unsigned long ltq_vr9_fpi_bus_clock(int fpi)
+{
+	return ltq_vr9_fpi_hz();
+}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
index 0929acb..b6f56b7 100644
--- a/arch/mips/lantiq/xway/prom.c
+++ b/arch/mips/lantiq/xway/prom.c
@@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 #endif
 		break;
 
+	case SOC_ID_VRX268:
+	case SOC_ID_VRX288:
+		i->name = SOC_VR9;
+		i->type = SOC_TYPE_VR9;
+		break;
+
 	default:
 		unreachable();
 		break;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 22d076e..ccf9223 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
 	clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 	clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 	clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
-	clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
+	if (!ltq_is_vr9())
+		clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 	if (ltq_is_ase()) {
 		if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
 			clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
@@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
 			clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 		clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
 		clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
+	} else if (ltq_is_vr9()) {
+		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
+					ltq_vr9_io_region_clock());
+		clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
+		clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
+		clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
+		clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
+		clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
+		clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 	} else {
 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 					ltq_danube_io_region_clock());
-- 
1.7.7.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2012-02-24 10:56 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-02-23 16:03 [PATCH V2 01/14] MIPS: add clkdev.h John Crispin
2012-02-23 16:03 ` [PATCH V2 02/14] MIPS: lantiq: helper functions for SoC detection John Crispin
2012-02-23 16:03 ` [PATCH V2 03/14] MIPS: lantiq: convert to clkdev api John Crispin
2012-02-23 16:03 ` [PATCH V2 04/14] MIPS: lantiq: convert xway " John Crispin
2012-02-23 16:03 ` [PATCH V2 05/14] MIPS: lantiq: convert falcon " John Crispin
2012-02-23 16:03 ` [PATCH V2 06/14] MIPS: lantiq: convert dma driver " John Crispin
2012-02-23 16:03 ` [PATCH V2 07/14] MIPS: lantiq: convert gpio_stp " John Crispin
2012-02-24 10:46   ` Sergei Shtylyov
2012-02-23 16:03 ` [PATCH V2 08/14] MIPS: lantiq: convert falcon gpio " John Crispin
2012-02-24 10:45   ` Sergei Shtylyov
2012-02-23 16:03 ` [PATCH V2 09/14] SERIAL: MIPS: lantiq: convert serial driver " John Crispin
2012-02-23 16:03 ` [PATCH V2 10/14] MIPS: lantiq: convert falcon debug uart " John Crispin
2012-02-24 10:53   ` Sergei Shtylyov
2012-02-23 16:03 ` [PATCH V2 11/14] NET: MIPS: lantiq: convert etop driver " John Crispin
2012-02-24  8:28   ` David Miller
2012-02-24  8:40     ` John Crispin
2012-02-24  8:53       ` David Miller
2012-02-24 10:55   ` Sergei Shtylyov
2012-02-23 16:03 ` [PATCH V2 12/14] WDT: MIPS: lantiq: convert watchdog " John Crispin
2012-02-23 16:03 ` [PATCH V2 13/14] MIPS: lantiq: unify xway prom code John Crispin
2012-02-23 16:03 ` [PATCH V2 14/14] MIPS: lantiq: add vr9 support John Crispin

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.