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* [PATCH] drm/i915: there's no cxsr on ilk
@ 2012-05-30 15:15 Daniel Vetter
  2012-05-30 15:19 ` Eugeni Dodonov
  0 siblings, 1 reply; 3+ messages in thread
From: Daniel Vetter @ 2012-05-30 15:15 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Eugeni Dodonov

Already discovered in

commit 5a117db77e47e3946d1aaa7ce8deafafd9d76746
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date:   Thu Jan 5 09:34:29 2012 -0200

    drm/i915: there is no pipe CxSR on ironlake

but we've failed to rip out the code from the ironlake specific code.

Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68dfc07..0161d94 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4647,16 +4647,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (is_lvds && has_reduced_clock && i915_powersave) {
 			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
 			intel_crtc->lowfreq_avail = true;
-			if (HAS_PIPE_CXSR(dev)) {
-				DRM_DEBUG_KMS("enabling CxSR downclocking\n");
-				pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
-			}
 		} else {
 			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
-			if (HAS_PIPE_CXSR(dev)) {
-				DRM_DEBUG_KMS("disabling CxSR downclocking\n");
-				pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
-			}
 		}
 	}
 
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2012-05-31  7:29 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2012-05-30 15:15 [PATCH] drm/i915: there's no cxsr on ilk Daniel Vetter
2012-05-30 15:19 ` Eugeni Dodonov
2012-05-31  7:30   ` Daniel Vetter

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