* [Xenomai] Edge interrupts on PCI drivers
@ 2012-07-17 14:57 Jorge Ramirez Ortiz, HCL Europe
2012-07-17 15:00 ` Wolfgang Grandegger
0 siblings, 1 reply; 4+ messages in thread
From: Jorge Ramirez Ortiz, HCL Europe @ 2012-07-17 14:57 UTC (permalink / raw)
To: xenomai@xenomai.org
Typical PCI devices have many sources of interrupts (some level, some edge triggered) normally all routed through PIN A.
When writing an RTDM pci driver for one of these devices, how does the microkernel manage the edge interrupts?
I am looking at some traces where the CPU seems to be interrupted continuously by an edge interrupt until the actual condition that causes it is cleared.
thanks
Jorge
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* Re: [Xenomai] Edge interrupts on PCI drivers
2012-07-17 14:57 [Xenomai] Edge interrupts on PCI drivers Jorge Ramirez Ortiz, HCL Europe
@ 2012-07-17 15:00 ` Wolfgang Grandegger
2012-07-17 15:02 ` Jan Kiszka
0 siblings, 1 reply; 4+ messages in thread
From: Wolfgang Grandegger @ 2012-07-17 15:00 UTC (permalink / raw)
To: Jorge Ramirez Ortiz, HCL Europe; +Cc: xenomai@xenomai.org
On 07/17/2012 04:57 PM, Jorge Ramirez Ortiz, HCL Europe wrote:
> Typical PCI devices have many sources of interrupts (some level, some edge triggered) normally all routed through PIN A.
AFAIC, PCI interrupts are *always* level sensitive.
> When writing an RTDM pci driver for one of these devices, how does the microkernel manage the edge interrupts?
>
> I am looking at some traces where the CPU seems to be interrupted continuously by an edge interrupt until the actual condition that causes it is cleared.
That's normal for level sensitive interrupt sources.
Wolfgang.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Xenomai] Edge interrupts on PCI drivers
2012-07-17 15:00 ` Wolfgang Grandegger
@ 2012-07-17 15:02 ` Jan Kiszka
2012-07-17 15:16 ` Jorge Ramirez Ortiz, HCL Europe
0 siblings, 1 reply; 4+ messages in thread
From: Jan Kiszka @ 2012-07-17 15:02 UTC (permalink / raw)
To: Wolfgang Grandegger, Jorge Ramirez Ortiz, HCL Europe; +Cc: xenomai@xenomai.org
On 2012-07-17 17:00, Wolfgang Grandegger wrote:
> On 07/17/2012 04:57 PM, Jorge Ramirez Ortiz, HCL Europe wrote:
>> Typical PCI devices have many sources of interrupts (some level, some edge triggered) normally all routed through PIN A.
>
> AFAIC, PCI interrupts are *always* level sensitive.
More precisely, legacy INTx are level triggered, MSI/MSI-X interrupts
are edge. About which type are we talking here?
Jan
--
Siemens AG, Corporate Technology, CT RTC ITP SDP-DE
Corporate Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Xenomai] Edge interrupts on PCI drivers
2012-07-17 15:02 ` Jan Kiszka
@ 2012-07-17 15:16 ` Jorge Ramirez Ortiz, HCL Europe
0 siblings, 0 replies; 4+ messages in thread
From: Jorge Ramirez Ortiz, HCL Europe @ 2012-07-17 15:16 UTC (permalink / raw)
To: Jan Kiszka, Wolfgang Grandegger; +Cc: xenomai@xenomai.org
sure all PCI interrupts are level (I wasnt referring to PCIe).
I think in the case of these PCI multidevice boards, the only way to handle the edge interrupt sources is to disable the particular edge interrupt in the ISR and re-enable it only after the condition is cleared. IF the condition is not cleared or the interrupt is not attended, even if it is an edge interrupt,. the CPU thinks the PCI device it is trying to interrupt again.
Sorry this wasnt Xenomai specific...just talking to myself...
[also apologies about the top posting. maybe I should copy/paste my comments at the bottom of the thread...]
________________________________________
From: Jan Kiszka [jan.kiszka@siemens.com]
Sent: 17 July 2012 16:02
To: Wolfgang Grandegger; Jorge Ramirez Ortiz, HCL Europe
Cc: xenomai@xenomai.org
Subject: Re: [Xenomai] Edge interrupts on PCI drivers
On 2012-07-17 17:00, Wolfgang Grandegger wrote:
> On 07/17/2012 04:57 PM, Jorge Ramirez Ortiz, HCL Europe wrote:
>> Typical PCI devices have many sources of interrupts (some level, some edge triggered) normally all routed through PIN A.
>
> AFAIC, PCI interrupts are *always* level sensitive.
More precisely, legacy INTx are level triggered, MSI/MSI-X interrupts
are edge. About which type are we talking here?
Jan
--
Siemens AG, Corporate Technology, CT RTC ITP SDP-DE
Corporate Competence Center Embedded Linux
::DISCLAIMER::
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The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only.
E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted,
lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents
(with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates.
Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the
views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification,
distribution and / or publication of this message without the prior written consent of authorized representative of
HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately.
Before opening any email and/or attachments, please check them for viruses and other defects.
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2012-07-17 14:57 [Xenomai] Edge interrupts on PCI drivers Jorge Ramirez Ortiz, HCL Europe
2012-07-17 15:00 ` Wolfgang Grandegger
2012-07-17 15:02 ` Jan Kiszka
2012-07-17 15:16 ` Jorge Ramirez Ortiz, HCL Europe
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