[PATCH 0/4] Add RI and XI bits to MIPS base architecture.

[PATCH 0/4] Add RI and XI bits to MIPS base architecture.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
and Execute Inhibit (XI) page protection. SmartMIPS cores will not
notice any change in functionality.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

Steven J. Hill (4):
  MIPS: Add base architecture support for RI and XI.
  MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm.
  MIPS: Remove kernel_uses_smartmips_rixi from page table bits.
  MIPS: Remove kernel_uses_smartmips_rixi macro definition.

 arch/mips/include/asm/cpu-features.h               |    7 ++++--
 arch/mips/include/asm/cpu.h                        |    2 ++
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 --
 arch/mips/include/asm/mipsregs.h                   |    1 +
 arch/mips/include/asm/pgtable-bits.h               |   24 ++++++++++++--------
 arch/mips/include/asm/pgtable.h                    |   12 +++++-----
 arch/mips/kernel/cpu-probe.c                       |   12 +++++++++-
 arch/mips/mm/cache.c                               |    2 +-
 arch/mips/mm/fault.c                               |    4 +++-
 arch/mips/mm/tlb-r4k.c                             |    7 ++++--
 arch/mips/mm/tlbex.c                               |   14 ++++++------
 11 files changed, 55 insertions(+), 32 deletions(-)

-- 
1.7.9.5

[PATCH 1/4] MIPS: Add base architecture support for RI and XI.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/include/asm/cpu-features.h |    6 ++++++
 arch/mips/include/asm/cpu.h          |    2 ++
 arch/mips/include/asm/mipsregs.h     |    1 +
 arch/mips/kernel/cpu-probe.c         |   12 +++++++++++-
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 080edd8..c78a77b 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -98,6 +98,12 @@
 #ifndef kernel_uses_smartmips_rixi
 #define kernel_uses_smartmips_rixi 0
 #endif
+#ifndef cpu_has_ri
+#define cpu_has_ri		(cpu_data[0].options & MIPS_CPU_RI)
+#endif 
+#ifndef cpu_has_xi
+#define cpu_has_xi		(cpu_data[0].options & MIPS_CPU_XI)
+#endif
 #ifndef cpu_has_mmips
 #define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4889fae..1b928ed 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -323,6 +323,8 @@ enum cpu_type_enum {
 #define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 #define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */
 #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_RI		0x02000000 /* CPU has TLB Read Inhibit */
+#define MIPS_CPU_XI		0x04000000 /* CPU has TLB Execute Inhibit */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index cdb9c87..19430fb 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -591,6 +591,7 @@
 #define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
 #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 009fc13..e85d732 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 
 	config3 = read_c0_config3();
 
-	if (config3 & MIPS_CONF3_SM)
+	if (config3 & MIPS_CONF3_SM) {
 		c->ases |= MIPS_ASE_SMARTMIPS;
+		c->options |= MIPS_CPU_RI;
+		c->options |= MIPS_CPU_XI;
+	}
+	if (config3 & MIPS_CONF3_RXI) {
+		write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE);
+		if (read_c0_pagegrain() & PG_RIE)
+			c->options |= MIPS_CPU_RI;
+		if (read_c0_pagegrain() & PG_XIE)
+			c->options |= MIPS_CPU_XI;
+	}
 	if (config3 & MIPS_CONF3_DSP)
 		c->ases |= MIPS_ASE_DSP;
 	if (config3 & MIPS_CONF3_DSP2P)
-- 
1.7.9.5

Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI.

[David Daney]

On 09/05/2012 01:27 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
> supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
> Architecture now defines an optional feature to implement these
> TLB bits separately. Support for one or both features can be
> checked by looking at the Config3.RXI bit.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>

This particular patch seems fine.

Acked-by: David Daney <david.daney@cavium.com>


However in order not to break things there has to be a follow-on patch 
that is applied before any of the subsequent patches that sets 
cpu_has_ri and cpu_has_xi to the proper values for OCTEON.

David Daney


> ---
>   arch/mips/include/asm/cpu-features.h |    6 ++++++
>   arch/mips/include/asm/cpu.h          |    2 ++
>   arch/mips/include/asm/mipsregs.h     |    1 +
>   arch/mips/kernel/cpu-probe.c         |   12 +++++++++++-
>   4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index 080edd8..c78a77b 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -98,6 +98,12 @@
>   #ifndef kernel_uses_smartmips_rixi
>   #define kernel_uses_smartmips_rixi 0
>   #endif
> +#ifndef cpu_has_ri
> +#define cpu_has_ri		(cpu_data[0].options & MIPS_CPU_RI)
> +#endif
> +#ifndef cpu_has_xi
> +#define cpu_has_xi		(cpu_data[0].options & MIPS_CPU_XI)
> +#endif
>   #ifndef cpu_has_mmips
>   #define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
>   #endif
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 4889fae..1b928ed 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -323,6 +323,8 @@ enum cpu_type_enum {
>   #define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
>   #define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */
>   #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
> +#define MIPS_CPU_RI		0x02000000 /* CPU has TLB Read Inhibit */
> +#define MIPS_CPU_XI		0x04000000 /* CPU has TLB Execute Inhibit */
>
>   /*
>    * CPU ASE encodings
> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index cdb9c87..19430fb 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -591,6 +591,7 @@
>   #define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
>   #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
>   #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
> +#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
>   #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
>   #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
>   #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 009fc13..e85d732 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
>
>   	config3 = read_c0_config3();
>
> -	if (config3 & MIPS_CONF3_SM)
> +	if (config3 & MIPS_CONF3_SM) {
>   		c->ases |= MIPS_ASE_SMARTMIPS;
> +		c->options |= MIPS_CPU_RI;
> +		c->options |= MIPS_CPU_XI;
> +	}
> +	if (config3 & MIPS_CONF3_RXI) {
> +		write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE);
> +		if (read_c0_pagegrain() & PG_RIE)
> +			c->options |= MIPS_CPU_RI;
> +		if (read_c0_pagegrain() & PG_XIE)
> +			c->options |= MIPS_CPU_XI;
> +	}
>   	if (config3 & MIPS_CONF3_DSP)
>   		c->ases |= MIPS_ASE_DSP;
>   	if (config3 & MIPS_CONF3_DSP2P)
>

Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI.

[David Daney]

On 09/05/2012 01:48 PM, David Daney wrote:
> On 09/05/2012 01:27 PM, Steven J. Hill wrote:
>> From: "Steven J. Hill" <sjhill@mips.com>
>>
>> Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
>> supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
>> Architecture now defines an optional feature to implement these
>> TLB bits separately. Support for one or both features can be
>> checked by looking at the Config3.RXI bit.
>>
>> Signed-off-by: Steven J. Hill <sjhill@mips.com>
>
> This particular patch seems fine.
>
> Acked-by: David Daney <david.daney@cavium.com>

Sorry, I changed my mind.

NAK.

>
>
> However in order not to break things there has to be a follow-on patch
> that is applied before any of the subsequent patches that sets
> cpu_has_ri and cpu_has_xi to the proper values for OCTEON.
>
> David Daney
>
>
>> ---
>>   arch/mips/include/asm/cpu-features.h |    6 ++++++
>>   arch/mips/include/asm/cpu.h          |    2 ++
>>   arch/mips/include/asm/mipsregs.h     |    1 +
>>   arch/mips/kernel/cpu-probe.c         |   12 +++++++++++-
>>   4 files changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/include/asm/cpu-features.h
>> b/arch/mips/include/asm/cpu-features.h
>> index 080edd8..c78a77b 100644
>> --- a/arch/mips/include/asm/cpu-features.h
>> +++ b/arch/mips/include/asm/cpu-features.h
>> @@ -98,6 +98,12 @@
>>   #ifndef kernel_uses_smartmips_rixi
>>   #define kernel_uses_smartmips_rixi 0
>>   #endif
>> +#ifndef cpu_has_ri
>> +#define cpu_has_ri        (cpu_data[0].options & MIPS_CPU_RI)
>> +#endif
>> +#ifndef cpu_has_xi
>> +#define cpu_has_xi        (cpu_data[0].options & MIPS_CPU_XI)

Nobody in their right mind would implement only one of RI or XI.  So 
splitting this feature into two parts just adds complication with no 
benefit.  Unless you have evidence that there is actual silicon that 
only implements one of the two, there is no reason to split this, and to 
way to test it.

You can just keep kernel_uses_smartmips_rixi, and the rest of the patch 
set is mostly unneeded.

>> +#endif
>>   #ifndef cpu_has_mmips
>>   #define cpu_has_mmips        (cpu_data[0].options & MIPS_CPU_MICROMIPS)
>>   #endif
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index 4889fae..1b928ed 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -323,6 +323,8 @@ enum cpu_type_enum {
>>   #define MIPS_CPU_VEIC        0x00100000 /* CPU supports MIPSR2
>> external interrupt controller mode */
>>   #define MIPS_CPU_ULRI        0x00200000 /* CPU has ULRI feature */
>>   #define MIPS_CPU_MICROMIPS    0x01000000 /* CPU has microMIPS
>> capability */
>> +#define MIPS_CPU_RI        0x02000000 /* CPU has TLB Read Inhibit */
>> +#define MIPS_CPU_XI        0x04000000 /* CPU has TLB Execute Inhibit */

... and only one new bit needed here. ...

>>
>>   /*
>>    * CPU ASE encodings
>> diff --git a/arch/mips/include/asm/mipsregs.h
>> b/arch/mips/include/asm/mipsregs.h
>> index cdb9c87..19430fb 100644
>> --- a/arch/mips/include/asm/mipsregs.h
>> +++ b/arch/mips/include/asm/mipsregs.h
>> @@ -591,6 +591,7 @@
>>   #define MIPS_CONF3_LPA        (_ULCAST_(1) <<  7)
>>   #define MIPS_CONF3_DSP        (_ULCAST_(1) << 10)
>>   #define MIPS_CONF3_DSP2P    (_ULCAST_(1) << 11)
>> +#define MIPS_CONF3_RXI        (_ULCAST_(1) << 12)
>>   #define MIPS_CONF3_ULRI        (_ULCAST_(1) << 13)
>>   #define MIPS_CONF3_ISA        (_ULCAST_(3) << 14)
>>   #define MIPS_CONF3_ISA_OE    (_ULCAST_(1) << 16)
>> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
>> index 009fc13..e85d732 100644
>> --- a/arch/mips/kernel/cpu-probe.c
>> +++ b/arch/mips/kernel/cpu-probe.c
>> @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct
>> cpuinfo_mips *c)
>>
>>       config3 = read_c0_config3();
>>
>> -    if (config3 & MIPS_CONF3_SM)
>> +    if (config3 & MIPS_CONF3_SM) {
>>           c->ases |= MIPS_ASE_SMARTMIPS;
>> +        c->options |= MIPS_CPU_RI;
>> +        c->options |= MIPS_CPU_XI;
>> +    }
>> +    if (config3 & MIPS_CONF3_RXI) {
>> +        write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE);
>> +        if (read_c0_pagegrain() & PG_RIE)
>> +            c->options |= MIPS_CPU_RI;
>> +        if (read_c0_pagegrain() & PG_XIE)
>> +            c->options |= MIPS_CPU_XI;
>> +    }

... and this bit becomes a little simpler.


>>       if (config3 & MIPS_CONF3_DSP)
>>           c->ases |= MIPS_ASE_DSP;
>>       if (config3 & MIPS_CONF3_DSP2P)
>>
>

Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI.

[Kevin Cernekee]

On Wed, Sep 5, 2012 at 2:51 PM, David Daney <ddaney.cavm@gmail.com> wrote:
> Nobody in their right mind would implement only one of RI or XI.  So
> splitting this feature into two parts just adds complication with no
> benefit.  Unless you have evidence that there is actual silicon that only
> implements one of the two, there is no reason to split this, and to way to
> test it.
>
> You can just keep kernel_uses_smartmips_rixi, and the rest of the patch set
> is mostly unneeded.

Recent BMIPS4380/BMIPS5000 cores support the XI bit, and ignore the RI bit.

AFAICT it is safe to just use kernel_uses_smartmips_rixi=1 on these processors.

[PATCH 2/4] MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
in the 'arch/mips/mm' subsystem.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/mm/cache.c   |    2 +-
 arch/mips/mm/fault.c   |    4 +++-
 arch/mips/mm/tlb-r4k.c |    7 +++++--
 arch/mips/mm/tlbex.c   |   14 +++++++-------
 4 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index ff910a1..b478c51 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -183,7 +183,7 @@ EXPORT_SYMBOL(_page_cachable_default);
 
 static inline void setup_protection_map(void)
 {
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		protection_map[0]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
 		protection_map[1]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
 		protection_map[2]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index c14f6df..153aeee 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -114,7 +114,7 @@ good_area:
 		if (!(vma->vm_flags & VM_WRITE))
 			goto bad_area;
 	} else {
-		if (kernel_uses_smartmips_rixi) {
+		if (cpu_has_xi) {
 			if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) {
 #if 0
 				pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n",
@@ -125,6 +125,8 @@ good_area:
 #endif
 				goto bad_area;
 			}
+		}
+		else if (cpu_has_ri) {
 			if (!(vma->vm_flags & VM_READ)) {
 #if 0
 				pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n",
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index d2572cb..df894f8 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -401,12 +401,15 @@ void __cpuinit tlb_init(void)
 	    current_cpu_type() == CPU_R14000)
 		write_c0_framemask(0);
 
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
+		u32 pg;
+
 		/*
 		 * Enable the no read, no exec bits, and enable large virtual
 		 * address.
 		 */
-		u32 pg = PG_RIE | PG_XIE;
+		pg = (cpu_has_ri ? PG_RIE : 0);
+		pg |= (cpu_has_xi ? PG_XIE : 0);
 #ifdef CONFIG_64BIT
 		pg |= PG_ELPA;
 #endif
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e565d45..90c86ee 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
 								  unsigned int reg)
 {
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
 		UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
 	} else {
@@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
 	if (cpu_has_64bits) {
 		uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
 		uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
-		if (kernel_uses_smartmips_rixi) {
+		if (cpu_has_ri | cpu_has_xi) {
 			UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
 			UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
 			UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
@@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
 	UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
 	if (r45k_bvahwbug())
 		build_tlb_probe_entry(p);
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
 		UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
 		UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
@@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 		UASM_i_LW(p, even, 0, ptr); /* get even pte */
 		UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
 	}
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
 		uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
 		uasm_i_drotr(p, even, even,
@@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
 {
 	int t = scratch >= 0 ? scratch : pte;
 
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		if (use_bbit_insns()) {
 			uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
 			uasm_i_nop(p);
@@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
 	if (m4kc_tlbp_war())
 		build_tlb_probe_entry(&p);
 
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
@@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
 	build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
 	build_tlb_probe_entry(&p);
 
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
-- 
1.7.9.5

Re: [PATCH 2/4] MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm.

[David Daney]

On 09/05/2012 01:27 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
> in the 'arch/mips/mm' subsystem.
>

> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index e565d45..90c86ee 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
>   static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
>   								  unsigned int reg)
>   {
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
>   		UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
>   		UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));

Patch is out of date.

This will not apply against mips-for-linux-next.

>   	} else {
> @@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
>   	if (cpu_has_64bits) {
>   		uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
>   		uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
> -		if (kernel_uses_smartmips_rixi) {
> +		if (cpu_has_ri | cpu_has_xi) {
>   			UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
>   			UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
>   			UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
> @@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
>   	UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
>   	if (r45k_bvahwbug())
>   		build_tlb_probe_entry(p);
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
>   		UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
>   		UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
>   		UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
> @@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
>   		UASM_i_LW(p, even, 0, ptr); /* get even pte */
>   		UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
>   	}
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
>   		uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
>   		uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
>   		uasm_i_drotr(p, even, even,
> @@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
>   {
>   	int t = scratch >= 0 ? scratch : pte;
>
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
>   		if (use_bbit_insns()) {
>   			uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
>   			uasm_i_nop(p);
> @@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
>   	if (m4kc_tlbp_war())
>   		build_tlb_probe_entry(&p);
>
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {

These bits should be made conditional on the value of PageGrain[IEC].

Also when PageGrain[IEC] is set you would have to install the proper 
exception handlers for TLBRI and TLBXI ExecCodes.

>   		/*
>   		 * If the page is not _PAGE_VALID, RI or XI could not
>   		 * have triggered it.  Skip the expensive test..
> @@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
>   	build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
>   	build_tlb_probe_entry(&p);
>
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
>   		/*
>   		 * If the page is not _PAGE_VALID, RI or XI could not
>   		 * have triggered it.  Skip the expensive test..
>

[PATCH 3/4] MIPS: Remove kernel_uses_smartmips_rixi from page table bits.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all the
page table bit definitions in 'arch/mips/include/asm' directory.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/include/asm/pgtable-bits.h |   24 ++++++++++++++----------
 arch/mips/include/asm/pgtable.h      |   12 ++++++------
 2 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e9fe7e9..c266cba 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -79,9 +79,9 @@
 /* implemented in software */
 #define _PAGE_PRESENT_SHIFT	(0)
 #define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
-/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
-#define _PAGE_READ_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
-#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
+/* implemented in software, should be unused if cpu_has_ri. */
+#define _PAGE_READ_SHIFT	(cpu_has_ri ? _PAGE_PRESENT_SHIFT + 1: _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_READ_SHIFT; })
 /* implemented in software */
 #define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
 #define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
@@ -104,12 +104,12 @@
 #endif
 
 /* Page cannot be executed */
-#define _PAGE_NO_EXEC_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
-#define _PAGE_NO_EXEC		({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
+#define _PAGE_NO_EXEC_SHIFT	(cpu_has_xi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
+#define _PAGE_NO_EXEC		({if (!cpu_has_xi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
 
 /* Page cannot be read */
-#define _PAGE_NO_READ_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
-#define _PAGE_NO_READ		({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
+#define _PAGE_NO_READ_SHIFT	(cpu_has_ri ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ		({if (!cpu_has_ri) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
 
 #define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
 #define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
@@ -155,20 +155,24 @@
  */
 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 {
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri | cpu_has_xi) {
+		unsigned long rixi;
 		int sa;
 #ifdef CONFIG_32BIT
 		sa = 31 - _PAGE_NO_READ_SHIFT;
 #else
 		sa = 63 - _PAGE_NO_READ_SHIFT;
 #endif
+		rixi = ((cpu_has_ri ? _PAGE_NO_READ : 0) |
+			(cpu_has_xi ? _PAGE_NO_EXEC : 0));
+
 		/*
 		 * C has no way to express that this is a DSRL
 		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
 		 * in the fast path this is done in assembly
 		 */
 		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
-			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+			 ((pte_val & rixi) << sa);
 	}
 
 	return pte_val >> _PAGE_GLOBAL_SHIFT;
@@ -220,7 +224,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 
 #endif
 
-#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
+#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_ri ? 0 : _PAGE_READ))
 #define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 
 #define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index b2202a6..748aa6a 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -22,15 +22,15 @@ struct mm_struct;
 struct vm_area_struct;
 
 #define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_ri ? 0 : _PAGE_READ) | \
 				 _page_cachable_default)
-#define PAGE_COPY	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
-				 (kernel_uses_smartmips_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
-#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_COPY	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \
+				 (cpu_has_xi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
+#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \
 				 _page_cachable_default)
 #define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
 				 _PAGE_GLOBAL | _page_cachable_default)
-#define PAGE_USERIO	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
+#define PAGE_USERIO	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | _PAGE_WRITE | \
 				 _page_cachable_default)
 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
 			__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
@@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte)
 static inline pte_t pte_mkyoung(pte_t pte)
 {
 	pte_val(pte) |= _PAGE_ACCESSED;
-	if (kernel_uses_smartmips_rixi) {
+	if (cpu_has_ri) {
 		if (!(pte_val(pte) & _PAGE_NO_READ))
 			pte_val(pte) |= _PAGE_SILENT_READ;
 	} else {
-- 
1.7.9.5

Re: [PATCH 3/4] MIPS: Remove kernel_uses_smartmips_rixi from page table bits.

[David Daney]

On 09/05/2012 01:27 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Remove usage of the 'kernel_uses_smartmips_rixi' macro from all the
> page table bit definitions in 'arch/mips/include/asm' directory.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
> ---
>   arch/mips/include/asm/pgtable-bits.h |   24 ++++++++++++++----------
>   arch/mips/include/asm/pgtable.h      |   12 ++++++------
>   2 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index e9fe7e9..c266cba 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -79,9 +79,9 @@
>   /* implemented in software */
>   #define _PAGE_PRESENT_SHIFT	(0)
>   #define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
> -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
> -#define _PAGE_READ_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
> -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
> +/* implemented in software, should be unused if cpu_has_ri. */
> +#define _PAGE_READ_SHIFT	(cpu_has_ri ? _PAGE_PRESENT_SHIFT + 1: _PAGE_PRESENT_SHIFT)

As per IRC discussion, it would be nice if the shift value were not 
dependent on runtime values (cpu_has_ri)

See this thread for ideas about this:

http://www.linux-mips.org/archives/linux-mips/2011-04/msg00102.html

> +#define _PAGE_READ ({if (!cpu_has_ri) BUG(); 1 << _PAGE_READ_SHIFT; })
>   /* implemented in software */
>   #define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
>   #define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
> @@ -104,12 +104,12 @@
>   #endif
>
>   /* Page cannot be executed */
> -#define _PAGE_NO_EXEC_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
> -#define _PAGE_NO_EXEC		({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
> +#define _PAGE_NO_EXEC_SHIFT	(cpu_has_xi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
> +#define _PAGE_NO_EXEC		({if (!cpu_has_xi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
>
>   /* Page cannot be read */
> -#define _PAGE_NO_READ_SHIFT	(kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
> -#define _PAGE_NO_READ		({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
> +#define _PAGE_NO_READ_SHIFT	(cpu_has_ri ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
> +#define _PAGE_NO_READ		({if (!cpu_has_ri) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
>
>   #define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
>   #define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
> @@ -155,20 +155,24 @@
>    */
>   static inline uint64_t pte_to_entrylo(unsigned long pte_val)
>   {
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri | cpu_has_xi) {
> +		unsigned long rixi;
>   		int sa;
>   #ifdef CONFIG_32BIT
>   		sa = 31 - _PAGE_NO_READ_SHIFT;
>   #else
>   		sa = 63 - _PAGE_NO_READ_SHIFT;
>   #endif
> +		rixi = ((cpu_has_ri ? _PAGE_NO_READ : 0) |
> +			(cpu_has_xi ? _PAGE_NO_EXEC : 0));
> +
>   		/*
>   		 * C has no way to express that this is a DSRL
>   		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
>   		 * in the fast path this is done in assembly
>   		 */
>   		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
> -			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
> +			 ((pte_val & rixi) << sa);
>   	}
>
>   	return pte_val >> _PAGE_GLOBAL_SHIFT;
> @@ -220,7 +224,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
>
>   #endif
>
> -#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
> +#define __READABLE	(_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_ri ? 0 : _PAGE_READ))
>   #define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
>
>   #define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
> diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
> index b2202a6..748aa6a 100644
> --- a/arch/mips/include/asm/pgtable.h
> +++ b/arch/mips/include/asm/pgtable.h
> @@ -22,15 +22,15 @@ struct mm_struct;
>   struct vm_area_struct;
>
>   #define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
> -#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
> +#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_ri ? 0 : _PAGE_READ) | \
>   				 _page_cachable_default)
> -#define PAGE_COPY	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
> -				 (kernel_uses_smartmips_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
> -#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
> +#define PAGE_COPY	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \
> +				 (cpu_has_xi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
> +#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | \
>   				 _page_cachable_default)
>   #define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
>   				 _PAGE_GLOBAL | _page_cachable_default)
> -#define PAGE_USERIO	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
> +#define PAGE_USERIO	__pgprot(_PAGE_PRESENT | (cpu_has_ri ? 0 : _PAGE_READ) | _PAGE_WRITE | \
>   				 _page_cachable_default)
>   #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
>   			__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
> @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte)
>   static inline pte_t pte_mkyoung(pte_t pte)
>   {
>   	pte_val(pte) |= _PAGE_ACCESSED;
> -	if (kernel_uses_smartmips_rixi) {
> +	if (cpu_has_ri) {
>   		if (!(pte_val(pte) & _PAGE_NO_READ))
>   			pte_val(pte) |= _PAGE_SILENT_READ;
>   	} else {
>

[PATCH 4/4] MIPS: Remove kernel_uses_smartmips_rixi macro definition.

[Steven J. Hill]

From: "Steven J. Hill" <sjhill@mips.com>

Remove the 'kernel_uses_smartmips_rixi' macro definitions from
the architecture header files.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/include/asm/cpu-features.h               |    3 ---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 --
 2 files changed, 5 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c78a77b..7452d78 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,9 +95,6 @@
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
-#ifndef kernel_uses_smartmips_rixi
-#define kernel_uses_smartmips_rixi 0
-#endif
 #ifndef cpu_has_ri
 #define cpu_has_ri		(cpu_data[0].options & MIPS_CPU_RI)
 #endif 
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index a58addb..971bdc2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,8 +58,6 @@
 #define cpu_has_veic		0
 #define cpu_hwrena_impl_bits	0xc0000000
 
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
-
 #define ARCH_HAS_IRQ_PER_CPU	1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 #define spin_lock_prefetch(x) prefetch(x)
-- 
1.7.9.5

Re: [PATCH 4/4] MIPS: Remove kernel_uses_smartmips_rixi macro definition.

[David Daney]

On 09/05/2012 01:27 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Remove the 'kernel_uses_smartmips_rixi' macro definitions from
> the architecture header files.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
> ---
>   arch/mips/include/asm/cpu-features.h               |    3 ---
>   .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 --
>   2 files changed, 5 deletions(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index c78a77b..7452d78 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -95,9 +95,6 @@
>   #ifndef cpu_has_smartmips
>   #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
>   #endif
> -#ifndef kernel_uses_smartmips_rixi
> -#define kernel_uses_smartmips_rixi 0

As I said in the other message, you will want to have the replacement 
for this instance of kernel_uses_smartmips_rixi in place before you do 
the other conversions.

That said, at the end of the patch set, this does need to go, so 
something like this will be needed.

David Daney

> -#endif
>   #ifndef cpu_has_ri
>   #define cpu_has_ri		(cpu_data[0].options & MIPS_CPU_RI)
>   #endif
> diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> index a58addb..971bdc2 100644
> --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> @@ -58,8 +58,6 @@
>   #define cpu_has_veic		0
>   #define cpu_hwrena_impl_bits	0xc0000000
>
> -#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
> -
>   #define ARCH_HAS_IRQ_PER_CPU	1
>   #define ARCH_HAS_SPINLOCK_PREFETCH 1
>   #define spin_lock_prefetch(x) prefetch(x)
>