[PATCH 0/9] Enable all display interfaces in Valleyview

[PATCH 0/9] Enable all display interfaces in Valleyview

[Vijay Purushothaman]

This patch set enables all supported display interfaces like HDMI, DisplayPort 
and eDP for Valleyview. This also enables support for multi-display configurations.

Jesse, Ben : Since this patch set was reviewed in internal mailing lists, could 
you please add your reviewed-by & tested-by tags?

Bhat, Gajanan (1):
  drm/i915: Enable multi display support in VLV

Vijay Purushothaman (8):
  drm/i915: Set aux clk to 100MHz for Valleyview
  drm/i915: Fix SDVO IER and status bits for Valleyview
  drm/i915: Add Valleyview lane control definitions
  drm/i915: Program correct m n tu register for Valleyview
  drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort
  drm/i915: Add eDP support for Valleyview
  drm/i915: panel power sequencing for VLV eDP
  drm/i915: Reverse min,max vco limits for VLV HDMI

 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |   15 +++-
 drivers/gpu/drm/i915/intel_crt.c     |    7 ++
 drivers/gpu/drm/i915/intel_display.c |  103 ++++++++++++++++-------
 drivers/gpu/drm/i915/intel_dp.c      |  148 ++++++++++++++++++++++++----------
 5 files changed, 200 insertions(+), 79 deletions(-)

-- 
1.7.9.5

[PATCH 1/9] drm/i915: Set aux clk to 100MHz for Valleyview

[Vijay Purushothaman]

Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a69d9a2..de8092a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t clkcfg;
 
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
 	clkcfg = I915_READ(CLKCFG);
 	switch (clkcfg & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_400:
@@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if (IS_VALLEYVIEW(dev))
+			aux_clock_divider = 100;
+		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
-- 
1.7.9.5

[PATCH 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview

[Vijay Purushothaman]

Fixed SDVOB and SDVOC bit definitions for Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d915126..1a974d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 #endif
 
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-#if 0 /* FIXME: check register definitions; some have moved */
 	/* Note HDMI and DP share bits */
 	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
@@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
 		hotplug_en |= HDMID_HOTPLUG_INT_EN;
-	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
-	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
 		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
 	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
 		hotplug_en |= CRT_HOTPLUG_INT_EN;
 		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
 	}
-#endif
 
 	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 
-- 
1.7.9.5

[PATCH 3/9] drm/i915: Add Valleyview lane control definitions

[Vijay Purushothaman]

Added DPIO data lane register definitions for Valleyview

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828e90..3f75ee6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -369,6 +369,7 @@
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_PLL_REFCLK_SEL_MASK	3
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
 #define _DPIO_REFSFR_B			0x8034
@@ -384,6 +385,13 @@
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
+#define _DPIO_DATA_LANE0		0x0220
+#define _DPIO_DATA_LANE1		0x0420
+#define _DPIO_DATA_LANE2		0x2620
+#define _DPIO_DATA_LANE3		0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+
 /*
  * Fence registers
  */
-- 
1.7.9.5

[PATCH 4/9] drm/i915: Program correct m n tu register for Valleyview

[Vijay Purushothaman]

m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 +++---
 drivers/gpu/drm/i915/intel_dp.c      |    5 +++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
 };
 
 static const intel_limit_t intel_limits_vlv_dp = {
-	.dot = { .min = 162000, .max = 270000 },
-	.vco = { .min = 5994000, .max = 4000000 },
+	.dot = { .min = 25000, .max = 270000 },
+	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
-	.m = { .min = 60, .max = 300 }, /* guess */
+	.m = { .min = 22, .max = 450 },
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+	} else if (IS_VALLEYVIEW(dev)) {
+		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 	} else {
 		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-- 
1.7.9.5

[PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort

[Vijay Purushothaman]

In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c     |    7 ++++++
 drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++------
 2 files changed, 44 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c42b980..bd23bdf 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 	bool ret;
 	u32 save_adpa;
 
+	/*
+	 * Disable crt detect hotplug for VLV X0. spurious hot plug
+	 * detect calls crashes the X0 system
+	 */
+	if (IS_VALLEYVIEW(dev))
+		return false;
+
 	save_adpa = adpa = I915_READ(ADPA);
 	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..a8a81d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 fp, fp2 = 0;
 
+	/* Disable FP0 register programming for VLV X0 */
+	if (IS_VALLEYVIEW(dev))
+		return;
+
 	if (IS_PINEVIEW(dev)) {
 		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
 		if (reduced_clock)
@@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 
 	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
 
-	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
 		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
-		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
+		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
 	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
 
-	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
 
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll);
@@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 		POSTING_READ(DPLL_MD(pipe));
 	}
 
-	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
 }
 
 static void i9xx_update_pll(struct drm_crtc *crtc,
@@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 		dpll |= DPLL_DVO_HIGH_SPEED;
 
+	if (IS_VALLEYVIEW(dev)) {
+		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+	}
+
 	/* compute bitmask from p1 value */
 	if (IS_PINEVIEW(dev))
 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
@@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
+
+	/*
+	 * In Valleyview PLL and program lane counter registes are exposed
+	 * through DPIO interface
+	 */
+	if (IS_VALLEYVIEW(dev)) {
+		int refclk;
+		refclk = i9xx_get_refclk(crtc, num_connectors);
+		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
+			num_connectors);
+	}
 	udelay(150);
 
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
@@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
+	/* Now program lane control registers for Valleyview */
+	if (IS_VALLEYVIEW(dev)) {
+		u32 temp = 0;
+		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
+		temp |= (1 << 20);
+		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
+		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
+		temp |= (1 << 20);
+		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
+	}
+
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 temp = 0;
 		if (is_sdvo) {
@@ -4332,9 +4365,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (IS_GEN2(dev))
 		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
-	else if (IS_VALLEYVIEW(dev))
-		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
-			       refclk, num_connectors);
 	else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
-- 
1.7.9.5

Re: [PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort

[Daniel Vetter]

On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric. Also use
> i9xx_update_pll to program the correct DPLL sequence.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c     |    7 ++++++
>  drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++------
>  2 files changed, 44 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c42b980..bd23bdf 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>  	bool ret;
>  	u32 save_adpa;
>  
> +	/*
> +	 * Disable crt detect hotplug for VLV X0. spurious hot plug
> +	 * detect calls crashes the X0 system
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		return false;

This hunk here belongs into a different patch.

> +
>  	save_adpa = adpa = I915_READ(ADPA);
>  	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 68828e7..a8a81d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	int pipe = intel_crtc->pipe;
>  	u32 fp, fp2 = 0;
>  
> +	/* Disable FP0 register programming for VLV X0 */
> +	if (IS_VALLEYVIEW(dev))
> +		return;

This patch folds back the vlv_update_pll function into the i9xx_update_pll
function, which is imo the wrong approach (since you add quite some if
(IS_VLV) blocks). Better would be to move the i9xx_update_pll_dividers
into i8xx_update_pll and i9xx_update_pll and then keep the vlv_update_pll
(and only apply the necessary fixes there.
-Daniel
)
> +
>  	if (IS_PINEVIEW(dev)) {
>  		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
>  		if (reduced_clock)
> @@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  
>  	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
>  
> -	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> +	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
>  		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> -		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> +		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
> +		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
>  	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
>  
> -	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
>  
>  	dpll |= DPLL_VCO_ENABLE;
>  	I915_WRITE(DPLL(pipe), dpll);
> @@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  		POSTING_READ(DPLL_MD(pipe));
>  	}
>  
> -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>  }
>  
>  static void i9xx_update_pll(struct drm_crtc *crtc,
> @@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>  		dpll |= DPLL_DVO_HIGH_SPEED;
>  
> +	if (IS_VALLEYVIEW(dev)) {
> +		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> +		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> +		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> +	}
> +
>  	/* compute bitmask from p1 value */
>  	if (IS_PINEVIEW(dev))
>  		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> @@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	dpll |= DPLL_VCO_ENABLE;
>  	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
>  	POSTING_READ(DPLL(pipe));
> +
> +	/*
> +	 * In Valleyview PLL and program lane counter registes are exposed
> +	 * through DPIO interface
> +	 */
> +	if (IS_VALLEYVIEW(dev)) {
> +		int refclk;
> +		refclk = i9xx_get_refclk(crtc, num_connectors);
> +		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
> +			num_connectors);
> +	}
>  	udelay(150);
>  
>  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> @@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	POSTING_READ(DPLL(pipe));
>  	udelay(150);
>  
> +	/* Now program lane control registers for Valleyview */
> +	if (IS_VALLEYVIEW(dev)) {
> +		u32 temp = 0;
> +		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
> +		temp |= (1 << 20);
> +		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
> +		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
> +		temp |= (1 << 20);
> +		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
> +	}
> +
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		u32 temp = 0;
>  		if (is_sdvo) {
> @@ -4332,9 +4365,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	if (IS_GEN2(dev))
>  		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> -	else if (IS_VALLEYVIEW(dev))
> -		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
> -			       refclk, num_connectors);
>  	else
>  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>  				has_reduced_clock ? &reduced_clock : NULL,
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort

[Vijay Purushothaman]

On 9/26/2012 7:54 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
>> In Valleyview voltage swing, pre-emphasis and lane control registers can
>> be programmed only through the h/w side band fabric. Also use
>> i9xx_update_pll to program the correct DPLL sequence.
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
>> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_crt.c     |    7 ++++++
>>   drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++------
>>   2 files changed, 44 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
>> index c42b980..bd23bdf 100644
>> --- a/drivers/gpu/drm/i915/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/intel_crt.c
>> @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>>   	bool ret;
>>   	u32 save_adpa;
>>
>> +	/*
>> +	 * Disable crt detect hotplug for VLV X0. spurious hot plug
>> +	 * detect calls crashes the X0 system
>> +	 */
>> +	if (IS_VALLEYVIEW(dev))
>> +		return false;
>
> This hunk here belongs into a different patch.

Sure. I will move this hunk as a separate patch.

>
>> +
>>   	save_adpa = adpa = I915_READ(ADPA);
>>   	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 68828e7..a8a81d1 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>>   	int pipe = intel_crtc->pipe;
>>   	u32 fp, fp2 = 0;
>>
>> +	/* Disable FP0 register programming for VLV X0 */
>> +	if (IS_VALLEYVIEW(dev))
>> +		return;
>
> This patch folds back the vlv_update_pll function into the i9xx_update_pll
> function, which is imo the wrong approach (since you add quite some if
> (IS_VLV) blocks). Better would be to move the i9xx_update_pll_dividers
> into i8xx_update_pll and i9xx_update_pll and then keep the vlv_update_pll
> (and only apply the necessary fixes there.
> -Daniel
> )

Done.

>> +
>>   	if (IS_PINEVIEW(dev)) {
>>   		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
>>   		if (reduced_clock)
>> @@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>>
>>   	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
>>
>> -	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
>> +	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
>>   		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
>> -		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
>> +		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
>> +		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
>>   	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
>>
>> -	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
>> +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
>>
>>   	dpll |= DPLL_VCO_ENABLE;
>>   	I915_WRITE(DPLL(pipe), dpll);
>> @@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>>   		POSTING_READ(DPLL_MD(pipe));
>>   	}
>>
>> -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
>> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>>   }
>>
>>   static void i9xx_update_pll(struct drm_crtc *crtc,
>> @@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>>   		dpll |= DPLL_DVO_HIGH_SPEED;
>>
>> +	if (IS_VALLEYVIEW(dev)) {
>> +		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
>> +		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
>> +		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
>> +	}
>> +
>>   	/* compute bitmask from p1 value */
>>   	if (IS_PINEVIEW(dev))
>>   		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
>> @@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	dpll |= DPLL_VCO_ENABLE;
>>   	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
>>   	POSTING_READ(DPLL(pipe));
>> +
>> +	/*
>> +	 * In Valleyview PLL and program lane counter registes are exposed
>> +	 * through DPIO interface
>> +	 */
>> +	if (IS_VALLEYVIEW(dev)) {
>> +		int refclk;
>> +		refclk = i9xx_get_refclk(crtc, num_connectors);
>> +		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
>> +			num_connectors);
>> +	}
>>   	udelay(150);
>>
>>   	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>> @@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	POSTING_READ(DPLL(pipe));
>>   	udelay(150);
>>
>> +	/* Now program lane control registers for Valleyview */
>> +	if (IS_VALLEYVIEW(dev)) {
>> +		u32 temp = 0;
>> +		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
>> +		temp |= (1 << 20);
>> +		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
>> +		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
>> +		temp |= (1 << 20);
>> +		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
>> +	}
>> +
>>   	if (INTEL_INFO(dev)->gen >= 4) {
>>   		u32 temp = 0;
>>   		if (is_sdvo) {
>> @@ -4332,9 +4365,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>
>>   	if (IS_GEN2(dev))
>>   		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>> -	else if (IS_VALLEYVIEW(dev))
>> -		vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
>> -			       refclk, num_connectors);
>>   	else
>>   		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>>   				has_reduced_clock ? &reduced_clock : NULL,
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

[PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Vijay Purushothaman]

Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.

v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
	interfaces

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		}
 	}
 
+	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		pipeconf |= PIPECONF_BPP_6 |
+			PIPECONF_ENABLE |
+			I965_PIPECONF_ACTIVE;
+	}
+
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..af57027 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		uint32_t    signal_levels;
 
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		if (intel_dpd_is_edp(dev))
 			intel_dp->is_pch_edp = true;
 
-	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
+	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
+		type = DRM_MODE_CONNECTOR_eDP;
+		intel_encoder->type = INTEL_OUTPUT_EDP;
+	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 	} else {
-- 
1.7.9.5

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Daniel Vetter]

On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> Eventhough Valleyview display block is derived from Cantiga, VLV
> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> 
> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> v3: fix DPIO value calculation to use same values for all display
> 	interfaces
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
>  2 files changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a8a81d1..aee6151 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		}
>  	}
>  
> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> +		pipeconf |= PIPECONF_BPP_6 |
> +			PIPECONF_ENABLE |
> +			I965_PIPECONF_ACTIVE;
> +	}

No.

Jani Nikula and me just figured out that we have a giant mess with 6bpc
dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
papers over issues.

> +
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c111c3f..af57027 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>  
>  	/* Split out the IBX/CPU vs CPT settings */
>  
> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  
> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_400:
>  			return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  		uint32_t    signal_levels;
>  
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  			break;
>  		}
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  		if (intel_dpd_is_edp(dev))
>  			intel_dp->is_pch_edp = true;
>  
> -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> +		type = DRM_MODE_CONNECTOR_eDP;
> +		intel_encoder->type = INTEL_OUTPUT_EDP;

You need to be a notch more careful, since since

commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
Author: Adam Jackson <ajax@redhat.com>
Date:   Fri Jul 16 14:46:29 2010 -0400

    drm/i915: Initialize LVDS and eDP outputs before anything else

We initialize built-in panels before external outputs. Hence you need to
adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
first. A bit a mess, I know.

Cheers, Daniel

> +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>  		type = DRM_MODE_CONNECTOR_eDP;
>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>  	} else {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Daniel Vetter]

On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> > Eventhough Valleyview display block is derived from Cantiga, VLV
> > supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> > 
> > v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> > v3: fix DPIO value calculation to use same values for all display
> > 	interfaces
> > 
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
> >  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
> >  2 files changed, 14 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a8a81d1..aee6151 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >  		}
> >  	}
> >  
> > +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> > +		pipeconf |= PIPECONF_BPP_6 |
> > +			PIPECONF_ENABLE |
> > +			I965_PIPECONF_ACTIVE;
> > +	}
> 
> No.
> 
> Jani Nikula and me just figured out that we have a giant mess with 6bpc
> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> papers over issues.

Forgotten to put Jani on cc.
-Daniel

> 
> > +
> >  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
> >  	drm_mode_debug_printmodeline(mode);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index c111c3f..af57027 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> >  
> >  	/* Split out the IBX/CPU vs CPT settings */
> >  
> > -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> > +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> >  			intel_dp->DP |= DP_SYNC_HS_HIGH;
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> > @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  
> > -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> >  		case DP_TRAIN_VOLTAGE_SWING_400:
> >  			return DP_TRAIN_PRE_EMPHASIS_6;
> > @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >  		uint32_t    signal_levels;
> >  
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >  			break;
> >  		}
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> >  		if (intel_dpd_is_edp(dev))
> >  			intel_dp->is_pch_edp = true;
> >  
> > -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> > +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> > +		type = DRM_MODE_CONNECTOR_eDP;
> > +		intel_encoder->type = INTEL_OUTPUT_EDP;
> 
> You need to be a notch more careful, since since
> 
> commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
> Author: Adam Jackson <ajax@redhat.com>
> Date:   Fri Jul 16 14:46:29 2010 -0400
> 
>     drm/i915: Initialize LVDS and eDP outputs before anything else
> 
> We initialize built-in panels before external outputs. Hence you need to
> adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
> first. A bit a mess, I know.
> 
> Cheers, Daniel
> 
> > +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> >  		type = DRM_MODE_CONNECTOR_eDP;
> >  		intel_encoder->type = INTEL_OUTPUT_EDP;
> >  	} else {
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Vijay Purushothaman]

On 9/26/2012 8:19 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
>> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>>> Eventhough Valleyview display block is derived from Cantiga, VLV
>>> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
>>>
>>> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
>>> v3: fix DPIO value calculation to use same values for all display
>>> 	interfaces
>>>
>>> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
>>> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>>>   drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
>>>   2 files changed, 14 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index a8a81d1..aee6151 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>>   		}
>>>   	}
>>>
>>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>>> +		pipeconf |= PIPECONF_BPP_6 |
>>> +			PIPECONF_ENABLE |
>>> +			I965_PIPECONF_ACTIVE;
>>> +	}
>>
>> No.
>>
>> Jani Nikula and me just figured out that we have a giant mess with 6bpc
>> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
>> papers over issues.
>
> Forgotten to put Jani on cc.
> -Daniel

Thanks for the catch. I've removed this unconditional enabling of 6bpc 
for VLV eDP. For long term i believe, eDP handling in i9xx_crtc_mode_set 
should be changed along the lines of ironlake_crtc_mode_set for cleaner 
code. For now, this should unblock others with VLV enabling.

>
>>
>>> +
>>>   	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>>>   	drm_mode_debug_printmodeline(mode);
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index c111c3f..af57027 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>>>
>>>   	/* Split out the IBX/CPU vs CPT settings */
>>>
>>> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
>>> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>>>   		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>>>   			intel_dp->DP |= DP_SYNC_HS_HIGH;
>>>   		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>>> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>>   {
>>>   	struct drm_device *dev = intel_dp->base.base.dev;
>>>
>>> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>>   		case DP_TRAIN_VOLTAGE_SWING_400:
>>>   			return DP_TRAIN_PRE_EMPHASIS_6;
>>> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>>>   		uint32_t    signal_levels;
>>>
>>>
>>> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>>>   			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>>>   		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
>>> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>>>   			break;
>>>   		}
>>>
>>> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>>>   			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>>>   		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
>>> @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>>>   		if (intel_dpd_is_edp(dev))
>>>   			intel_dp->is_pch_edp = true;
>>>
>>> -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>>> +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
>>> +		type = DRM_MODE_CONNECTOR_eDP;
>>> +		intel_encoder->type = INTEL_OUTPUT_EDP;
>>
>> You need to be a notch more careful, since since
>>
>> commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
>> Author: Adam Jackson <ajax@redhat.com>
>> Date:   Fri Jul 16 14:46:29 2010 -0400
>>
>>      drm/i915: Initialize LVDS and eDP outputs before anything else
>>
>> We initialize built-in panels before external outputs. Hence you need to
>> adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
>> first. A bit a mess, I know.

I've changed the detection order in intel_setup_outputs for valleyview. 
In intel_dp_init, I have added a comment to fix this in next patch series.

Thanks,
Vijay

>>
>> Cheers, Daniel
>>
>>> +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>>>   		type = DRM_MODE_CONNECTOR_eDP;
>>>   		intel_encoder->type = INTEL_OUTPUT_EDP;
>>>   	} else {
>>> --
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
>

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Daniel Vetter]

On Thu, Sep 27, 2012 at 07:08:41PM +0530, Vijay Purushothaman wrote:
> On 9/26/2012 8:19 PM, Daniel Vetter wrote:
> >On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
> >>On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> >>>Eventhough Valleyview display block is derived from Cantiga, VLV
> >>>supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> >>>
> >>>v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> >>>v3: fix DPIO value calculation to use same values for all display
> >>>	interfaces
> >>>
> >>>Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> >>>Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> >>>Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> >>>---
> >>>  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
> >>>  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
> >>>  2 files changed, 14 insertions(+), 5 deletions(-)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>index a8a81d1..aee6151 100644
> >>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >>>  		}
> >>>  	}
> >>>
> >>>+	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> >>>+		pipeconf |= PIPECONF_BPP_6 |
> >>>+			PIPECONF_ENABLE |
> >>>+			I965_PIPECONF_ACTIVE;
> >>>+	}
> >>
> >>No.
> >>
> >>Jani Nikula and me just figured out that we have a giant mess with 6bpc
> >>dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> >>papers over issues.
> >
> >Forgotten to put Jani on cc.
> >-Daniel
> 
> Thanks for the catch. I've removed this unconditional enabling of
> 6bpc for VLV eDP. For long term i believe, eDP handling in
> i9xx_crtc_mode_set should be changed along the lines of
> ironlake_crtc_mode_set for cleaner code. For now, this should
> unblock others with VLV enabling.

My Big Plan (tm) for handling bpc, bandwidth, dotclocks and clocks in
general (e.g. pll sharing) is to move all this stuff out of the ->mode_set
callbacks and into a new preparation step at the beginning of the modeset
sequence (i.e. before we start touching the hw). Essentially I want to
extend the current ->mode_adjust callbacks and move all these calculations
in there. Aims for this are
- should allow us to move a lot of the encoder specific code that
  currently sits in the xxx_crtc_mode_set functions into encoder callbacks
- allows us to fail a modeset that won't work (e.g. due to pll sharing
  limits or fdi link bw limits) _before_ we touch the hw
- prepares for the global modeset stuff, where we want to make clever
  decision about shared resources (e.g. enable 6bpc dithering if there are
  not enough fdi lanes availbale in 3 pipe configs).

So the ironlake bpc code is a bit cleaner, but imho still gets it wrong.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Jani Nikula]

On Wed, 26 Sep 2012, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a8a81d1..aee6151 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>  		}
>>  	}
>>  
>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>> +		pipeconf |= PIPECONF_BPP_6 |
>> +			PIPECONF_ENABLE |
>> +			I965_PIPECONF_ACTIVE;
>> +	}
>
> No.
>
> Jani Nikula and me just figured out that we have a giant mess with 6bpc
> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> papers over issues.

Vijay, please check commit 0c96c65b in drm-intel-fixes.

BR,
Jani.

Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Vijay Purushothaman]

On 9/27/2012 12:48 PM, Jani Nikula wrote:
> On Wed, 26 Sep 2012, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index a8a81d1..aee6151 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>>   		}
>>>   	}
>>>
>>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>>> +		pipeconf |= PIPECONF_BPP_6 |
>>> +			PIPECONF_ENABLE |
>>> +			I965_PIPECONF_ACTIVE;
>>> +	}
>>
>> No.
>>
>> Jani Nikula and me just figured out that we have a giant mess with 6bpc
>> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
>> papers over issues.
>
> Vijay, please check commit 0c96c65b in drm-intel-fixes.
>
> BR,
> Jani.
>
Thanks Jani & Daniel for your review. I will send out the v2 of the 
patch set.

Thanks,
Vijay

>
>

[PATCH 7/9] drm/i915: panel power sequencing for VLV eDP

[Vijay Purushothaman]

PPS register offsets have changed in Valleyview.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    9 +++
 drivers/gpu/drm/i915/intel_dp.c |  122 +++++++++++++++++++++++++++------------
 2 files changed, 93 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..e421847 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3981,6 +3981,15 @@
 #define PIPEB_PP_ON_DELAYS      0x61308
 #define PIPEB_PP_OFF_DELAYS     0x6130c
 #define PIPEB_PP_DIVISOR        0x61310
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
 
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index af57027..b944529 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg;
 
-	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_ctrl_reg;
 
-	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 }
 
 static void
@@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
 	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 		WARN(1, "eDP powered off while attempting aux channel communication.\n");
 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS),
-			      I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 
 	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
-		      mask, value,
-		      I915_READ(PCH_PP_STATUS),
-		      I915_READ(PCH_PP_CONTROL));
+			mask, value,
+			I915_READ(pp_stat_reg),
+			I915_READ(pp_ctrl_reg));
 
-	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
-			  I915_READ(PCH_PP_STATUS),
-			  I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  * is locked
  */
 
-static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 {
-	u32	control = I915_READ(PCH_PP_CONTROL);
+	struct drm_device *dev = intel_dp->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 control;
+	u32 pp_ctrl_reg;
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	control = I915_READ(pp_ctrl_reg);
 
 	control &= ~PANEL_UNLOCK_MASK;
 	control |= PANEL_UNLOCK_REGS;
@@ -994,6 +1013,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1012,13 +1032,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	if (!ironlake_edp_have_panel_power(intel_dp))
 		ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_FORCE_VDD;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
-	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
+	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 	/*
 	 * If the panel wasn't on, delay before accessing aux channel
 	 */
@@ -1033,17 +1056,21 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
-		pp = ironlake_get_pp_control(dev_priv);
+		pp = ironlake_get_pp_control(intel_dp);
 		pp &= ~EDP_FORCE_VDD;
-		I915_WRITE(PCH_PP_CONTROL, pp);
-		POSTING_READ(PCH_PP_CONTROL);
 
-		/* Make sure sequencer is idle before allowing subsequent activity */
-		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 
+		I915_WRITE(pp_ctrl_reg, pp);
+		POSTING_READ(pp_ctrl_reg);
+
+		/* Make sure sequencer is idle before allowing subsequent activity */
+		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 		msleep(intel_dp->panel_power_down_delay);
 	}
 }
@@ -1087,6 +1114,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1100,7 +1128,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 
 	ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	if (IS_GEN5(dev)) {
 		/* ILK workaround: disable reset around power sequence */
 		pp &= ~PANEL_POWER_RESET;
@@ -1112,8 +1140,10 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	if (!IS_GEN5(dev))
 		pp |= PANEL_POWER_RESET;
 
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	ironlake_wait_panel_on(intel_dp);
 
@@ -1129,6 +1159,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1137,12 +1168,15 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 
 	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	/* We need to switch off panel power _and_ force vdd, for otherwise some
 	 * panels get very unhappy and cease to work. */
 	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	intel_dp->want_panel_vdd = false;
 
@@ -1154,6 +1188,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1166,10 +1201,13 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	 * allowing it to appear.
 	 */
 	msleep(intel_dp->backlight_on_delay);
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 }
 
 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
@@ -1177,15 +1215,17 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
 
 	DRM_DEBUG_KMS("\n");
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp &= ~EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 	msleep(intel_dp->backlight_off_delay);
 }
 
@@ -2543,9 +2583,15 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		u32 pp_on, pp_off, pp_div;
 		struct edid *edid;
 
-		pp_on = I915_READ(PCH_PP_ON_DELAYS);
-		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
-		pp_div = I915_READ(PCH_PP_DIVISOR);
+		if (IS_VALLEYVIEW(dev)) {
+			pp_on = I915_READ(PIPEA_PP_ON_DELAYS);
+			pp_off = I915_READ(PIPEA_PP_OFF_DELAYS);
+			pp_div = I915_READ(PIPEA_PP_DIVISOR);
+		} else {
+			pp_on = I915_READ(PCH_PP_ON_DELAYS);
+			pp_off = I915_READ(PCH_PP_OFF_DELAYS);
+			pp_div = I915_READ(PCH_PP_DIVISOR);
+		}
 
 		if (!pp_on || !pp_off || !pp_div) {
 			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
-- 
1.7.9.5

Re: [PATCH 7/9] drm/i915: panel power sequencing for VLV eDP

[Daniel Vetter]

On Wed, Sep 26, 2012 at 07:07:36PM +0530, Vijay Purushothaman wrote:
> PPS register offsets have changed in Valleyview.
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>

I have a feeling that we need to add some panel power sequencer
abstraction, especially if we want to support the 2nd panel power sequence
on vlv, too. I'm trying to volunteer some of the Helsinki guys here to
brush up Chris' panel refactoring (which combines lvds and edp panel
handling a bit), that would fit in. But for now this quick&dirty way looks
good enough.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h |    9 +++
>  drivers/gpu/drm/i915/intel_dp.c |  122 +++++++++++++++++++++++++++------------
>  2 files changed, 93 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f75ee6..e421847 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3981,6 +3981,15 @@
>  #define PIPEB_PP_ON_DELAYS      0x61308
>  #define PIPEB_PP_OFF_DELAYS     0x6130c
>  #define PIPEB_PP_DIVISOR        0x61310
> +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe) \
> +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> +
>  
>  #define PCH_PP_STATUS		0xc7200
>  #define PCH_PP_CONTROL		0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index af57027..b944529 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -316,16 +316,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg;
>  
> -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
>  }
>  
>  static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_ctrl_reg;
>  
> -	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
>  }
>  
>  static void
> @@ -333,14 +337,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> +
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
>  	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
>  		WARN(1, "eDP powered off while attempting aux channel communication.\n");
>  		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
> -			      I915_READ(PCH_PP_STATUS),
> -			      I915_READ(PCH_PP_CONTROL));
> +				I915_READ(pp_stat_reg),
> +				I915_READ(pp_ctrl_reg));
>  	}
>  }
>  
> @@ -944,16 +953,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg, pp_ctrl_reg;
> +
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>  
>  	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
> -		      mask, value,
> -		      I915_READ(PCH_PP_STATUS),
> -		      I915_READ(PCH_PP_CONTROL));
> +			mask, value,
> +			I915_READ(pp_stat_reg),
> +			I915_READ(pp_ctrl_reg));
>  
> -	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
> +	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
>  		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
> -			  I915_READ(PCH_PP_STATUS),
> -			  I915_READ(PCH_PP_CONTROL));
> +				I915_READ(pp_stat_reg),
> +				I915_READ(pp_ctrl_reg));
>  	}
>  }
>  
> @@ -980,9 +993,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
>   * is locked
>   */
>  
> -static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
> +static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
>  {
> -	u32	control = I915_READ(PCH_PP_CONTROL);
> +	struct drm_device *dev = intel_dp->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 control;
> +	u32 pp_ctrl_reg;
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	control = I915_READ(pp_ctrl_reg);
>  
>  	control &= ~PANEL_UNLOCK_MASK;
>  	control |= PANEL_UNLOCK_REGS;
> @@ -994,6 +1013,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1012,13 +1032,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
>  	if (!ironlake_edp_have_panel_power(intel_dp))
>  		ironlake_wait_panel_power_cycle(intel_dp);
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp |= EDP_FORCE_VDD;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> -	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> -		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
>  
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
> +	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> +			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  	/*
>  	 * If the panel wasn't on, delay before accessing aux channel
>  	 */
> @@ -1033,17 +1056,21 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_stat_reg, pp_ctrl_reg;
>  
>  	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
> -		pp = ironlake_get_pp_control(dev_priv);
> +		pp = ironlake_get_pp_control(intel_dp);
>  		pp &= ~EDP_FORCE_VDD;
> -		I915_WRITE(PCH_PP_CONTROL, pp);
> -		POSTING_READ(PCH_PP_CONTROL);
>  
> -		/* Make sure sequencer is idle before allowing subsequent activity */
> -		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> -			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
> +		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> +		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>  
> +		I915_WRITE(pp_ctrl_reg, pp);
> +		POSTING_READ(pp_ctrl_reg);
> +
> +		/* Make sure sequencer is idle before allowing subsequent activity */
> +		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> +		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  		msleep(intel_dp->panel_power_down_delay);
>  	}
>  }
> @@ -1087,6 +1114,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1100,7 +1128,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  
>  	ironlake_wait_panel_power_cycle(intel_dp);
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	if (IS_GEN5(dev)) {
>  		/* ILK workaround: disable reset around power sequence */
>  		pp &= ~PANEL_POWER_RESET;
> @@ -1112,8 +1140,10 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  	if (!IS_GEN5(dev))
>  		pp |= PANEL_POWER_RESET;
>  
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  
>  	ironlake_wait_panel_on(intel_dp);
>  
> @@ -1129,6 +1159,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1137,12 +1168,15 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>  
>  	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
>  
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	/* We need to switch off panel power _and_ force vdd, for otherwise some
>  	 * panels get very unhappy and cease to work. */
>  	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  
>  	intel_dp->want_panel_vdd = false;
>  
> @@ -1154,6 +1188,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -1166,10 +1201,13 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>  	 * allowing it to appear.
>  	 */
>  	msleep(intel_dp->backlight_on_delay);
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp |= EDP_BLC_ENABLE;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  }
>  
>  static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> @@ -1177,15 +1215,17 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> +	u32 pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
>  
>  	DRM_DEBUG_KMS("\n");
> -	pp = ironlake_get_pp_control(dev_priv);
> +	pp = ironlake_get_pp_control(intel_dp);
>  	pp &= ~EDP_BLC_ENABLE;
> -	I915_WRITE(PCH_PP_CONTROL, pp);
> -	POSTING_READ(PCH_PP_CONTROL);
> +	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +	I915_WRITE(pp_ctrl_reg, pp);
> +	POSTING_READ(pp_ctrl_reg);
>  	msleep(intel_dp->backlight_off_delay);
>  }
>  
> @@ -2543,9 +2583,15 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  		u32 pp_on, pp_off, pp_div;
>  		struct edid *edid;
>  
> -		pp_on = I915_READ(PCH_PP_ON_DELAYS);
> -		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> -		pp_div = I915_READ(PCH_PP_DIVISOR);
> +		if (IS_VALLEYVIEW(dev)) {
> +			pp_on = I915_READ(PIPEA_PP_ON_DELAYS);
> +			pp_off = I915_READ(PIPEA_PP_OFF_DELAYS);
> +			pp_div = I915_READ(PIPEA_PP_DIVISOR);
> +		} else {
> +			pp_on = I915_READ(PCH_PP_ON_DELAYS);
> +			pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> +			pp_div = I915_READ(PCH_PP_DIVISOR);
> +		}
>  
>  		if (!pp_on || !pp_off || !pp_div) {
>  			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 8/9] drm/i915: Reverse min, max vco limits for VLV HDMI

[Vijay Purushothaman]

Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 +-
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e421847..d4ed30e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3687,7 +3687,7 @@
 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
-#define VLV_VIDEO_DIP_CTL_A		0x60220
+#define VLV_VIDEO_DIP_CTL_A		0x60200
 #define VLV_VIDEO_DIP_DATA_A		0x60208
 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aee6151..647e311 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
 
 static const intel_limit_t intel_limits_vlv_hdmi = {
 	.dot = { .min = 20000, .max = 165000 },
-	.vco = { .min = 5994000, .max = 4000000 },
+	.vco = { .min = 4000000, .max = 5994000},
 	.n = { .min = 1, .max = 7 },
 	.m = { .min = 60, .max = 300 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
-- 
1.7.9.5

Re: [PATCH 8/9] drm/i915: Reverse min, max vco limits for VLV HDMI

[Daniel Vetter]

On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
> Fixed min, max vco limits for VLV HDMI. Also fixed correct register
> offset for VLV_VIDEO_DIP_CTL_A
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>

Patch splitup bikeshed: Either split up the dip reg fix into its own
patch, or make the commit headline more generic (e.g "fixup HDMI output on
vlv") with the details of the fix ("fixup vco limits and dip ctl reg") in
the commit message. I'll bikeshed the headline when applying.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    2 +-
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e421847..d4ed30e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3687,7 +3687,7 @@
>  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
> -#define VLV_VIDEO_DIP_CTL_A		0x60220
> +#define VLV_VIDEO_DIP_CTL_A		0x60200
>  #define VLV_VIDEO_DIP_DATA_A		0x60208
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index aee6151..647e311 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
>  
>  static const intel_limit_t intel_limits_vlv_hdmi = {
>  	.dot = { .min = 20000, .max = 165000 },
> -	.vco = { .min = 5994000, .max = 4000000 },
> +	.vco = { .min = 4000000, .max = 5994000},
>  	.n = { .min = 1, .max = 7 },
>  	.m = { .min = 60, .max = 300 }, /* guess */
>  	.m1 = { .min = 2, .max = 3 },
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 8/9] drm/i915: Reverse min, max vco limits for VLV HDMI

[Vijay Purushothaman]

On 9/26/2012 8:08 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
>> Fixed min, max vco limits for VLV HDMI. Also fixed correct register
>> offset for VLV_VIDEO_DIP_CTL_A
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
>> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>
> Patch splitup bikeshed: Either split up the dip reg fix into its own
> patch, or make the commit headline more generic (e.g "fixup HDMI output on
> vlv") with the details of the fix ("fixup vco limits and dip ctl reg") in
> the commit message. I'll bikeshed the headline when applying.
> -Daniel
>

I will change the commit headline. Thanks.

>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |    2 +-
>>   drivers/gpu/drm/i915/intel_display.c |    2 +-
>>   2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e421847..d4ed30e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3687,7 +3687,7 @@
>>   #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>>   #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>>
>> -#define VLV_VIDEO_DIP_CTL_A		0x60220
>> +#define VLV_VIDEO_DIP_CTL_A		0x60200
>>   #define VLV_VIDEO_DIP_DATA_A		0x60208
>>   #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index aee6151..647e311 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -380,7 +380,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
>>
>>   static const intel_limit_t intel_limits_vlv_hdmi = {
>>   	.dot = { .min = 20000, .max = 165000 },
>> -	.vco = { .min = 5994000, .max = 4000000 },
>> +	.vco = { .min = 4000000, .max = 5994000},
>>   	.n = { .min = 1, .max = 7 },
>>   	.m = { .min = 60, .max = 300 }, /* guess */
>>   	.m1 = { .min = 2, .max = 3 },
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

[PATCH 9/9] drm/i915: Enable multi display support in VLV

[Vijay Purushothaman]

From: "Bhat, Gajanan" <gajanan.bhat@intel.com>

Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    8 +--
 drivers/gpu/drm/i915/intel_display.c |  105 ++++++++++++++++++----------------
 2 files changed, 58 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ed30e..71aa0a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
-#define _DPIO_DATA_LANE0		0x0220
-#define _DPIO_DATA_LANE1		0x0420
-#define _DPIO_DATA_LANE2		0x2620
-#define _DPIO_DATA_LANE3		0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1		0x8220
+#define DPIO_DATA_CHANNEL2		0x8420
 
 /*
  * Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 647e311..e933031 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
 }
 
 static void vlv_update_pll(struct drm_crtc *crtc,
-			   struct drm_display_mode *mode,
-			   struct drm_display_mode *adjusted_mode,
-			   intel_clock_t *clock, intel_clock_t *reduced_clock,
-			   int refclk, int num_connectors)
+			    struct drm_display_mode *mode,
+			    struct drm_display_mode *adjusted_mode,
+			    intel_clock_t *clock, intel_clock_t *reduced_clock,
+			    int num_connectors)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 dpll, mdiv, pdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	bool is_hdmi;
+	bool is_sdvo;
+	u32 temp;
 
-	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+	dpll = DPLL_VGA_MODE_DIS;
+	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
 
 	bestn = clock->n;
 	bestm1 = clock->m1;
@@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	bestp1 = clock->p1;
 	bestp2 = clock->p2;
 
-	/* Enable DPIO clock input */
-	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
-		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
-
+	/*
+	 * In Valleyview PLL and program lane counter registes are exposed
+	 * through DPIO interface
+	 */
 	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
@@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("DPLL %d failed to lock\n", pipe);
 
-	if (is_hdmi) {
-		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
 
+	temp = 0;
+	if (is_sdvo) {
+		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
 		if (temp > 1)
 			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		else
 			temp = 0;
-
-		I915_WRITE(DPLL_MD(pipe), temp);
-		POSTING_READ(DPLL_MD(pipe));
 	}
+	I915_WRITE(DPLL_MD(pipe), temp);
+	POSTING_READ(DPLL_MD(pipe));
 
-	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+	/* Now program lane control registers */
+	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
+			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+	{
+		temp = 0x1000C4;
+		if(pipe == 1)
+			temp |= (1 << 21);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
+	}
+	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
+	{
+		temp = 0x1000C4;
+		if(pipe == 1)
+			temp |= (1 << 21);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
+	}
 }
 
+
 static void i9xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode,
@@ -4096,10 +4130,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 dpll;
 	bool is_sdvo;
-
 	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
 		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
-
 	dpll = DPLL_VGA_MODE_DIS;
 
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
@@ -4117,12 +4149,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 		dpll |= DPLL_DVO_HIGH_SPEED;
 
-	if (IS_VALLEYVIEW(dev)) {
-		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
-		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
-		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
-	}
-
 	/* compute bitmask from p1 value */
 	if (IS_PINEVIEW(dev))
 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
@@ -4164,18 +4190,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
 
-	/*
-	 * In Valleyview PLL and program lane counter registes are exposed
-	 * through DPIO interface
-	 */
-	if (IS_VALLEYVIEW(dev)) {
-		int refclk;
-		refclk = i9xx_get_refclk(crtc, num_connectors);
-		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
-			num_connectors);
-	}
-	udelay(150);
-
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
 	 * things on.
@@ -4192,17 +4206,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
-	/* Now program lane control registers for Valleyview */
-	if (IS_VALLEYVIEW(dev)) {
-		u32 temp = 0;
-		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
-		temp |= (1 << 20);
-		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
-		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
-		temp |= (1 << 20);
-		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
-	}
-
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 temp = 0;
 		if (is_sdvo) {
@@ -4365,6 +4368,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (IS_GEN2(dev))
 		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
+	else if (IS_VALLEYVIEW(dev))
+		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
+				has_reduced_clock ? &reduced_clock : NULL,
+				num_connectors);
 	else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
-- 
1.7.9.5

Re: [PATCH 9/9] drm/i915: Enable multi display support in VLV

[Daniel Vetter]

On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
> From: "Bhat, Gajanan" <gajanan.bhat@intel.com>
> 
> Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
> programming to vlv_update_pll function. With all the changes multi
> display (clone, extended desktop) should work for VLV.
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>

I guess this patch will look much better once we don't disable the
vlv_update_pll function in between (and apply my other suggestion to move
i9xx_update_pll_divisors into the !vlv pll functions).
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    8 +--
>  drivers/gpu/drm/i915/intel_display.c |  105 ++++++++++++++++++----------------
>  2 files changed, 58 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4ed30e..71aa0a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -385,12 +385,8 @@
>  
>  #define DPIO_FASTCLK_DISABLE		0x8100
>  
> -#define _DPIO_DATA_LANE0		0x0220
> -#define _DPIO_DATA_LANE1		0x0420
> -#define _DPIO_DATA_LANE2		0x2620
> -#define _DPIO_DATA_LANE3		0x2820
> -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> +#define DPIO_DATA_CHANNEL1		0x8220
> +#define DPIO_DATA_CHANNEL2		0x8420
>  
>  /*
>   * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 647e311..e933031 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
>  }
>  
>  static void vlv_update_pll(struct drm_crtc *crtc,
> -			   struct drm_display_mode *mode,
> -			   struct drm_display_mode *adjusted_mode,
> -			   intel_clock_t *clock, intel_clock_t *reduced_clock,
> -			   int refclk, int num_connectors)
> +			    struct drm_display_mode *mode,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
> +			    int num_connectors)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll, mdiv, pdiv;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> -	bool is_hdmi;
> +	bool is_sdvo;
> +	u32 temp;
>  
> -	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> +	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> +	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +	POSTING_READ(DPLL(pipe));
>  
>  	bestn = clock->n;
>  	bestm1 = clock->m1;
> @@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	bestp1 = clock->p1;
>  	bestp2 = clock->p2;
>  
> -	/* Enable DPIO clock input */
> -	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> -		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
> -	I915_WRITE(DPLL(pipe), dpll);
> -	POSTING_READ(DPLL(pipe));
> -
> +	/*
> +	 * In Valleyview PLL and program lane counter registes are exposed
> +	 * through DPIO interface
> +	 */
>  	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
>  	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>  	mdiv |= ((bestn << DPIO_N_SHIFT));
> @@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>  		DRM_ERROR("DPLL %d failed to lock\n", pipe);
>  
> -	if (is_hdmi) {
> -		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
>  
> +	temp = 0;
> +	if (is_sdvo) {
> +		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>  		if (temp > 1)
>  			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  		else
>  			temp = 0;
> -
> -		I915_WRITE(DPLL_MD(pipe), temp);
> -		POSTING_READ(DPLL_MD(pipe));
>  	}
> +	I915_WRITE(DPLL_MD(pipe), temp);
> +	POSTING_READ(DPLL_MD(pipe));
>  
> -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> +	/* Now program lane control registers */
> +	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
> +			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> +	{
> +		temp = 0x1000C4;
> +		if(pipe == 1)
> +			temp |= (1 << 21);
> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
> +	}
> +	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
> +	{
> +		temp = 0x1000C4;
> +		if(pipe == 1)
> +			temp |= (1 << 21);
> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
> +	}
>  }
>  
> +
>  static void i9xx_update_pll(struct drm_crtc *crtc,
>  			    struct drm_display_mode *mode,
>  			    struct drm_display_mode *adjusted_mode,
> @@ -4096,10 +4130,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll;
>  	bool is_sdvo;
> -
>  	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>  		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> -
>  	dpll = DPLL_VGA_MODE_DIS;
>  
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> @@ -4117,12 +4149,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>  		dpll |= DPLL_DVO_HIGH_SPEED;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> -		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> -		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> -		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> -	}
> -
>  	/* compute bitmask from p1 value */
>  	if (IS_PINEVIEW(dev))
>  		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> @@ -4164,18 +4190,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
>  	POSTING_READ(DPLL(pipe));
>  
> -	/*
> -	 * In Valleyview PLL and program lane counter registes are exposed
> -	 * through DPIO interface
> -	 */
> -	if (IS_VALLEYVIEW(dev)) {
> -		int refclk;
> -		refclk = i9xx_get_refclk(crtc, num_connectors);
> -		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
> -			num_connectors);
> -	}
> -	udelay(150);
> -
>  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>  	 * This is an exception to the general rule that mode_set doesn't turn
>  	 * things on.
> @@ -4192,17 +4206,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	POSTING_READ(DPLL(pipe));
>  	udelay(150);
>  
> -	/* Now program lane control registers for Valleyview */
> -	if (IS_VALLEYVIEW(dev)) {
> -		u32 temp = 0;
> -		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
> -		temp |= (1 << 20);
> -		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
> -		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
> -		temp |= (1 << 20);
> -		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
> -	}
> -
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		u32 temp = 0;
>  		if (is_sdvo) {
> @@ -4365,6 +4368,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	if (IS_GEN2(dev))
>  		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> +	else if (IS_VALLEYVIEW(dev))
> +		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  	else
>  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>  				has_reduced_clock ? &reduced_clock : NULL,
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 9/9] drm/i915: Enable multi display support in VLV

[Vijay Purushothaman]

On 9/26/2012 8:10 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
>> From: "Bhat, Gajanan" <gajanan.bhat@intel.com>
>>
>> Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
>> programming to vlv_update_pll function. With all the changes multi
>> display (clone, extended desktop) should work for VLV.
>>
>> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>
> I guess this patch will look much better once we don't disable the
> vlv_update_pll function in between (and apply my other suggestion to move
> i9xx_update_pll_divisors into the !vlv pll functions).
> -Daniel

I've merged patch 5 and 9 and took care of your suggestions.

Thanks,
Vijay

>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |    8 +--
>>   drivers/gpu/drm/i915/intel_display.c |  105 ++++++++++++++++++----------------
>>   2 files changed, 58 insertions(+), 55 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d4ed30e..71aa0a7 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -385,12 +385,8 @@
>>
>>   #define DPIO_FASTCLK_DISABLE		0x8100
>>
>> -#define _DPIO_DATA_LANE0		0x0220
>> -#define _DPIO_DATA_LANE1		0x0420
>> -#define _DPIO_DATA_LANE2		0x2620
>> -#define _DPIO_DATA_LANE3		0x2820
>> -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
>> -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
>> +#define DPIO_DATA_CHANNEL1		0x8220
>> +#define DPIO_DATA_CHANNEL2		0x8420
>>
>>   /*
>>    * Fence registers
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 647e311..e933031 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
>>   }
>>
>>   static void vlv_update_pll(struct drm_crtc *crtc,
>> -			   struct drm_display_mode *mode,
>> -			   struct drm_display_mode *adjusted_mode,
>> -			   intel_clock_t *clock, intel_clock_t *reduced_clock,
>> -			   int refclk, int num_connectors)
>> +			    struct drm_display_mode *mode,
>> +			    struct drm_display_mode *adjusted_mode,
>> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
>> +			    int num_connectors)
>>   {
>>   	struct drm_device *dev = crtc->dev;
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>> @@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>>   	int pipe = intel_crtc->pipe;
>>   	u32 dpll, mdiv, pdiv;
>>   	u32 bestn, bestm1, bestm2, bestp1, bestp2;
>> -	bool is_hdmi;
>> +	bool is_sdvo;
>> +	u32 temp;
>>
>> -	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> +
>> +	dpll = DPLL_VGA_MODE_DIS;
>> +	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
>> +	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
>> +	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
>> +
>> +	I915_WRITE(DPLL(pipe), dpll);
>> +	POSTING_READ(DPLL(pipe));
>>
>>   	bestn = clock->n;
>>   	bestm1 = clock->m1;
>> @@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>>   	bestp1 = clock->p1;
>>   	bestp2 = clock->p2;
>>
>> -	/* Enable DPIO clock input */
>> -	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
>> -		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
>> -	I915_WRITE(DPLL(pipe), dpll);
>> -	POSTING_READ(DPLL(pipe));
>> -
>> +	/*
>> +	 * In Valleyview PLL and program lane counter registes are exposed
>> +	 * through DPIO interface
>> +	 */
>>   	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
>>   	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>>   	mdiv |= ((bestn << DPIO_N_SHIFT));
>> @@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>>   	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>>   		DRM_ERROR("DPLL %d failed to lock\n", pipe);
>>
>> -	if (is_hdmi) {
>> -		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>> +
>> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
>> +
>> +	I915_WRITE(DPLL(pipe), dpll);
>> +
>> +	/* Wait for the clocks to stabilize. */
>> +	POSTING_READ(DPLL(pipe));
>> +	udelay(150);
>>
>> +	temp = 0;
>> +	if (is_sdvo) {
>> +		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>>   		if (temp > 1)
>>   			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>>   		else
>>   			temp = 0;
>> -
>> -		I915_WRITE(DPLL_MD(pipe), temp);
>> -		POSTING_READ(DPLL_MD(pipe));
>>   	}
>> +	I915_WRITE(DPLL_MD(pipe), temp);
>> +	POSTING_READ(DPLL_MD(pipe));
>>
>> -	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>> +	/* Now program lane control registers */
>> +	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
>> +			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
>> +	{
>> +		temp = 0x1000C4;
>> +		if(pipe == 1)
>> +			temp |= (1 << 21);
>> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
>> +	}
>> +	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
>> +	{
>> +		temp = 0x1000C4;
>> +		if(pipe == 1)
>> +			temp |= (1 << 21);
>> +		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
>> +	}
>>   }
>>
>> +
>>   static void i9xx_update_pll(struct drm_crtc *crtc,
>>   			    struct drm_display_mode *mode,
>>   			    struct drm_display_mode *adjusted_mode,
>> @@ -4096,10 +4130,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	int pipe = intel_crtc->pipe;
>>   	u32 dpll;
>>   	bool is_sdvo;
>> -
>>   	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>>   		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> -
>>   	dpll = DPLL_VGA_MODE_DIS;
>>
>>   	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
>> @@ -4117,12 +4149,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>>   		dpll |= DPLL_DVO_HIGH_SPEED;
>>
>> -	if (IS_VALLEYVIEW(dev)) {
>> -		dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
>> -		dpll |= DPLL_REFA_CLK_ENABLE_VLV;
>> -		dpll |= DPLL_INTEGRATED_CLOCK_VLV;
>> -	}
>> -
>>   	/* compute bitmask from p1 value */
>>   	if (IS_PINEVIEW(dev))
>>   		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
>> @@ -4164,18 +4190,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
>>   	POSTING_READ(DPLL(pipe));
>>
>> -	/*
>> -	 * In Valleyview PLL and program lane counter registes are exposed
>> -	 * through DPIO interface
>> -	 */
>> -	if (IS_VALLEYVIEW(dev)) {
>> -		int refclk;
>> -		refclk = i9xx_get_refclk(crtc, num_connectors);
>> -		vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
>> -			num_connectors);
>> -	}
>> -	udelay(150);
>> -
>>   	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>>   	 * This is an exception to the general rule that mode_set doesn't turn
>>   	 * things on.
>> @@ -4192,17 +4206,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>>   	POSTING_READ(DPLL(pipe));
>>   	udelay(150);
>>
>> -	/* Now program lane control registers for Valleyview */
>> -	if (IS_VALLEYVIEW(dev)) {
>> -		u32 temp = 0;
>> -		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
>> -		temp |= (1 << 20);
>> -		intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
>> -		temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
>> -		temp |= (1 << 20);
>> -		intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
>> -	}
>> -
>>   	if (INTEL_INFO(dev)->gen >= 4) {
>>   		u32 temp = 0;
>>   		if (is_sdvo) {
>> @@ -4365,6 +4368,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>
>>   	if (IS_GEN2(dev))
>>   		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>> +	else if (IS_VALLEYVIEW(dev))
>> +		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
>> +				has_reduced_clock ? &reduced_clock : NULL,
>> +				num_connectors);
>>   	else
>>   		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>>   				has_reduced_clock ? &reduced_clock : NULL,
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>