From: Mitch Bradley <wmb@firmworks.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Grant Likely <grant.likely@secretlab.ca>,
linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org,
Rob Herring <rob.herring@calxeda.com>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: pci and pcie device-tree binding - range No cells
Date: Mon, 10 Dec 2012 13:11:38 -1000 [thread overview]
Message-ID: <50C66C2A.7010102@firmworks.com> (raw)
In-Reply-To: <1355179097.19932.5.camel@pasglop>
On 12/10/2012 12:38 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2012-12-10 at 21:43 +0000, Grant Likely wrote:
>>> Sorry for my pci ignorance (have never got hw for mb/zynq)
>>> I just want to get better overview how we should we our drivers to
>> be compatible.
>>>
>>> Does it mean that pci is supposed be always 64 bit wide?
>>> And there is no option to have just 32bit values.
>>
>> Yes, PCIe addressing is always 64 bits wide. Even on 32bit PCI systems
>> we use 64 bit PCI addressing in the device tree.
>
> Right. The size & format of an address cell for PCI is specified in the
> OF PCI bindings and we follow that binding. It's always 3 cells.
.. and the reason why it must be 3 cells, even if the host PCI bus only
supports 32-bit addressing, is because a plug-in PCI card has no way of
knowing what the host supports.
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
WARNING: multiple messages have this Message-ID (diff)
From: Mitch Bradley <wmb@firmworks.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Rob Herring <rob.herring@calxeda.com>
Subject: Re: pci and pcie device-tree binding - range No cells
Date: Mon, 10 Dec 2012 13:11:38 -1000 [thread overview]
Message-ID: <50C66C2A.7010102@firmworks.com> (raw)
In-Reply-To: <1355179097.19932.5.camel@pasglop>
On 12/10/2012 12:38 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2012-12-10 at 21:43 +0000, Grant Likely wrote:
>>> Sorry for my pci ignorance (have never got hw for mb/zynq)
>>> I just want to get better overview how we should we our drivers to
>> be compatible.
>>>
>>> Does it mean that pci is supposed be always 64 bit wide?
>>> And there is no option to have just 32bit values.
>>
>> Yes, PCIe addressing is always 64 bits wide. Even on 32bit PCI systems
>> we use 64 bit PCI addressing in the device tree.
>
> Right. The size & format of an address cell for PCI is specified in the
> OF PCI bindings and we follow that binding. It's always 3 cells.
.. and the reason why it must be 3 cells, even if the host PCI bus only
supports 32-bit addressing, is because a plug-in PCI card has no way of
knowing what the host supports.
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
WARNING: multiple messages have this Message-ID (diff)
From: Mitch Bradley <wmb-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org>
To: Benjamin Herrenschmidt
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linuxppc-dev
<linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Subject: Re: pci and pcie device-tree binding - range No cells
Date: Mon, 10 Dec 2012 13:11:38 -1000 [thread overview]
Message-ID: <50C66C2A.7010102@firmworks.com> (raw)
In-Reply-To: <1355179097.19932.5.camel@pasglop>
On 12/10/2012 12:38 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2012-12-10 at 21:43 +0000, Grant Likely wrote:
>>> Sorry for my pci ignorance (have never got hw for mb/zynq)
>>> I just want to get better overview how we should we our drivers to
>> be compatible.
>>>
>>> Does it mean that pci is supposed be always 64 bit wide?
>>> And there is no option to have just 32bit values.
>>
>> Yes, PCIe addressing is always 64 bits wide. Even on 32bit PCI systems
>> we use 64 bit PCI addressing in the device tree.
>
> Right. The size & format of an address cell for PCI is specified in the
> OF PCI bindings and we follow that binding. It's always 3 cells.
.. and the reason why it must be 3 cells, even if the host PCI bus only
supports 32-bit addressing, is because a plug-in PCI card has no way of
knowing what the host supports.
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
next prev parent reply other threads:[~2012-12-10 23:12 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-10 12:20 pci and pcie device-tree binding - range No cells Michal Simek
2012-12-10 14:26 ` Rob Herring
2012-12-10 14:26 ` Rob Herring
2012-12-10 15:05 ` Michal Simek
2012-12-10 15:05 ` Michal Simek
2012-12-10 15:21 ` Rob Herring
2012-12-10 15:21 ` Rob Herring
2012-12-10 15:37 ` Michal Simek
2012-12-10 15:37 ` Michal Simek
2012-12-10 15:52 ` David Laight
2012-12-10 15:52 ` David Laight
2012-12-10 15:52 ` David Laight
2012-12-10 16:05 ` Michal Simek
2012-12-10 16:05 ` Michal Simek
2012-12-10 17:15 ` Thomas Petazzoni
2012-12-10 17:15 ` Thomas Petazzoni
2012-12-10 23:24 ` Rob Herring
2012-12-10 23:24 ` Rob Herring
2012-12-12 16:16 ` Thomas Petazzoni
2012-12-12 16:16 ` Thomas Petazzoni
2012-12-12 17:22 ` Grant Likely
2012-12-12 17:22 ` Grant Likely
2012-12-12 17:29 ` Rob Herring
2012-12-12 17:29 ` Rob Herring
2012-12-10 16:02 ` Rob Herring
2012-12-10 16:02 ` Rob Herring
2012-12-10 16:11 ` Michal Simek
2012-12-10 16:11 ` Michal Simek
2012-12-10 21:43 ` Grant Likely
2012-12-10 21:43 ` Grant Likely
2012-12-10 22:38 ` Benjamin Herrenschmidt
2012-12-10 22:38 ` Benjamin Herrenschmidt
2012-12-10 23:11 ` Mitch Bradley [this message]
2012-12-10 23:11 ` Mitch Bradley
2012-12-10 23:11 ` Mitch Bradley
2012-12-10 21:41 ` Grant Likely
2012-12-10 21:41 ` Grant Likely
2012-12-12 10:37 ` Michal Simek
2012-12-12 10:37 ` Michal Simek
2012-12-12 10:49 ` Grant Likely
2012-12-12 10:49 ` Grant Likely
[not found] ` <CAPcvp5EJH-Q6wd7my+V+FUVE1=hzwMN-yOfHiukGvDmkcoRcsQ@mail.gmail.com>
2012-12-12 12:19 ` Andrew Murray
2012-12-12 12:19 ` Andrew Murray
2012-12-12 13:34 ` Thierry Reding
2012-12-12 13:34 ` Thierry Reding
2012-12-12 16:44 ` Andrew Murray
2012-12-12 16:44 ` Andrew Murray
2012-12-12 16:55 ` Michal Simek
2012-12-12 16:55 ` Michal Simek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=50C66C2A.7010102@firmworks.com \
--to=wmb@firmworks.com \
--cc=benh@kernel.crashing.org \
--cc=devicetree-discuss@lists.ozlabs.org \
--cc=grant.likely@secretlab.ca \
--cc=linux-pci@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=rob.herring@calxeda.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.