From: Santosh Shilimkar <santosh.shilimkar@ti.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"tony@atomide.com" <tony@atomide.com>,
Rajendra Nayak <rnayak@ti.com>, Benoit Cousson <b-cousson@ti.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 5/5] ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Date: Sat, 19 Jan 2013 00:21:22 +0530 [thread overview]
Message-ID: <50F999AA.2020901@ti.com> (raw)
In-Reply-To: <50F98176.6070703@arm.com>
On Friday 18 January 2013 10:38 PM, Marc Zyngier wrote:
> On 18/01/13 17:00, Santosh Shilimkar wrote:
>> On Friday 18 January 2013 09:32 PM, Marc Zyngier wrote:
>>> On 18/01/13 15:32, Santosh Shilimkar wrote:
>>>> From: Rajendra Nayak <rnayak@ti.com>
>>>>
>>>> Specify both secure as well as nonsecure PPI IRQ for arch
>>>> timer. This fixes the following errors seen on DT OMAP5 boot..
>>>>
>>>> [ 0.000000] arch_timer: No interrupt available, giving up
>>>>
>>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>>>
>>>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> ---
>>>> arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++----
>>>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>>>> index 790bb2a..7a78d1b 100644
>>>> --- a/arch/arm/boot/dts/omap5.dtsi
>>>> +++ b/arch/arm/boot/dts/omap5.dtsi
>>>> @@ -35,8 +35,12 @@
>>>> compatible = "arm,cortex-a15";
>>>> timer {
>>>> compatible = "arm,armv7-timer";
>>>> - /* 14th PPI IRQ, active low level-sensitive */
>>>> - interrupts = <1 14 0x308>;
>>>> + /*
>>>> + * PPI secure/nonsecure IRQ,
>>>> + * active low level-sensitive
>>>> + */
>>>> + interrupts = <1 13 0x308>,
>>>> + <1 14 0x308>;
>>>
>>> Care to add the virtual and HYP timer interrupts? So KVM can get a
>>> chance to run on this HW...
>>>
>> Thanks Marc for spotting it. Will take care of it.
>
> I just realised something silly... You have one timer node *per cpu*,
> and this is not really expected.
>
This was discussed on the list here [1]
Benoit suggested to add per CPU node since arch timer is per
CPU and DT should describe the hw the way it is. Did we miss
something ?
> The driver really wants one single node. See
> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts for an example.
>
I remember adding only one node based on above file and then
updating the patch based on the comment.
> Oh, and your GIC node could do with some updating too (no VGIC regs or
> interrupt).
>
Will have a look at that as well.
Regards
Santosh,
[1] https://patchwork.kernel.org/patch/1312061/
WARNING: multiple messages have this Message-ID (diff)
From: santosh.shilimkar@ti.com (Santosh Shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Date: Sat, 19 Jan 2013 00:21:22 +0530 [thread overview]
Message-ID: <50F999AA.2020901@ti.com> (raw)
In-Reply-To: <50F98176.6070703@arm.com>
On Friday 18 January 2013 10:38 PM, Marc Zyngier wrote:
> On 18/01/13 17:00, Santosh Shilimkar wrote:
>> On Friday 18 January 2013 09:32 PM, Marc Zyngier wrote:
>>> On 18/01/13 15:32, Santosh Shilimkar wrote:
>>>> From: Rajendra Nayak <rnayak@ti.com>
>>>>
>>>> Specify both secure as well as nonsecure PPI IRQ for arch
>>>> timer. This fixes the following errors seen on DT OMAP5 boot..
>>>>
>>>> [ 0.000000] arch_timer: No interrupt available, giving up
>>>>
>>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>>>
>>>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> ---
>>>> arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++----
>>>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>>>> index 790bb2a..7a78d1b 100644
>>>> --- a/arch/arm/boot/dts/omap5.dtsi
>>>> +++ b/arch/arm/boot/dts/omap5.dtsi
>>>> @@ -35,8 +35,12 @@
>>>> compatible = "arm,cortex-a15";
>>>> timer {
>>>> compatible = "arm,armv7-timer";
>>>> - /* 14th PPI IRQ, active low level-sensitive */
>>>> - interrupts = <1 14 0x308>;
>>>> + /*
>>>> + * PPI secure/nonsecure IRQ,
>>>> + * active low level-sensitive
>>>> + */
>>>> + interrupts = <1 13 0x308>,
>>>> + <1 14 0x308>;
>>>
>>> Care to add the virtual and HYP timer interrupts? So KVM can get a
>>> chance to run on this HW...
>>>
>> Thanks Marc for spotting it. Will take care of it.
>
> I just realised something silly... You have one timer node *per cpu*,
> and this is not really expected.
>
This was discussed on the list here [1]
Benoit suggested to add per CPU node since arch timer is per
CPU and DT should describe the hw the way it is. Did we miss
something ?
> The driver really wants one single node. See
> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts for an example.
>
I remember adding only one node based on above file and then
updating the patch based on the comment.
> Oh, and your GIC node could do with some updating too (no VGIC regs or
> interrupt).
>
Will have a look at that as well.
Regards
Santosh,
[1] https://patchwork.kernel.org/patch/1312061/
next prev parent reply other threads:[~2013-01-18 18:50 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-18 15:32 [PATCH 0/5] ARM: OMAP5: Misc fixes Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-18 15:32 ` [PATCH 1/5] ARM: OMAP5: Update SOC id detection code for ES2 Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-18 15:32 ` [PATCH 2/5] ARM: OMAP2+: timer: Update the OMAP5 clocksource name as per clock data Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-30 17:42 ` Jon Hunter
2013-01-30 17:42 ` Jon Hunter
2013-01-18 15:32 ` [PATCH 3/5] ARM: OMAP: prm: Allow prm init to success on OMAP5 SOCs Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-18 15:32 ` [PATCH 4/5] ARM: dts: omap5-evm: Update available memory to 2032 MB Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-18 15:32 ` [PATCH 5/5] ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer Santosh Shilimkar
2013-01-18 15:32 ` Santosh Shilimkar
2013-01-18 16:02 ` Marc Zyngier
2013-01-18 16:02 ` Marc Zyngier
2013-01-18 17:00 ` Santosh Shilimkar
2013-01-18 17:00 ` Santosh Shilimkar
2013-01-18 17:08 ` Marc Zyngier
2013-01-18 17:08 ` Marc Zyngier
2013-01-18 18:51 ` Santosh Shilimkar [this message]
2013-01-18 18:51 ` Santosh Shilimkar
2013-01-19 14:46 ` Marc Zyngier
2013-01-19 14:46 ` Marc Zyngier
2013-01-19 17:26 ` Santosh Shilimkar
2013-01-19 17:26 ` Santosh Shilimkar
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