From: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
"linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
"devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org"
<devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
Date: Mon, 4 Feb 2013 11:36:47 +0530 [thread overview]
Message-ID: <510F4FF7.3050502@nvidia.com> (raw)
In-Reply-To: <1359713962-16822-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Refactor the PLL programming code to make it useable by the new PLL types
> introduced by Tegra114.
>
> The following changes were done:
>
> * Split programming the PLL into updating m,n,p and updating cpcon
> * Move locking from _update_pll_cpcon() to clk_pll_set_rate()
> * Introduce _get_pll_mnp() helper
> * Move check for identical m,n,p values to clk_pll_set_rate()
> * struct tegra_clk_pll_freq_table will always contain the values as defined
> by the hardware.
> * Simplify the arguments to clk_pll_wait_for_lock()
>
> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-pll.c | 178 +++++++++++++++++------------
> drivers/clk/tegra/clk-tegra20.c | 144 ++++++++++++------------
> drivers/clk/tegra/clk-tegra30.c | 234 +++++++++++++++++++-------------------
> 3 files changed, 294 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 165f247..912c977 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> pll_writel_misc(val, pll);
> }
>
> -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> - void __iomem *lock_addr, u32 lock_bit_idx)
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
> {
> int i;
> - u32 val;
> + u32 val, lock_bit;
> + void __iomem *lock_addr;
>
> if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> udelay(pll->params->lock_delay);
> return 0;
> }
>
> + lock_addr = pll->clk_base + pll->params->base_reg;
This will not work for PLLE. Lock bit for PLLE is in misc register.
> + lock_bit = BIT(pll->params->lock_bit_idx);
> +
> for (i = 0; i < pll->params->lock_delay; i++) {
> val = readl_relaxed(lock_addr);
> - if (val & BIT(lock_bit_idx)) {
> + if (val & lock_bit) {
Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.
> udelay(PLL_POST_LOCK_DELAY);
> return 0;
> }
> @@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
> return val & PLL_BASE_ENABLE ? 1 : 0;
> }
<snip>
> @@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
> val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> pll_writel_base(val, pll);
>
> - clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
> - pll->params->lock_bit_idx);
> + clk_pll_wait_for_lock(pll);
> +
> return 0;
> }
<snip>
> static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
> /* 1.7 GHz */
> - { 12000000, 1700000000, 850, 6, 1, 8},
> - { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
> - { 26000000, 1700000000, 850, 13, 1, 8},
> + { 12000000, 1700000000, 850, 6, 0, 8},
> + { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
> + { 26000000, 1700000000, 850, 13, 0, 8},
>
> /* 1.6 GHz */
> - { 12000000, 1600000000, 800, 6, 1, 8},
> - { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
> - { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
> - { 19200000, 1600000000, 500, 6, 1, 8},
> - { 26000000, 1600000000, 800, 13, 1, 8},
> + { 12000000, 1600000000, 800, 6, 0, 8},
> + { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
> + { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
> + { 19200000, 1600000000, 500, 6, 0, 8},
> + { 26000000, 1600000000, 800, 13, 0, 8},
>
> /* 1.5 GHz */
> - { 12000000, 1500000000, 750, 6, 1, 8},
> - { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
> - { 16800000, 1500000000, 625, 7, 1, 8},
> - { 19200000, 1500000000, 625, 8, 1, 8},
> - { 26000000, 1500000000, 750, 13, 1, 8},
> + { 12000000, 1500000000, 750, 6, 0, 8},
> + { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
> + { 16800000, 1500000000, 625, 7, 0, 8},
> + { 19200000, 1500000000, 625, 8, 0, 8},
> + { 26000000, 1500000000, 750, 13, 0, 8},
>
> /* 1.4 GHz */
> - { 12000000, 1400000000, 700, 6, 1, 8},
> - { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
> - { 16800000, 1400000000, 1000, 12, 1, 8},
> - { 19200000, 1400000000, 875, 12, 1, 8},
> - { 26000000, 1400000000, 700, 13, 1, 8},
> + { 12000000, 1400000000, 700, 6, 0, 8},
> + { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
> + { 16800000, 1400000000, 1000, 12, 0, 8},
> + { 19200000, 1400000000, 875, 12, 0, 8},
> + { 26000000, 1400000000, 700, 13, 0, 8},
>
> /* 1.3 GHz */
> - { 12000000, 1300000000, 975, 9, 1, 8},
> - { 13000000, 1300000000, 1000, 10, 1, 8},
> - { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 26000000, 1300000000, 650, 13, 1, 8},
> + { 12000000, 1300000000, 975, 9, 0, 8},
> + { 13000000, 1300000000, 1000, 10, 0, 8},
> + { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 26000000, 1300000000, 650, 13, 0, 8},
>
> /* 1.2 GHz */
> - { 12000000, 1200000000, 1000, 10, 1, 8},
> - { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
> - { 16800000, 1200000000, 1000, 14, 1, 8},
> - { 19200000, 1200000000, 1000, 16, 1, 8},
> - { 26000000, 1200000000, 600, 13, 1, 8},
> + { 12000000, 1200000000, 1000, 10, 0, 8},
> + { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
> + { 16800000, 1200000000, 1000, 14, 0, 8},
> + { 19200000, 1200000000, 1000, 16, 0, 8},
> + { 26000000, 1200000000, 600, 13, 0, 8},
>
> /* 1.1 GHz */
> - { 12000000, 1100000000, 825, 9, 1, 8},
> - { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
> - { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
> - { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
> - { 26000000, 1100000000, 550, 13, 1, 8},
> + { 12000000, 1100000000, 825, 9, 0, 8},
> + { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
> + { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
> + { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
> + { 26000000, 1100000000, 550, 13, 0, 8},
>
> /* 1 GHz */
> - { 12000000, 1000000000, 1000, 12, 1, 8},
> - { 13000000, 1000000000, 1000, 13, 1, 8},
> - { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
> - { 19200000, 1000000000, 625, 12, 1, 8},
> - { 26000000, 1000000000, 1000, 26, 1, 8},
> + { 12000000, 1000000000, 1000, 12, 0, 8},
> + { 13000000, 1000000000, 1000, 13, 0, 8},
> + { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
> + { 19200000, 1000000000, 625, 12, 0, 8},
> + { 26000000, 1000000000, 1000, 26, 0, 8},
>
> { 0, 0, 0, 0, 0, 0 },
> };
>
WARNING: multiple messages have this Message-ID (diff)
From: pgaikwad@nvidia.com (Prashant Gaikwad)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
Date: Mon, 4 Feb 2013 11:36:47 +0530 [thread overview]
Message-ID: <510F4FF7.3050502@nvidia.com> (raw)
In-Reply-To: <1359713962-16822-2-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Refactor the PLL programming code to make it useable by the new PLL types
> introduced by Tegra114.
>
> The following changes were done:
>
> * Split programming the PLL into updating m,n,p and updating cpcon
> * Move locking from _update_pll_cpcon() to clk_pll_set_rate()
> * Introduce _get_pll_mnp() helper
> * Move check for identical m,n,p values to clk_pll_set_rate()
> * struct tegra_clk_pll_freq_table will always contain the values as defined
> by the hardware.
> * Simplify the arguments to clk_pll_wait_for_lock()
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 178 +++++++++++++++++------------
> drivers/clk/tegra/clk-tegra20.c | 144 ++++++++++++------------
> drivers/clk/tegra/clk-tegra30.c | 234 +++++++++++++++++++-------------------
> 3 files changed, 294 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 165f247..912c977 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> pll_writel_misc(val, pll);
> }
>
> -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> - void __iomem *lock_addr, u32 lock_bit_idx)
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
> {
> int i;
> - u32 val;
> + u32 val, lock_bit;
> + void __iomem *lock_addr;
>
> if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> udelay(pll->params->lock_delay);
> return 0;
> }
>
> + lock_addr = pll->clk_base + pll->params->base_reg;
This will not work for PLLE. Lock bit for PLLE is in misc register.
> + lock_bit = BIT(pll->params->lock_bit_idx);
> +
> for (i = 0; i < pll->params->lock_delay; i++) {
> val = readl_relaxed(lock_addr);
> - if (val & BIT(lock_bit_idx)) {
> + if (val & lock_bit) {
Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.
> udelay(PLL_POST_LOCK_DELAY);
> return 0;
> }
> @@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
> return val & PLL_BASE_ENABLE ? 1 : 0;
> }
<snip>
> @@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
> val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> pll_writel_base(val, pll);
>
> - clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
> - pll->params->lock_bit_idx);
> + clk_pll_wait_for_lock(pll);
> +
> return 0;
> }
<snip>
> static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
> /* 1.7 GHz */
> - { 12000000, 1700000000, 850, 6, 1, 8},
> - { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
> - { 26000000, 1700000000, 850, 13, 1, 8},
> + { 12000000, 1700000000, 850, 6, 0, 8},
> + { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
> + { 26000000, 1700000000, 850, 13, 0, 8},
>
> /* 1.6 GHz */
> - { 12000000, 1600000000, 800, 6, 1, 8},
> - { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
> - { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
> - { 19200000, 1600000000, 500, 6, 1, 8},
> - { 26000000, 1600000000, 800, 13, 1, 8},
> + { 12000000, 1600000000, 800, 6, 0, 8},
> + { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
> + { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
> + { 19200000, 1600000000, 500, 6, 0, 8},
> + { 26000000, 1600000000, 800, 13, 0, 8},
>
> /* 1.5 GHz */
> - { 12000000, 1500000000, 750, 6, 1, 8},
> - { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
> - { 16800000, 1500000000, 625, 7, 1, 8},
> - { 19200000, 1500000000, 625, 8, 1, 8},
> - { 26000000, 1500000000, 750, 13, 1, 8},
> + { 12000000, 1500000000, 750, 6, 0, 8},
> + { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
> + { 16800000, 1500000000, 625, 7, 0, 8},
> + { 19200000, 1500000000, 625, 8, 0, 8},
> + { 26000000, 1500000000, 750, 13, 0, 8},
>
> /* 1.4 GHz */
> - { 12000000, 1400000000, 700, 6, 1, 8},
> - { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
> - { 16800000, 1400000000, 1000, 12, 1, 8},
> - { 19200000, 1400000000, 875, 12, 1, 8},
> - { 26000000, 1400000000, 700, 13, 1, 8},
> + { 12000000, 1400000000, 700, 6, 0, 8},
> + { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
> + { 16800000, 1400000000, 1000, 12, 0, 8},
> + { 19200000, 1400000000, 875, 12, 0, 8},
> + { 26000000, 1400000000, 700, 13, 0, 8},
>
> /* 1.3 GHz */
> - { 12000000, 1300000000, 975, 9, 1, 8},
> - { 13000000, 1300000000, 1000, 10, 1, 8},
> - { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 26000000, 1300000000, 650, 13, 1, 8},
> + { 12000000, 1300000000, 975, 9, 0, 8},
> + { 13000000, 1300000000, 1000, 10, 0, 8},
> + { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 26000000, 1300000000, 650, 13, 0, 8},
>
> /* 1.2 GHz */
> - { 12000000, 1200000000, 1000, 10, 1, 8},
> - { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
> - { 16800000, 1200000000, 1000, 14, 1, 8},
> - { 19200000, 1200000000, 1000, 16, 1, 8},
> - { 26000000, 1200000000, 600, 13, 1, 8},
> + { 12000000, 1200000000, 1000, 10, 0, 8},
> + { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
> + { 16800000, 1200000000, 1000, 14, 0, 8},
> + { 19200000, 1200000000, 1000, 16, 0, 8},
> + { 26000000, 1200000000, 600, 13, 0, 8},
>
> /* 1.1 GHz */
> - { 12000000, 1100000000, 825, 9, 1, 8},
> - { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
> - { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
> - { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
> - { 26000000, 1100000000, 550, 13, 1, 8},
> + { 12000000, 1100000000, 825, 9, 0, 8},
> + { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
> + { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
> + { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
> + { 26000000, 1100000000, 550, 13, 0, 8},
>
> /* 1 GHz */
> - { 12000000, 1000000000, 1000, 12, 1, 8},
> - { 13000000, 1000000000, 1000, 13, 1, 8},
> - { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
> - { 19200000, 1000000000, 625, 12, 1, 8},
> - { 26000000, 1000000000, 1000, 26, 1, 8},
> + { 12000000, 1000000000, 1000, 12, 0, 8},
> + { 13000000, 1000000000, 1000, 13, 0, 8},
> + { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
> + { 19200000, 1000000000, 625, 12, 0, 8},
> + { 26000000, 1000000000, 1000, 26, 0, 8},
>
> { 0, 0, 0, 0, 0, 0 },
> };
>
WARNING: multiple messages have this Message-ID (diff)
From: Prashant Gaikwad <pgaikwad@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Grant Likely <grant.likely@secretlab.ca>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>,
Stephen Warren <swarren@wwwdotorg.org>,
Russell King <linux@arm.linux.org.uk>,
Simon Glass <sjg@chromium.org>,
Mike Turquette <mturquette@linaro.org>,
Joseph Lo <josephl@nvidia.com>,
"devicetree-discuss@lists.ozlabs.org"
<devicetree-discuss@lists.ozlabs.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
Date: Mon, 4 Feb 2013 11:36:47 +0530 [thread overview]
Message-ID: <510F4FF7.3050502@nvidia.com> (raw)
In-Reply-To: <1359713962-16822-2-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Refactor the PLL programming code to make it useable by the new PLL types
> introduced by Tegra114.
>
> The following changes were done:
>
> * Split programming the PLL into updating m,n,p and updating cpcon
> * Move locking from _update_pll_cpcon() to clk_pll_set_rate()
> * Introduce _get_pll_mnp() helper
> * Move check for identical m,n,p values to clk_pll_set_rate()
> * struct tegra_clk_pll_freq_table will always contain the values as defined
> by the hardware.
> * Simplify the arguments to clk_pll_wait_for_lock()
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 178 +++++++++++++++++------------
> drivers/clk/tegra/clk-tegra20.c | 144 ++++++++++++------------
> drivers/clk/tegra/clk-tegra30.c | 234 +++++++++++++++++++-------------------
> 3 files changed, 294 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 165f247..912c977 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> pll_writel_misc(val, pll);
> }
>
> -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> - void __iomem *lock_addr, u32 lock_bit_idx)
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
> {
> int i;
> - u32 val;
> + u32 val, lock_bit;
> + void __iomem *lock_addr;
>
> if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> udelay(pll->params->lock_delay);
> return 0;
> }
>
> + lock_addr = pll->clk_base + pll->params->base_reg;
This will not work for PLLE. Lock bit for PLLE is in misc register.
> + lock_bit = BIT(pll->params->lock_bit_idx);
> +
> for (i = 0; i < pll->params->lock_delay; i++) {
> val = readl_relaxed(lock_addr);
> - if (val & BIT(lock_bit_idx)) {
> + if (val & lock_bit) {
Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.
> udelay(PLL_POST_LOCK_DELAY);
> return 0;
> }
> @@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
> return val & PLL_BASE_ENABLE ? 1 : 0;
> }
<snip>
> @@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
> val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> pll_writel_base(val, pll);
>
> - clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
> - pll->params->lock_bit_idx);
> + clk_pll_wait_for_lock(pll);
> +
> return 0;
> }
<snip>
> static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
> /* 1.7 GHz */
> - { 12000000, 1700000000, 850, 6, 1, 8},
> - { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
> - { 26000000, 1700000000, 850, 13, 1, 8},
> + { 12000000, 1700000000, 850, 6, 0, 8},
> + { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
> + { 26000000, 1700000000, 850, 13, 0, 8},
>
> /* 1.6 GHz */
> - { 12000000, 1600000000, 800, 6, 1, 8},
> - { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
> - { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
> - { 19200000, 1600000000, 500, 6, 1, 8},
> - { 26000000, 1600000000, 800, 13, 1, 8},
> + { 12000000, 1600000000, 800, 6, 0, 8},
> + { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
> + { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
> + { 19200000, 1600000000, 500, 6, 0, 8},
> + { 26000000, 1600000000, 800, 13, 0, 8},
>
> /* 1.5 GHz */
> - { 12000000, 1500000000, 750, 6, 1, 8},
> - { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
> - { 16800000, 1500000000, 625, 7, 1, 8},
> - { 19200000, 1500000000, 625, 8, 1, 8},
> - { 26000000, 1500000000, 750, 13, 1, 8},
> + { 12000000, 1500000000, 750, 6, 0, 8},
> + { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
> + { 16800000, 1500000000, 625, 7, 0, 8},
> + { 19200000, 1500000000, 625, 8, 0, 8},
> + { 26000000, 1500000000, 750, 13, 0, 8},
>
> /* 1.4 GHz */
> - { 12000000, 1400000000, 700, 6, 1, 8},
> - { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
> - { 16800000, 1400000000, 1000, 12, 1, 8},
> - { 19200000, 1400000000, 875, 12, 1, 8},
> - { 26000000, 1400000000, 700, 13, 1, 8},
> + { 12000000, 1400000000, 700, 6, 0, 8},
> + { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
> + { 16800000, 1400000000, 1000, 12, 0, 8},
> + { 19200000, 1400000000, 875, 12, 0, 8},
> + { 26000000, 1400000000, 700, 13, 0, 8},
>
> /* 1.3 GHz */
> - { 12000000, 1300000000, 975, 9, 1, 8},
> - { 13000000, 1300000000, 1000, 10, 1, 8},
> - { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 26000000, 1300000000, 650, 13, 1, 8},
> + { 12000000, 1300000000, 975, 9, 0, 8},
> + { 13000000, 1300000000, 1000, 10, 0, 8},
> + { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 26000000, 1300000000, 650, 13, 0, 8},
>
> /* 1.2 GHz */
> - { 12000000, 1200000000, 1000, 10, 1, 8},
> - { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
> - { 16800000, 1200000000, 1000, 14, 1, 8},
> - { 19200000, 1200000000, 1000, 16, 1, 8},
> - { 26000000, 1200000000, 600, 13, 1, 8},
> + { 12000000, 1200000000, 1000, 10, 0, 8},
> + { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
> + { 16800000, 1200000000, 1000, 14, 0, 8},
> + { 19200000, 1200000000, 1000, 16, 0, 8},
> + { 26000000, 1200000000, 600, 13, 0, 8},
>
> /* 1.1 GHz */
> - { 12000000, 1100000000, 825, 9, 1, 8},
> - { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
> - { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
> - { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
> - { 26000000, 1100000000, 550, 13, 1, 8},
> + { 12000000, 1100000000, 825, 9, 0, 8},
> + { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
> + { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
> + { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
> + { 26000000, 1100000000, 550, 13, 0, 8},
>
> /* 1 GHz */
> - { 12000000, 1000000000, 1000, 12, 1, 8},
> - { 13000000, 1000000000, 1000, 13, 1, 8},
> - { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
> - { 19200000, 1000000000, 625, 12, 1, 8},
> - { 26000000, 1000000000, 1000, 26, 1, 8},
> + { 12000000, 1000000000, 1000, 12, 0, 8},
> + { 13000000, 1000000000, 1000, 13, 0, 8},
> + { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
> + { 19200000, 1000000000, 625, 12, 0, 8},
> + { 26000000, 1000000000, 1000, 26, 0, 8},
>
> { 0, 0, 0, 0, 0, 0 },
> };
>
next prev parent reply other threads:[~2013-02-04 6:06 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-01 10:18 [PATCH v5 00/10] Tegra114 clockframework Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-01 10:18 ` [PATCH v5 01/10] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 6:06 ` Prashant Gaikwad [this message]
2013-02-04 6:06 ` Prashant Gaikwad
2013-02-04 6:06 ` Prashant Gaikwad
2013-02-04 14:32 ` Peter De Schrijver
2013-02-04 14:32 ` Peter De Schrijver
2013-02-05 5:42 ` Prashant Gaikwad
2013-02-05 5:42 ` Prashant Gaikwad
[not found] ` <51109BB3.8000706-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-05 13:23 ` Peter De Schrijver
2013-02-05 13:23 ` Peter De Schrijver
2013-02-05 13:23 ` Peter De Schrijver
[not found] ` <20130205132355.GD3073-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-02-06 12:32 ` Peter De Schrijver
2013-02-06 12:32 ` Peter De Schrijver
2013-02-06 12:32 ` Peter De Schrijver
2013-02-04 21:57 ` Stephen Warren
2013-02-04 21:57 ` Stephen Warren
2013-02-04 21:57 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-3-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 6:13 ` Prashant Gaikwad
2013-02-04 6:13 ` Prashant Gaikwad
2013-02-04 6:13 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-01 19:40 ` Rhyland Klein
2013-02-01 19:40 ` Rhyland Klein
2013-02-01 19:40 ` Rhyland Klein
[not found] ` <510C1A2E.5010408-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 6:35 ` Prashant Gaikwad
2013-02-04 6:35 ` Prashant Gaikwad
2013-02-04 6:35 ` Prashant Gaikwad
[not found] ` <510F56B1.5060409-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 10:37 ` Peter De Schrijver
2013-02-04 10:37 ` Peter De Schrijver
2013-02-04 10:37 ` Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-6-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 6:33 ` Prashant Gaikwad
2013-02-04 6:33 ` Prashant Gaikwad
2013-02-04 6:33 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-04 6:39 ` Prashant Gaikwad
2013-02-04 6:39 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 07/10] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-04 21:16 ` Stephen Warren
2013-02-04 21:16 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-04 6:45 ` Prashant Gaikwad
2013-02-04 6:45 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia,tegra114-car Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia, tegra114-car Peter De Schrijver
2013-02-04 7:10 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia,tegra114-car Prashant Gaikwad
2013-02-04 7:10 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia, tegra114-car Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 03/10] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
[not found] ` <1359713962-16822-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 6:28 ` Prashant Gaikwad
2013-02-04 6:28 ` Prashant Gaikwad
2013-02-04 6:28 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-01 10:18 ` Peter De Schrijver
2013-02-04 7:08 ` Prashant Gaikwad
2013-02-04 7:08 ` Prashant Gaikwad
[not found] ` <510F5E87.90801-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-04 10:45 ` Peter De Schrijver
2013-02-04 10:45 ` Peter De Schrijver
2013-02-04 10:45 ` Peter De Schrijver
[not found] ` <20130204104531.GQ2364-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-02-04 14:07 ` Peter De Schrijver
2013-02-04 14:07 ` Peter De Schrijver
2013-02-04 14:07 ` Peter De Schrijver
2013-02-04 21:01 ` Stephen Warren
2013-02-04 21:01 ` Stephen Warren
2013-02-07 16:18 ` Peter De Schrijver
2013-02-07 16:18 ` Peter De Schrijver
2013-02-04 14:34 ` Peter De Schrijver
2013-02-04 14:34 ` Peter De Schrijver
[not found] ` <20130204143401.GW2364-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-02-05 5:36 ` Prashant Gaikwad
2013-02-05 5:36 ` Prashant Gaikwad
2013-02-05 5:36 ` Prashant Gaikwad
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=510F4FF7.3050502@nvidia.com \
--to=pgaikwad-ddmlm1+adcrqt0dzr+alfa@public.gmane.org \
--cc=devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org \
--cc=josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org \
--cc=linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org \
--cc=pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \
--cc=rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.