* [Qemu-devel] [RFC PATCH 8/8] exec: Make ldl_*_phys input an AddressSpace
2013-11-22 15:15 [Qemu-devel] [RFC PATCH 0/8] Steps towards per CPU address-spaces edgar.iglesias
` (6 preceding siblings ...)
2013-11-22 15:15 ` [Qemu-devel] [RFC PATCH 7/8] exec: On AS changes, only flush affected CPU TLBs edgar.iglesias
@ 2013-11-22 15:15 ` edgar.iglesias
7 siblings, 0 replies; 13+ messages in thread
From: edgar.iglesias @ 2013-11-22 15:15 UTC (permalink / raw)
To: qemu-devel
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
cpu-exec.c | 5 +-
exec.c | 19 ++++---
hw/dma/pl080.c | 9 ++--
hw/dma/sun4m_iommu.c | 3 +-
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 8 +--
hw/s390x/css.c | 3 +-
hw/s390x/s390-virtio-bus.c | 2 +-
hw/s390x/virtio-ccw.c | 5 +-
hw/scsi/megasas.c | 4 +-
hw/scsi/vmw_pvscsi.c | 3 +-
hw/virtio/virtio.c | 3 +-
include/exec/cpu-common.h | 6 +--
include/hw/ppc/spapr.h | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 8 +--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 12 ++---
target-i386/arch_memory_mapping.c | 36 ++++++-------
target-i386/helper.c | 8 +--
target-i386/seg_helper.c | 4 +-
target-i386/smm_helper.c | 102 +++++++++++++++++++------------------
target-i386/svm_helper.c | 26 +++++-----
target-ppc/excp_helper.c | 2 +-
target-ppc/mmu-hash32.h | 4 +-
target-s390x/cpu.c | 2 +-
target-sparc/ldst_helper.c | 6 +--
target-sparc/mmu_helper.c | 18 +++----
target-unicore32/softmmu.c | 4 +-
target-xtensa/helper.c | 2 +-
30 files changed, 163 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..8f6766b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -374,7 +374,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
- intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
+ intno = ldl_phys(env->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+ control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index f273a46..ba67f98 100644
--- a/exec.c
+++ b/exec.c
@@ -1490,7 +1490,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
- case 4: return ldl_phys(addr);
+ case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2216,7 +2216,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2225,8 +2225,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+ mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2259,19 +2258,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 35b9015..58556f3 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
- ch->src = ldl_le_phys(ch->lli);
- ch->dest = ldl_le_phys(ch->lli + 4);
- ch->ctrl = ldl_le_phys(ch->lli + 12);
- ch->lli = ldl_le_phys(ch->lli + 8);
+ ch->src = ldl_le_phys(&address_space_memory, ch->lli);
+ ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
+ ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
+ ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
} else {
ch->conf &= ~PL080_CCONF_E;
}
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4m_iommu.c
index a04409a..723f66d 100644
--- a/hw/dma/sun4m_iommu.c
+++ b/hw/dma/sun4m_iommu.c
@@ -24,6 +24,7 @@
#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#include "trace.h"
/*
@@ -262,7 +263,7 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
- ret = ldl_be_phys(iopte);
+ ret = ldl_be_phys(&address_space_memory, iopte);
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
return ret;
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 5307e2c..b465eb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -95,7 +95,7 @@ vmw_shmem_st16(hwaddr addr, uint16_t value)
static inline uint32_t
vmw_shmem_ld32(hwaddr addr)
{
- uint32_t res = ldl_le_phys(addr);
+ uint32_t res = ldl_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f755a53..8ba2c3f 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -397,7 +397,7 @@ static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(env->as, addr + 0x4);
if (size < 0x8) {
return H_PARAMETER;
}
@@ -432,7 +432,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(env->as, addr + 0x4);
if (size < 48) {
return H_PARAMETER;
@@ -543,7 +543,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = lduw_phys(addr);
return H_SUCCESS;
case 4:
- args[0] = ldl_phys(addr);
+ args[0] = ldl_phys(cpu->env.as, addr);
return H_SUCCESS;
case 8:
args[0] = ldq_phys(addr);
@@ -611,7 +611,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = lduw_phys(src);
break;
case 2:
- tmp = ldl_phys(src);
+ tmp = ldl_phys(cpu->env.as, src);
break;
case 3:
tmp = ldq_phys(src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 101da63..41b1903 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -11,6 +11,7 @@
#include <hw/qdev.h>
#include "qemu/bitops.h"
+#include "exec/address-spaces.h"
#include "cpu.h"
#include "ioinst.h"
#include "css.h"
@@ -667,7 +668,7 @@ static void css_update_chnmon(SubchDev *sch)
/* Format 1, per-subchannel area. */
uint32_t count;
- count = ldl_phys(sch->curr_status.mba);
+ count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
stl_phys(sch->curr_status.mba, count);
} else {
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 6a83111..7c28fd7 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -409,7 +409,7 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
/* Update guest supported feature bitmap */
- features = bswap32(ldl_be_phys(dev->feat_offs));
+ features = bswap32(ldl_be_phys(&address_space_memory, dev->feat_offs));
virtio_set_features(vdev, features);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index f93a81c..7f6e131 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -259,7 +259,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
info.queue = ldq_phys(ccw.cda);
- info.align = ldl_phys(ccw.cda + sizeof(info.queue));
+ info.align = ldl_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
info.num = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -316,7 +317,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
features.index = ldub_phys(ccw.cda + sizeof(features.features));
- features.features = ldl_le_phys(ccw.cda);
+ features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
dev->vdev->guest_features = features.features;
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 7c5a1a2..a655980 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -602,8 +602,8 @@ static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
pa_lo = le32_to_cpu(initq->pi_addr_lo);
pa_hi = le32_to_cpu(initq->pi_addr_hi);
s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
- s->reply_queue_head = ldl_le_phys(s->producer_pa);
- s->reply_queue_tail = ldl_le_phys(s->consumer_pa);
+ s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
+ s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
flags = le32_to_cpu(initq->flags);
if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
s->flags |= MEGASAS_MASK_USE_QUEUE64;
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 94b328f..6cc6c1b 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -43,7 +43,8 @@
(sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
#define RS_GET_FIELD(rs_pa, field) \
- (ldl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field)))
+ (ldl_le_phys(&address_space_memory, \
+ rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
(stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 2f1e73b..0dceb5b 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -14,6 +14,7 @@
#include <inttypes.h>
#include "trace.h"
+#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/virtio/virtio.h"
#include "qemu/atomic.h"
@@ -111,7 +112,7 @@ static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
- return ldl_phys(pa);
+ return ldl_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index e4996e1..2f5626a 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -86,8 +86,8 @@ void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
-uint32_t ldl_le_phys(hwaddr addr);
-uint32_t ldl_be_phys(hwaddr addr);
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(hwaddr addr);
uint64_t ldq_be_phys(hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
@@ -100,7 +100,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
-uint32_t ldl_phys(hwaddr addr);
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index fdaab2d..aec756e 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -339,7 +339,7 @@ static inline uint64_t ppc64_phys_to_real(uint64_t addr)
static inline uint32_t rtas_ld(target_ulong phys, int n)
{
- return ldl_be_phys(ppc64_phys_to_real(phys + 4*n));
+ return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
}
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 5a0e78c..3977702 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -101,7 +101,7 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
-DEF_HELPER_1(ldl_phys, i64, i64)
+DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_1(ldq_phys, i64, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 7160a1c..5887052 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -24,9 +24,9 @@
/* Softmmu support */
#ifndef CONFIG_USER_ONLY
-uint64_t helper_ldl_phys(uint64_t p)
+uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
{
- return (int32_t)ldl_phys(p);
+ return (int32_t)ldl_phys(env->as, p);
}
uint64_t helper_ldq_phys(uint64_t p)
@@ -37,7 +37,7 @@ uint64_t helper_ldq_phys(uint64_t p)
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
{
env->lock_addr = p;
- return env->lock_value = (int32_t)ldl_phys(p);
+ return env->lock_value = (int32_t)ldl_phys(env->as, p);
}
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
@@ -61,7 +61,7 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
uint64_t ret = 0;
if (p == env->lock_addr) {
- int32_t old = ldl_phys(p);
+ int32_t old = ldl_phys(env->as, p);
if (old == (int32_t)env->lock_value) {
stl_phys(p, v);
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1155e86..802c49a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2912,7 +2912,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- gen_helper_ldl_phys(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3445813..7c6bb31 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2226,7 +2226,7 @@ static void v7m_push(CPUARMState *env, uint32_t val)
static uint32_t v7m_pop(CPUARMState *env)
{
uint32_t val;
- val = ldl_phys(env->regs[13]);
+ val = ldl_phys(env->as, env->regs[13]);
env->regs[13] += 4;
return val;
}
@@ -2381,7 +2381,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
- addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
+ addr = ldl_phys(env->as, env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
@@ -2598,7 +2598,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
@@ -2629,7 +2629,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -2695,7 +2695,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -2737,7 +2737,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
}
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c
index 462f984..132be93 100644
--- a/target-i386/arch_memory_mapping.c
+++ b/target-i386/arch_memory_mapping.c
@@ -16,7 +16,8 @@
#include "sysemu/memory_mapping.h"
/* PAE Paging or IA-32e Paging */
-static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
+static void walk_pte(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pte_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pte_addr, start_paddr;
@@ -45,7 +46,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
}
/* 32-bit Paging */
-static void walk_pte2(MemoryMappingList *list,
+static void walk_pte2(MemoryMappingList *list, AddressSpace *as,
hwaddr pte_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -56,7 +57,7 @@ static void walk_pte2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pte_addr = (pte_start_addr + i * 4) & a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -77,7 +78,8 @@ static void walk_pte2(MemoryMappingList *list,
/* PAE Paging or IA-32e Paging */
#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */
-static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
+static void walk_pde(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pde_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pde_addr, pte_start_addr, start_paddr;
@@ -108,12 +110,12 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
}
pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
- walk_pte(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* 32-bit Paging */
-static void walk_pde2(MemoryMappingList *list,
+static void walk_pde2(MemoryMappingList *list, AddressSpace *as,
hwaddr pde_start_addr, int32_t a20_mask,
bool pse)
{
@@ -124,7 +126,7 @@ static void walk_pde2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pde_addr = (pde_start_addr + i * 4) & a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -150,12 +152,12 @@ static void walk_pde2(MemoryMappingList *list,
}
pte_start_addr = (pde & ~0xfff) & a20_mask;
- walk_pte2(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* PAE Paging */
-static void walk_pdpe2(MemoryMappingList *list,
+static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask)
{
hwaddr pdpe_addr, pde_start_addr;
@@ -173,13 +175,13 @@ static void walk_pdpe2(MemoryMappingList *list,
line_addr = (((unsigned int)i & 0x3) << 30);
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
#ifdef TARGET_X86_64
/* IA-32e Paging */
-static void walk_pdpe(MemoryMappingList *list,
+static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -211,12 +213,12 @@ static void walk_pdpe(MemoryMappingList *list,
}
pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
/* IA-32e Paging */
-static void walk_pml4e(MemoryMappingList *list,
+static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
hwaddr pml4e_start_addr, int32_t a20_mask)
{
hwaddr pml4e_addr, pdpe_start_addr;
@@ -234,7 +236,7 @@ static void walk_pml4e(MemoryMappingList *list,
line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
- walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
+ walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
}
}
#endif
@@ -256,14 +258,14 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
hwaddr pml4e_addr;
pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
- walk_pml4e(list, pml4e_addr, env->a20_mask);
+ walk_pml4e(list, env->as, pml4e_addr, env->a20_mask);
} else
#endif
{
hwaddr pdpe_addr;
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
- walk_pdpe2(list, pdpe_addr, env->a20_mask);
+ walk_pdpe2(list, env->as, pdpe_addr, env->a20_mask);
}
} else {
hwaddr pde_addr;
@@ -271,7 +273,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
pse = !!(env->cr[4] & CR4_PSE_MASK);
- walk_pde2(list, pde_addr, env->a20_mask, pse);
+ walk_pde2(list, env->as, pde_addr, env->a20_mask, pse);
}
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 7c196ff..c802d34 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -728,7 +728,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -786,7 +786,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(env->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -957,7 +957,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK))
return -1;
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -966,7 +966,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
} else {
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(env->as, pte_addr);
if (!(pte & PG_PRESENT_MASK))
return -1;
page_size = 4096;
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index e789102..0c7216f 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1131,7 +1131,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
static void handle_even_inj(CPUX86State *env, int intno, int is_int,
int error_code, int is_hw, int rm)
{
- uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ uint32_t event_inj = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (!(event_inj & SVM_EVTINJ_VALID)) {
@@ -1225,7 +1225,7 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & HF_SVMI_MASK) {
- uint32_t event_inj = ldl_phys(env->vm_vmcb +
+ uint32_t event_inj = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj));
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 6cb4551..4c2edc2 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -194,25 +194,25 @@ void helper_rsm(CPUX86State *env)
cpu_x86_load_seg_cache(env, i,
lduw_phys(sm_state + offset),
ldq_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
+ ldl_phys(env->as, sm_state + offset + 4),
(lduw_phys(sm_state + offset + 2) &
0xf0ff) << 8);
}
env->gdt.base = ldq_phys(sm_state + 0x7e68);
- env->gdt.limit = ldl_phys(sm_state + 0x7e64);
+ env->gdt.limit = ldl_phys(env->as, sm_state + 0x7e64);
env->ldt.selector = lduw_phys(sm_state + 0x7e70);
env->ldt.base = ldq_phys(sm_state + 0x7e78);
- env->ldt.limit = ldl_phys(sm_state + 0x7e74);
+ env->ldt.limit = ldl_phys(env->as, sm_state + 0x7e74);
env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
env->idt.base = ldq_phys(sm_state + 0x7e88);
- env->idt.limit = ldl_phys(sm_state + 0x7e84);
+ env->idt.limit = ldl_phys(env->as, sm_state + 0x7e84);
env->tr.selector = lduw_phys(sm_state + 0x7e90);
env->tr.base = ldq_phys(sm_state + 0x7e98);
- env->tr.limit = ldl_phys(sm_state + 0x7e94);
+ env->tr.limit = ldl_phys(env->as, sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
@@ -227,51 +227,51 @@ void helper_rsm(CPUX86State *env)
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
}
env->eip = ldq_phys(sm_state + 0x7f78);
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
+ cpu_load_eflags(env, ldl_phys(env->as, sm_state + 0x7f70),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->dr[6] = ldl_phys(sm_state + 0x7f68);
- env->dr[7] = ldl_phys(sm_state + 0x7f60);
+ env->dr[6] = ldl_phys(env->as, sm_state + 0x7f68);
+ env->dr[7] = ldl_phys(env->as, sm_state + 0x7f60);
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
+ cpu_x86_update_cr4(env, ldl_phys(env->as, sm_state + 0x7f48));
+ cpu_x86_update_cr3(env, ldl_phys(env->as, sm_state + 0x7f50));
+ cpu_x86_update_cr0(env, ldl_phys(env->as, sm_state + 0x7f58));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(env->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
+ env->smbase = ldl_phys(env->as, sm_state + 0x7f00) & ~0x7fff;
}
#else
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
+ cpu_x86_update_cr0(env, ldl_phys(env->as, sm_state + 0x7ffc));
+ cpu_x86_update_cr3(env, ldl_phys(env->as, sm_state + 0x7ff8));
+ cpu_load_eflags(env, ldl_phys(env->as, sm_state + 0x7ff4),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->eip = ldl_phys(sm_state + 0x7ff0);
- env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec);
- env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
- env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
- env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
- env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
- env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
- env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
- env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
- env->dr[6] = ldl_phys(sm_state + 0x7fcc);
- env->dr[7] = ldl_phys(sm_state + 0x7fc8);
-
- env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
- env->tr.base = ldl_phys(sm_state + 0x7f64);
- env->tr.limit = ldl_phys(sm_state + 0x7f60);
- env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
-
- env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
- env->ldt.base = ldl_phys(sm_state + 0x7f80);
- env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
- env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
-
- env->gdt.base = ldl_phys(sm_state + 0x7f74);
- env->gdt.limit = ldl_phys(sm_state + 0x7f70);
-
- env->idt.base = ldl_phys(sm_state + 0x7f58);
- env->idt.limit = ldl_phys(sm_state + 0x7f54);
+ env->eip = ldl_phys(env->as, sm_state + 0x7ff0);
+ env->regs[R_EDI] = ldl_phys(env->as, sm_state + 0x7fec);
+ env->regs[R_ESI] = ldl_phys(env->as, sm_state + 0x7fe8);
+ env->regs[R_EBP] = ldl_phys(env->as, sm_state + 0x7fe4);
+ env->regs[R_ESP] = ldl_phys(env->as, sm_state + 0x7fe0);
+ env->regs[R_EBX] = ldl_phys(env->as, sm_state + 0x7fdc);
+ env->regs[R_EDX] = ldl_phys(env->as, sm_state + 0x7fd8);
+ env->regs[R_ECX] = ldl_phys(env->as, sm_state + 0x7fd4);
+ env->regs[R_EAX] = ldl_phys(env->as, sm_state + 0x7fd0);
+ env->dr[6] = ldl_phys(env->as, sm_state + 0x7fcc);
+ env->dr[7] = ldl_phys(env->as, sm_state + 0x7fc8);
+
+ env->tr.selector = ldl_phys(env->as, sm_state + 0x7fc4) & 0xffff;
+ env->tr.base = ldl_phys(env->as, sm_state + 0x7f64);
+ env->tr.limit = ldl_phys(env->as, sm_state + 0x7f60);
+ env->tr.flags = (ldl_phys(env->as, sm_state + 0x7f5c) & 0xf0ff) << 8;
+
+ env->ldt.selector = ldl_phys(env->as, sm_state + 0x7fc0) & 0xffff;
+ env->ldt.base = ldl_phys(env->as, sm_state + 0x7f80);
+ env->ldt.limit = ldl_phys(env->as, sm_state + 0x7f7c);
+ env->ldt.flags = (ldl_phys(env->as, sm_state + 0x7f78) & 0xf0ff) << 8;
+
+ env->gdt.base = ldl_phys(env->as, sm_state + 0x7f74);
+ env->gdt.limit = ldl_phys(env->as, sm_state + 0x7f70);
+
+ env->idt.base = ldl_phys(env->as, sm_state + 0x7f58);
+ env->idt.limit = ldl_phys(env->as, sm_state + 0x7f54);
for (i = 0; i < 6; i++) {
if (i < 3) {
@@ -280,16 +280,18 @@ void helper_rsm(CPUX86State *env)
offset = 0x7f2c + (i - 3) * 12;
}
cpu_x86_load_seg_cache(env, i,
- ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
- ldl_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
- (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
+ ldl_phys(env->as,
+ sm_state + 0x7fa8 + i * 4) & 0xffff,
+ ldl_phys(env->as, sm_state + offset + 8),
+ ldl_phys(env->as, sm_state + offset + 4),
+ (ldl_phys(env->as,
+ sm_state + offset) & 0xf0ff) << 8);
}
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
+ cpu_x86_update_cr4(env, ldl_phys(env->as, sm_state + 0x7f14));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(env->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
+ env->smbase = ldl_phys(env->as, sm_state + 0x7ef8) & ~0x7fff;
}
#endif
CC_OP = CC_OP_EFLAGS;
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4a7de42..2700232 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -105,7 +105,7 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
- sc->limit = ldl_phys(addr + offsetof(struct vmcb_seg, limit));
+ sc->limit = ldl_phys(env->as, addr + offsetof(struct vmcb_seg, limit));
flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
@@ -190,7 +190,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->intercept_dr_write = lduw_phys(env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_write));
- env->intercept_exceptions = ldl_phys(env->vm_vmcb +
+ env->intercept_exceptions = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_exceptions
));
@@ -203,12 +203,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.limit));
/* clear exit_info_2 so we behave like the real hardware */
@@ -221,7 +221,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.cr3)));
env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
if (int_ctl & V_INTR_MASKING_MASK) {
env->v_tpr = int_ctl & V_TPR_MASK;
@@ -277,12 +278,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
}
/* maybe we need to inject an event */
- event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ event_inj = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (event_inj & SVM_EVTINJ_VALID) {
uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK;
uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR;
- uint32_t event_inj_err = ldl_phys(env->vm_vmcb +
+ uint32_t event_inj_err = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj_err));
@@ -594,7 +595,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK);
int_ctl |= env->v_tpr & V_TPR_MASK;
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
@@ -623,12 +625,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.limit));
cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
@@ -674,10 +676,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
exit_info_1);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index c959460..bb1e206 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -185,7 +185,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
if (env->mpic_proxy) {
/* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(env->mpic_iack);
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(env->as, env->mpic_iack);
}
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b..d102bff 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -69,14 +69,14 @@ static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
hwaddr pte_offset)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset);
+ return ldl_phys(env->as, env->htab_base + pte_offset);
}
static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
hwaddr pte_offset)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+ return ldl_phys(env->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
}
static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 3c89f8a..b2d6716 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -70,7 +70,7 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
static void s390_cpu_load_normal(CPUState *s)
{
S390CPU *cpu = S390_CPU(s);
- cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR;
+ cpu->env.psw.addr = ldl_phys(cpu->env.as, 4) & PSW_MASK_ESA_ADDR;
cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
s390_add_running_cpu(cpu);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2936b58..d5400e2 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -615,7 +615,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(env->as, addr);
break;
case 8:
ret = ldq_phys(addr);
@@ -634,7 +634,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys((hwaddr)addr
+ ret = ldl_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
@@ -1438,7 +1438,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = lduw_phys(addr);
break;
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(env->as, addr);
break;
default:
case 8:
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ef12a0a..8c5986e 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -108,7 +108,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
/* Ctx pde */
switch (pde & PTE_ENTRYTYPE_MASK) {
@@ -120,7 +120,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return 4 << 2;
case 1: /* L0 PDE */
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -130,7 +130,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (1 << 8) | (4 << 2);
case 1: /* L1 PDE */
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -140,7 +140,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (2 << 8) | (4 << 2);
case 1: /* L2 PDE */
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -250,7 +250,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
/* Context base + context number */
pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -263,7 +263,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -277,7 +277,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -291,7 +291,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -317,7 +317,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 1e13a85..9045fcf 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -130,7 +130,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
/* Lookup l1 descriptor. */
table = env->cp0.c2_base & 0xfffff000;
table |= (address >> 20) & 0xffc;
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
code = 0;
switch (PAGETABLE_TYPE(desc)) {
case 3:
@@ -152,7 +152,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
goto do_fault;
}
table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
/* 4k page. */
if (is_user) {
DPRINTF("PTE address %x, desc %x\n", table, desc);
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index a0f9993..6977726 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -564,7 +564,7 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
vaddr, ret ? ~0 : paddr);
if (ret == 0) {
- *pte = ldl_phys(paddr);
+ *pte = ldl_phys(env->as, paddr);
}
return ret;
}
--
1.7.10.4
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