Re: [Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

[Sebastian Huber <sebastian.huber@embedded-brains.de>]

On 2014-02-13 13:01, Fabien Chouteau wrote:
> On 02/13/2014 10:52 AM, Sebastian Huber wrote:
>> The LEON3 processor has support for the CASA instruction which is
>> normally only available for SPARC V9 processors.  Binutils 2.24
>> and GCC 4.9 will support this instruction for LEON3.  GCC uses it to
>> generate C11 atomic operations.
>>
>> The CAS synthetic instruction uses an ASI of 0x80.  If TARGET_SPARC64 is
>> not defined use a supervisor data load/store for an ASI of 0x80 in
>> helper_ld_asi()/helper_st_asi().
>>
>
> Hello Sebastian,
>
> If I understand correctly, the difference with V1 is that ASI 0x80. Why
> did you chose Supervisor data access against User data access?

User data access would work also.  I don't have a preference here.

> (I cannot
> find documentation about 0x80 ASI)

GCC will generate CAS instructions, e.g.

	.file	"ticket.c"
	.section	".text"
	.align 4
	.global acquire
	.type	acquire, #function
	.proc	020
acquire:
	ld	[%o0], %g1
	mov	%g1, %g2
.LL7:
	add	%g1, 1, %g1
	cas	[%o0], %g2, %g1
	cmp	%g1, %g2
	bne,a	.LL7
	 mov	%g1, %g2
	add	%o0, 4, %o0
.LL4:
	ld	[%o0], %g1
	cmp	%g1, %g2
	bne	.LL4
	 nop
	jmp	%o7+8
	 nop
	.size	acquire, .-acquire
	.align 4
	.global release
	.type	release, #function
	.proc	020
release:
	ld	[%o0+4], %g1
	add	%g1, 1, %g1
	st	%g1, [%o0+4]
	jmp	%o7+8
	 nop
	.size	release, .-release
	.ident	"GCC: (GNU) 4.9.0 20130917 (experimental)"

In the GNU Binutils you find:

opcodes/sparc-opc.c:{ "cas",    F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, 
~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P,rs2,rd */

This is where the 0x80 comes from.

-- 
Sebastian Huber, embedded brains GmbH

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