From: Paolo Bonzini <pbonzini@redhat.com>
To: Tiejun Chen <tiejun.chen@intel.com>,
daniel.vetter@ffwll.ch, jani.nikula@linux.intel.com,
airlied@linux.ie
Cc: intel-gfx@lists.freedesktop.org, xen-devel@lists.xensource.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
qemu-devel@nongnu.org
Subject: Re: [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Fri, 20 Jun 2014 14:48:42 +0200 [thread overview]
Message-ID: <53A42DAA.80406@redhat.com> (raw)
In-Reply-To: <1403171631-3452-1-git-send-email-tiejun.chen@intel.com>
Il 19/06/2014 11:53, Tiejun Chen ha scritto:
> so this mean that isa bridge is still represented with Dev31:Func0
> like the native OS. Furthermore, currently we're pushing VGA
> passthrough support into qemu upstream, and with some discussion,
> we wouldn't set the bridge class type and just expose this devfn.
Even this is not really optimal. It just happens to work just because
QEMU's machine is currently a PCI machine with the ISA bridge on 00:01.0.
As soon as you'll try doing integrated graphics passthrough on a PCIe
machine type (such as QEMU's "-M q35") things will break down just as badly.
Paolo
WARNING: multiple messages have this Message-ID (diff)
From: Paolo Bonzini <pbonzini@redhat.com>
To: Tiejun Chen <tiejun.chen@intel.com>,
daniel.vetter@ffwll.ch, jani.nikula@linux.intel.com,
airlied@linux.ie
Cc: intel-gfx@lists.freedesktop.org, xen-devel@lists.xensource.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Fri, 20 Jun 2014 14:48:42 +0200 [thread overview]
Message-ID: <53A42DAA.80406@redhat.com> (raw)
In-Reply-To: <1403171631-3452-1-git-send-email-tiejun.chen@intel.com>
Il 19/06/2014 11:53, Tiejun Chen ha scritto:
> so this mean that isa bridge is still represented with Dev31:Func0
> like the native OS. Furthermore, currently we're pushing VGA
> passthrough support into qemu upstream, and with some discussion,
> we wouldn't set the bridge class type and just expose this devfn.
Even this is not really optimal. It just happens to work just because
QEMU's machine is currently a PCI machine with the ISA bridge on 00:01.0.
As soon as you'll try doing integrated graphics passthrough on a PCIe
machine type (such as QEMU's "-M q35") things will break down just as badly.
Paolo
next prev parent reply other threads:[~2014-06-20 12:48 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 9:53 [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type Tiejun Chen
2014-06-19 9:53 ` [Qemu-devel] " Tiejun Chen
2014-06-19 9:53 ` Tiejun Chen
2014-06-20 9:40 ` Chen, Tiejun
2014-06-20 9:40 ` [Qemu-devel] " Chen, Tiejun
2014-06-20 9:40 ` Chen, Tiejun
2014-06-20 12:32 ` Daniel Vetter
2014-06-20 12:32 ` [Qemu-devel] " Daniel Vetter
2014-06-20 12:32 ` Daniel Vetter
2014-06-22 8:00 ` Chen, Tiejun
2014-06-22 8:00 ` [Qemu-devel] " Chen, Tiejun
2014-06-22 8:00 ` Chen, Tiejun
2014-06-20 12:48 ` Paolo Bonzini [this message]
2014-06-20 12:48 ` [Qemu-devel] " Paolo Bonzini
2014-06-22 8:25 ` Chen, Tiejun
2014-06-22 8:25 ` [Qemu-devel] " Chen, Tiejun
2014-06-25 6:48 ` Paolo Bonzini
2014-06-25 6:48 ` [Qemu-devel] " Paolo Bonzini
2014-06-25 7:34 ` Chen, Tiejun
2014-06-25 7:34 ` [Qemu-devel] " Chen, Tiejun
2014-06-25 7:55 ` Paolo Bonzini
2014-06-25 7:55 ` [Qemu-devel] " Paolo Bonzini
2014-06-30 3:13 ` Chen, Tiejun
2014-06-30 3:13 ` [Qemu-devel] " Chen, Tiejun
2014-06-30 10:56 ` Paolo Bonzini
2014-06-30 10:56 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 14:49 ` Daniel Vetter
2014-07-07 14:49 ` [Qemu-devel] " Daniel Vetter
2014-07-07 14:49 ` Daniel Vetter
2014-07-07 14:57 ` Paolo Bonzini
2014-07-07 14:57 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 17:54 ` [Intel-gfx] " Daniel Vetter
2014-07-07 17:54 ` [Qemu-devel] " Daniel Vetter
2014-07-07 17:54 ` Daniel Vetter
2014-07-07 17:58 ` Paolo Bonzini
2014-07-07 17:58 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 18:40 ` Daniel Vetter
2014-07-07 18:40 ` [Qemu-devel] [Intel-gfx] " Daniel Vetter
2014-07-07 18:40 ` Daniel Vetter
2014-07-10 21:08 ` Tian, Kevin
2014-07-10 21:08 ` [Qemu-devel] [Intel-gfx] " Tian, Kevin
2014-07-10 21:08 ` Tian, Kevin
2014-07-11 6:29 ` Daniel Vetter
2014-07-11 6:29 ` [Qemu-devel] " Daniel Vetter
2014-07-11 6:29 ` Daniel Vetter
2014-07-11 19:42 ` [Xen-devel] " Konrad Rzeszutek Wilk
2014-07-11 19:42 ` [Qemu-devel] [Xen-devel] [Intel-gfx] " Konrad Rzeszutek Wilk
2014-07-11 19:42 ` Konrad Rzeszutek Wilk
2014-07-11 20:30 ` [Xen-devel] " Tian, Kevin
2014-07-11 20:30 ` [Qemu-devel] [Xen-devel] [Intel-gfx] " Tian, Kevin
2014-07-11 20:30 ` Tian, Kevin
2014-07-12 10:13 ` [Xen-devel] " Daniel Vetter
2014-07-12 10:13 ` [Qemu-devel] [Intel-gfx] " Daniel Vetter
2014-07-12 10:13 ` Daniel Vetter
2014-06-24 2:59 ` Zhenyu Wang
2014-06-24 2:59 ` [Qemu-devel] [Intel-gfx] " Zhenyu Wang
2014-06-24 2:59 ` Zhenyu Wang
2014-06-25 2:28 ` Chen, Tiejun
2014-06-25 2:28 ` [Qemu-devel] [Intel-gfx] " Chen, Tiejun
2014-06-25 2:28 ` Chen, Tiejun
2014-07-07 14:51 ` Daniel Vetter
2014-07-07 14:51 ` [Qemu-devel] " Daniel Vetter
2014-07-07 14:51 ` Daniel Vetter
2014-06-30 11:18 ` Michael S. Tsirkin
2014-06-30 11:18 ` [Qemu-devel] " Michael S. Tsirkin
2014-06-30 11:18 ` Michael S. Tsirkin
2014-07-01 1:52 ` Chen, Tiejun
2014-07-01 1:52 ` [Qemu-devel] " Chen, Tiejun
2014-07-01 1:52 ` Chen, Tiejun
2014-07-02 6:21 ` Michael S. Tsirkin
2014-07-02 6:21 ` [Qemu-devel] " Michael S. Tsirkin
2014-07-02 6:21 ` Michael S. Tsirkin
2014-07-02 8:27 ` Chen, Tiejun
2014-07-02 8:27 ` [Qemu-devel] " Chen, Tiejun
2014-07-02 8:27 ` Chen, Tiejun
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