From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: xen-devel@lists.xensource.com, Dave Airlie <airlied@linux.ie>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
qemu-devel@nongnu.org
Subject: Re: [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Sun, 22 Jun 2014 16:00:31 +0800 [thread overview]
Message-ID: <53A68D1F.5050101@intel.com> (raw)
In-Reply-To: <CAKMK7uGr=Mn13eRO-AZBM7aEBrNEp7Zn+5mQyEbuoq9XeqT-pQ@mail.gmail.com>
On 2014/6/20 20:32, Daniel Vetter wrote:
> Well I have no clue about forwarding the intel gpu to virtualized
> hosts and also no idea who could review this really. There's been a
> bit a discussion around the iommu mapping forwarding and similar
No, this doesn't affect IOMMU mapping.
> topics though. So I really wonder how well our driver works in this
> use case ...
In native case the truth is intel_detect_pch() needs to probe the
00:15.0 to determine what type current pch is, then the i915 driver can
be initialized correctly. Actually the 00:15.0 is just a ISA bridge.
In virtualized case we thought this ISA bridge mayn't be represented
with 00:15.0 originally by qemu-xen-traditional. So instead of checking
devfn, the i915 driver check the class type to get this ISA bridge.
But with my investigation,qemu-xen-traditional always set 00:15.0
explicitly to represent this ISA bridge. And especially, we wouldn't
provide that ISA bridge with an explicit class type in qemu-upstream, so
we need to the i915 driver to probe pch by checking devfn.
This should work both on the native case and the virtualized case.
Thanks
Tiejun
> -Daniel
>
> On Fri, Jun 20, 2014 at 11:40 AM, Chen, Tiejun <tiejun.chen@intel.com> wrote:
>> Just ping, any comments?
>>
>> Thanks
>> Tiejun
>>
>>
>> On 2014/6/19 17:53, Tiejun Chen wrote:
>>>
>>> Originally the reason to probe ISA bridge instead of Dev31:Fun0
>>> is to make graphics device passthrough work easy for VMM, that
>>> only need to expose ISA bridge to let driver know the real
>>> hardware underneath. This is a requirement from virtualization
>>> team. Especially in that virtualized environments, XEN, there
>>> is irrelevant ISA bridge in the system with that legacy qemu
>>> version specific to xen, qemu-xen-traditional. So to work
>>> reliably, we should scan through all the ISA bridge devices
>>> and check for the first match, instead of only checking the
>>> first one.
>>>
>>> But actually, qemu-xen-traditional, is always enumerated with
>>> Dev31:Fun0, 00:1f.0 as follows:
>>>
>>> hw/pt-graphics.c:
>>>
>>> intel_pch_init()
>>> |
>>> + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), ...);
>>>
>>> so this mean that isa bridge is still represented with Dev31:Func0
>>> like the native OS. Furthermore, currently we're pushing VGA
>>> passthrough support into qemu upstream, and with some discussion,
>>> we wouldn't set the bridge class type and just expose this devfn.
>>>
>>> So we just go back to check devfn to make life normal.
>>>
>>> Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.c | 19 +++----------------
>>> 1 file changed, 3 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index 651e65e..cb2526e 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -417,18 +417,8 @@ void intel_detect_pch(struct drm_device *dev)
>>> return;
>>> }
>>>
>>> - /*
>>> - * The reason to probe ISA bridge instead of Dev31:Fun0 is to
>>> - * make graphics device passthrough work easy for VMM, that only
>>> - * need to expose ISA bridge to let driver know the real hardware
>>> - * underneath. This is a requirement from virtualization team.
>>> - *
>>> - * In some virtualized environments (e.g. XEN), there is
>>> irrelevant
>>> - * ISA bridge in the system. To work reliably, we should scan
>>> trhough
>>> - * all the ISA bridge devices and check for the first match,
>>> instead
>>> - * of only checking the first one.
>>> - */
>>> - while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
>>> + pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
>>> + if (pch) {
>>> if (pch->vendor == PCI_VENDOR_ID_INTEL) {
>>> unsigned short id = pch->device &
>>> INTEL_PCH_DEVICE_ID_MASK;
>>> dev_priv->pch_id = id;
>>> @@ -462,10 +452,7 @@ void intel_detect_pch(struct drm_device *dev)
>>> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>>> WARN_ON(!IS_HASWELL(dev));
>>> WARN_ON(!IS_ULT(dev));
>>> - } else
>>> - continue;
>>> -
>>> - break;
>>> + }
>>> }
>>> }
>>> if (!pch)
>>>
>>
>
>
>
WARNING: multiple messages have this Message-ID (diff)
From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: "Nikula, Jani" <jani.nikula@linux.intel.com>,
Dave Airlie <airlied@linux.ie>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
xen-devel@lists.xensource.com, qemu-devel@nongnu.org
Subject: Re: [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Sun, 22 Jun 2014 16:00:31 +0800 [thread overview]
Message-ID: <53A68D1F.5050101@intel.com> (raw)
In-Reply-To: <CAKMK7uGr=Mn13eRO-AZBM7aEBrNEp7Zn+5mQyEbuoq9XeqT-pQ@mail.gmail.com>
On 2014/6/20 20:32, Daniel Vetter wrote:
> Well I have no clue about forwarding the intel gpu to virtualized
> hosts and also no idea who could review this really. There's been a
> bit a discussion around the iommu mapping forwarding and similar
No, this doesn't affect IOMMU mapping.
> topics though. So I really wonder how well our driver works in this
> use case ...
In native case the truth is intel_detect_pch() needs to probe the
00:15.0 to determine what type current pch is, then the i915 driver can
be initialized correctly. Actually the 00:15.0 is just a ISA bridge.
In virtualized case we thought this ISA bridge mayn't be represented
with 00:15.0 originally by qemu-xen-traditional. So instead of checking
devfn, the i915 driver check the class type to get this ISA bridge.
But with my investigation,qemu-xen-traditional always set 00:15.0
explicitly to represent this ISA bridge. And especially, we wouldn't
provide that ISA bridge with an explicit class type in qemu-upstream, so
we need to the i915 driver to probe pch by checking devfn.
This should work both on the native case and the virtualized case.
Thanks
Tiejun
> -Daniel
>
> On Fri, Jun 20, 2014 at 11:40 AM, Chen, Tiejun <tiejun.chen@intel.com> wrote:
>> Just ping, any comments?
>>
>> Thanks
>> Tiejun
>>
>>
>> On 2014/6/19 17:53, Tiejun Chen wrote:
>>>
>>> Originally the reason to probe ISA bridge instead of Dev31:Fun0
>>> is to make graphics device passthrough work easy for VMM, that
>>> only need to expose ISA bridge to let driver know the real
>>> hardware underneath. This is a requirement from virtualization
>>> team. Especially in that virtualized environments, XEN, there
>>> is irrelevant ISA bridge in the system with that legacy qemu
>>> version specific to xen, qemu-xen-traditional. So to work
>>> reliably, we should scan through all the ISA bridge devices
>>> and check for the first match, instead of only checking the
>>> first one.
>>>
>>> But actually, qemu-xen-traditional, is always enumerated with
>>> Dev31:Fun0, 00:1f.0 as follows:
>>>
>>> hw/pt-graphics.c:
>>>
>>> intel_pch_init()
>>> |
>>> + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), ...);
>>>
>>> so this mean that isa bridge is still represented with Dev31:Func0
>>> like the native OS. Furthermore, currently we're pushing VGA
>>> passthrough support into qemu upstream, and with some discussion,
>>> we wouldn't set the bridge class type and just expose this devfn.
>>>
>>> So we just go back to check devfn to make life normal.
>>>
>>> Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.c | 19 +++----------------
>>> 1 file changed, 3 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index 651e65e..cb2526e 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -417,18 +417,8 @@ void intel_detect_pch(struct drm_device *dev)
>>> return;
>>> }
>>>
>>> - /*
>>> - * The reason to probe ISA bridge instead of Dev31:Fun0 is to
>>> - * make graphics device passthrough work easy for VMM, that only
>>> - * need to expose ISA bridge to let driver know the real hardware
>>> - * underneath. This is a requirement from virtualization team.
>>> - *
>>> - * In some virtualized environments (e.g. XEN), there is
>>> irrelevant
>>> - * ISA bridge in the system. To work reliably, we should scan
>>> trhough
>>> - * all the ISA bridge devices and check for the first match,
>>> instead
>>> - * of only checking the first one.
>>> - */
>>> - while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
>>> + pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
>>> + if (pch) {
>>> if (pch->vendor == PCI_VENDOR_ID_INTEL) {
>>> unsigned short id = pch->device &
>>> INTEL_PCH_DEVICE_ID_MASK;
>>> dev_priv->pch_id = id;
>>> @@ -462,10 +452,7 @@ void intel_detect_pch(struct drm_device *dev)
>>> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>>> WARN_ON(!IS_HASWELL(dev));
>>> WARN_ON(!IS_ULT(dev));
>>> - } else
>>> - continue;
>>> -
>>> - break;
>>> + }
>>> }
>>> }
>>> if (!pch)
>>>
>>
>
>
>
WARNING: multiple messages have this Message-ID (diff)
From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: xen-devel@lists.xensource.com, Dave Airlie <airlied@linux.ie>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
qemu-devel@nongnu.org, "Nikula,
Jani" <jani.nikula@linux.intel.com>
Subject: Re: [Qemu-devel] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Sun, 22 Jun 2014 16:00:31 +0800 [thread overview]
Message-ID: <53A68D1F.5050101@intel.com> (raw)
In-Reply-To: <CAKMK7uGr=Mn13eRO-AZBM7aEBrNEp7Zn+5mQyEbuoq9XeqT-pQ@mail.gmail.com>
On 2014/6/20 20:32, Daniel Vetter wrote:
> Well I have no clue about forwarding the intel gpu to virtualized
> hosts and also no idea who could review this really. There's been a
> bit a discussion around the iommu mapping forwarding and similar
No, this doesn't affect IOMMU mapping.
> topics though. So I really wonder how well our driver works in this
> use case ...
In native case the truth is intel_detect_pch() needs to probe the
00:15.0 to determine what type current pch is, then the i915 driver can
be initialized correctly. Actually the 00:15.0 is just a ISA bridge.
In virtualized case we thought this ISA bridge mayn't be represented
with 00:15.0 originally by qemu-xen-traditional. So instead of checking
devfn, the i915 driver check the class type to get this ISA bridge.
But with my investigation,qemu-xen-traditional always set 00:15.0
explicitly to represent this ISA bridge. And especially, we wouldn't
provide that ISA bridge with an explicit class type in qemu-upstream, so
we need to the i915 driver to probe pch by checking devfn.
This should work both on the native case and the virtualized case.
Thanks
Tiejun
> -Daniel
>
> On Fri, Jun 20, 2014 at 11:40 AM, Chen, Tiejun <tiejun.chen@intel.com> wrote:
>> Just ping, any comments?
>>
>> Thanks
>> Tiejun
>>
>>
>> On 2014/6/19 17:53, Tiejun Chen wrote:
>>>
>>> Originally the reason to probe ISA bridge instead of Dev31:Fun0
>>> is to make graphics device passthrough work easy for VMM, that
>>> only need to expose ISA bridge to let driver know the real
>>> hardware underneath. This is a requirement from virtualization
>>> team. Especially in that virtualized environments, XEN, there
>>> is irrelevant ISA bridge in the system with that legacy qemu
>>> version specific to xen, qemu-xen-traditional. So to work
>>> reliably, we should scan through all the ISA bridge devices
>>> and check for the first match, instead of only checking the
>>> first one.
>>>
>>> But actually, qemu-xen-traditional, is always enumerated with
>>> Dev31:Fun0, 00:1f.0 as follows:
>>>
>>> hw/pt-graphics.c:
>>>
>>> intel_pch_init()
>>> |
>>> + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), ...);
>>>
>>> so this mean that isa bridge is still represented with Dev31:Func0
>>> like the native OS. Furthermore, currently we're pushing VGA
>>> passthrough support into qemu upstream, and with some discussion,
>>> we wouldn't set the bridge class type and just expose this devfn.
>>>
>>> So we just go back to check devfn to make life normal.
>>>
>>> Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.c | 19 +++----------------
>>> 1 file changed, 3 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index 651e65e..cb2526e 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -417,18 +417,8 @@ void intel_detect_pch(struct drm_device *dev)
>>> return;
>>> }
>>>
>>> - /*
>>> - * The reason to probe ISA bridge instead of Dev31:Fun0 is to
>>> - * make graphics device passthrough work easy for VMM, that only
>>> - * need to expose ISA bridge to let driver know the real hardware
>>> - * underneath. This is a requirement from virtualization team.
>>> - *
>>> - * In some virtualized environments (e.g. XEN), there is
>>> irrelevant
>>> - * ISA bridge in the system. To work reliably, we should scan
>>> trhough
>>> - * all the ISA bridge devices and check for the first match,
>>> instead
>>> - * of only checking the first one.
>>> - */
>>> - while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
>>> + pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
>>> + if (pch) {
>>> if (pch->vendor == PCI_VENDOR_ID_INTEL) {
>>> unsigned short id = pch->device &
>>> INTEL_PCH_DEVICE_ID_MASK;
>>> dev_priv->pch_id = id;
>>> @@ -462,10 +452,7 @@ void intel_detect_pch(struct drm_device *dev)
>>> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>>> WARN_ON(!IS_HASWELL(dev));
>>> WARN_ON(!IS_ULT(dev));
>>> - } else
>>> - continue;
>>> -
>>> - break;
>>> + }
>>> }
>>> }
>>> if (!pch)
>>>
>>
>
>
>
next prev parent reply other threads:[~2014-06-22 8:00 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 9:53 [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type Tiejun Chen
2014-06-19 9:53 ` [Qemu-devel] " Tiejun Chen
2014-06-19 9:53 ` Tiejun Chen
2014-06-20 9:40 ` Chen, Tiejun
2014-06-20 9:40 ` [Qemu-devel] " Chen, Tiejun
2014-06-20 9:40 ` Chen, Tiejun
2014-06-20 12:32 ` Daniel Vetter
2014-06-20 12:32 ` [Qemu-devel] " Daniel Vetter
2014-06-20 12:32 ` Daniel Vetter
2014-06-22 8:00 ` Chen, Tiejun [this message]
2014-06-22 8:00 ` [Qemu-devel] " Chen, Tiejun
2014-06-22 8:00 ` Chen, Tiejun
2014-06-20 12:48 ` Paolo Bonzini
2014-06-20 12:48 ` [Qemu-devel] " Paolo Bonzini
2014-06-22 8:25 ` Chen, Tiejun
2014-06-22 8:25 ` [Qemu-devel] " Chen, Tiejun
2014-06-25 6:48 ` Paolo Bonzini
2014-06-25 6:48 ` [Qemu-devel] " Paolo Bonzini
2014-06-25 7:34 ` Chen, Tiejun
2014-06-25 7:34 ` [Qemu-devel] " Chen, Tiejun
2014-06-25 7:55 ` Paolo Bonzini
2014-06-25 7:55 ` [Qemu-devel] " Paolo Bonzini
2014-06-30 3:13 ` Chen, Tiejun
2014-06-30 3:13 ` [Qemu-devel] " Chen, Tiejun
2014-06-30 10:56 ` Paolo Bonzini
2014-06-30 10:56 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 14:49 ` Daniel Vetter
2014-07-07 14:49 ` [Qemu-devel] " Daniel Vetter
2014-07-07 14:49 ` Daniel Vetter
2014-07-07 14:57 ` Paolo Bonzini
2014-07-07 14:57 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 17:54 ` [Intel-gfx] " Daniel Vetter
2014-07-07 17:54 ` [Qemu-devel] " Daniel Vetter
2014-07-07 17:54 ` Daniel Vetter
2014-07-07 17:58 ` Paolo Bonzini
2014-07-07 17:58 ` [Qemu-devel] " Paolo Bonzini
2014-07-07 18:40 ` Daniel Vetter
2014-07-07 18:40 ` [Qemu-devel] [Intel-gfx] " Daniel Vetter
2014-07-07 18:40 ` Daniel Vetter
2014-07-10 21:08 ` Tian, Kevin
2014-07-10 21:08 ` [Qemu-devel] [Intel-gfx] " Tian, Kevin
2014-07-10 21:08 ` Tian, Kevin
2014-07-11 6:29 ` Daniel Vetter
2014-07-11 6:29 ` [Qemu-devel] " Daniel Vetter
2014-07-11 6:29 ` Daniel Vetter
2014-07-11 19:42 ` [Xen-devel] " Konrad Rzeszutek Wilk
2014-07-11 19:42 ` [Qemu-devel] [Xen-devel] [Intel-gfx] " Konrad Rzeszutek Wilk
2014-07-11 19:42 ` Konrad Rzeszutek Wilk
2014-07-11 20:30 ` [Xen-devel] " Tian, Kevin
2014-07-11 20:30 ` [Qemu-devel] [Xen-devel] [Intel-gfx] " Tian, Kevin
2014-07-11 20:30 ` Tian, Kevin
2014-07-12 10:13 ` [Xen-devel] " Daniel Vetter
2014-07-12 10:13 ` [Qemu-devel] [Intel-gfx] " Daniel Vetter
2014-07-12 10:13 ` Daniel Vetter
2014-06-24 2:59 ` Zhenyu Wang
2014-06-24 2:59 ` [Qemu-devel] [Intel-gfx] " Zhenyu Wang
2014-06-24 2:59 ` Zhenyu Wang
2014-06-25 2:28 ` Chen, Tiejun
2014-06-25 2:28 ` [Qemu-devel] [Intel-gfx] " Chen, Tiejun
2014-06-25 2:28 ` Chen, Tiejun
2014-07-07 14:51 ` Daniel Vetter
2014-07-07 14:51 ` [Qemu-devel] " Daniel Vetter
2014-07-07 14:51 ` Daniel Vetter
2014-06-30 11:18 ` Michael S. Tsirkin
2014-06-30 11:18 ` [Qemu-devel] " Michael S. Tsirkin
2014-06-30 11:18 ` Michael S. Tsirkin
2014-07-01 1:52 ` Chen, Tiejun
2014-07-01 1:52 ` [Qemu-devel] " Chen, Tiejun
2014-07-01 1:52 ` Chen, Tiejun
2014-07-02 6:21 ` Michael S. Tsirkin
2014-07-02 6:21 ` [Qemu-devel] " Michael S. Tsirkin
2014-07-02 6:21 ` Michael S. Tsirkin
2014-07-02 8:27 ` Chen, Tiejun
2014-07-02 8:27 ` [Qemu-devel] " Chen, Tiejun
2014-07-02 8:27 ` Chen, Tiejun
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