From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding
Date: Mon, 30 Jun 2014 12:38:13 -0600 [thread overview]
Message-ID: <53B1AE95.3000602@wwwdotorg.org> (raw)
In-Reply-To: <20140630174334.GF28740@leverpostej>
On 06/30/2014 11:43 AM, Mark Rutland wrote:
> On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:
>> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
>> the AVP coprocessor and can also serve as a backup for the ARM Cortex
>> CPU's local interrupt controller (GIC).
>>
>> The LIC is subdivided into multiple identical units, each handling 32
>> possible interrupt sources.
>>
>> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> Changes in v2:
>> - new patch
>>
>> .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> new file mode 100644
>> index 000000000000..c695ec713740
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> @@ -0,0 +1,19 @@
>> +NVIDIA Tegra Legacy Interrupt Controller
>> +
>> +The legacy interrupt controller is divided into units that serve 32 interrupts
>> +each. Tegra20 implements four units, whereas Tegra30 and later implement five.
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra<chip>-ictlr"
>
> And valid <chip> values are?
Do you really want us to edit every single binding every time a new chip
comes out? Surely just relying NVIDIA's published chip names is fine?
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding
Date: Mon, 30 Jun 2014 12:38:13 -0600 [thread overview]
Message-ID: <53B1AE95.3000602@wwwdotorg.org> (raw)
In-Reply-To: <20140630174334.GF28740@leverpostej>
On 06/30/2014 11:43 AM, Mark Rutland wrote:
> On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
>> the AVP coprocessor and can also serve as a backup for the ARM Cortex
>> CPU's local interrupt controller (GIC).
>>
>> The LIC is subdivided into multiple identical units, each handling 32
>> possible interrupt sources.
>>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> Changes in v2:
>> - new patch
>>
>> .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> new file mode 100644
>> index 000000000000..c695ec713740
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> @@ -0,0 +1,19 @@
>> +NVIDIA Tegra Legacy Interrupt Controller
>> +
>> +The legacy interrupt controller is divided into units that serve 32 interrupts
>> +each. Tegra20 implements four units, whereas Tegra30 and later implement five.
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra<chip>-ictlr"
>
> And valid <chip> values are?
Do you really want us to edit every single binding every time a new chip
comes out? Surely just relying NVIDIA's published chip names is fine?
next prev parent reply other threads:[~2014-06-30 18:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-28 1:02 [PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding Thierry Reding
2014-06-28 1:02 ` Thierry Reding
[not found] ` <1403917351-13215-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-28 1:02 ` [PATCH v2 2/4] ARM: tegra: Add legacy interrupt controller nodes Thierry Reding
2014-06-28 1:02 ` Thierry Reding
2014-06-28 1:02 ` [PATCH v2 3/4] soc/tegra: Initialize interrupt controller from DT Thierry Reding
2014-06-28 1:02 ` Thierry Reding
[not found] ` <1403917351-13215-3-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-06-30 20:31 ` Stephen Warren
2014-06-30 20:31 ` Stephen Warren
2014-06-28 1:02 ` [PATCH v2 4/4] soc/tegra: Remove unused defines Thierry Reding
2014-06-28 1:02 ` Thierry Reding
2014-06-30 17:43 ` [PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding Mark Rutland
2014-06-30 17:43 ` Mark Rutland
2014-06-30 18:38 ` Stephen Warren [this message]
2014-06-30 18:38 ` Stephen Warren
[not found] ` <53B1AE95.3000602-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-07-01 13:10 ` Mark Rutland
2014-07-01 13:10 ` Mark Rutland
2014-06-30 20:32 ` Stephen Warren
2014-06-30 20:32 ` Stephen Warren
[not found] ` <53B1C948.6050603-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-25 17:35 ` Stephen Warren
2014-08-25 17:35 ` Stephen Warren
[not found] ` <53FB73EE.7000508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-26 6:17 ` Thierry Reding
2014-08-26 6:17 ` Thierry Reding
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