From: Markos Chandras <Markos.Chandras@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: <linux-mips@linux-mips.org>
Subject: Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores
Date: Wed, 16 Jul 2014 08:44:22 +0100 [thread overview]
Message-ID: <53C62D56.7090401@imgtec.com> (raw)
In-Reply-To: <53C5780B.1090602@gmail.com>
Hi David,
On 07/15/2014 07:50 PM, David Daney wrote:
> On 07/15/2014 06:09 AM, Markos Chandras wrote:
>> Hi,
>>
>> This patchset adds support for unique RI/XI exceptions. This feature has
>> been added in MIPSr5. Using this feature, we reduce the time it takes
>> to deal with a TLB exception caused by the RI/XI bits since the TLB load
>> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>>
>> This patch depends on the Hardware Page Table Walker (HTW) patchset
>> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html
>
> They are unrelated features, why the dependency?
Because of the conflicts in cpu.h and cpu-features.h. I am just trying
to make Ralf' life easier when he tries to determine the order to apply
this patches.
--
markos
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <Markos.Chandras@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores
Date: Wed, 16 Jul 2014 08:44:22 +0100 [thread overview]
Message-ID: <53C62D56.7090401@imgtec.com> (raw)
Message-ID: <20140716074422.raYQudN2GFu7XG-DVII0d9XCB3Zk5mzhPwgiJGnr_94@z> (raw)
In-Reply-To: <53C5780B.1090602@gmail.com>
Hi David,
On 07/15/2014 07:50 PM, David Daney wrote:
> On 07/15/2014 06:09 AM, Markos Chandras wrote:
>> Hi,
>>
>> This patchset adds support for unique RI/XI exceptions. This feature has
>> been added in MIPSr5. Using this feature, we reduce the time it takes
>> to deal with a TLB exception caused by the RI/XI bits since the TLB load
>> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>>
>> This patch depends on the Hardware Page Table Walker (HTW) patchset
>> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html
>
> They are unrelated features, why the dependency?
Because of the conflicts in cpu.h and cpu-features.h. I am just trying
to make Ralf' life easier when he tries to determine the order to apply
this patches.
--
markos
next prev parent reply other threads:[~2014-07-16 7:44 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-15 13:09 [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores Markos Chandras
2014-07-15 13:09 ` Markos Chandras
2014-07-15 13:09 ` [PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions Markos Chandras
2014-07-15 13:09 ` Markos Chandras
2014-07-15 16:09 ` Sergei Shtylyov
2014-07-16 7:45 ` Markos Chandras
2014-07-16 7:45 ` Markos Chandras
2014-07-15 13:09 ` [PATCH 2/3] MIPS: Use dedicated exception handler if CPU supports " Markos Chandras
2014-07-15 13:09 ` Markos Chandras
2014-07-15 13:09 ` [PATCH 3/3] MIPS: kernel: cpu-probe: Detect unique " Markos Chandras
2014-07-15 13:09 ` Markos Chandras
2014-07-15 18:50 ` [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores David Daney
2014-07-16 7:44 ` Markos Chandras [this message]
2014-07-16 7:44 ` Markos Chandras
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