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From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>,
	<tony.luck@intel.com>, <bp@alien8.de>,
	<jiang.liu@linux.intel.com>, <yinghai@kernel.org>,
	<x86@kernel.org>, <dvlasenk@redhat.com>, <JBeulich@suse.com>,
	<slaoub@gmail.com>, <luto@amacapital.net>,
	<dave.hansen@linux.intel.com>, <oleg@redhat.com>,
	<rostedt@goodmis.org>, <rusty@rustcorp.com.au>,
	<prarit@redhat.com>, <linux@rasmusvillemoes.dk>,
	<jroedel@suse.de>, <andriy.shevchenko@linux.intel.com>,
	<macro@linux-mips.org>, <wangnan0@huawei.com>,
	<linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>
Subject: Re: [PATCH 0/4] Enable deferred error interrupts
Date: Fri, 1 May 2015 09:50:44 -0500	[thread overview]
Message-ID: <554392C4.4060209@amd.com> (raw)
In-Reply-To: <20150501071830.GB19852@gmail.com>

On 5/1/2015 2:18 AM, Ingo Molnar wrote:
> * Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> wrote:
>
>> Newer AMD processors can generate deferred errors and can be configured
>> to generate APIC interrupts on such events.
> What's the wider context of this? What is it good for?
>
> I suspect it's MCE related, but only from the diffstat:

Deferred errors indicate error conditions that were not corrected, but 
require no action from S/W (or action is optional).
These errors provide info about a latent UC MCE that can occur when a 
poisoned data is consumed by the processor.

HTH,

I shall include the short description in the cover letter of V2.

Thanks,
-Aravind.


>>   arch/x86/kernel/cpu/mcheck/mce.c         |   1 +
>>   arch/x86/kernel/cpu/mcheck/mce_amd.c     | 105 ++++++++++++++++++++++++++++++-
> Please provide proper high level description for the changes.
>
>



      reply	other threads:[~2015-05-01 14:50 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-30 14:49 [PATCH 0/4] Enable deferred error interrupts Aravind Gopalakrishnan
2015-04-30 14:49 ` [PATCH 1/4] x86/mce: Define 'SUCCOR' cpuid bit Aravind Gopalakrishnan
2015-05-01 10:25   ` Borislav Petkov
2015-05-01 14:54     ` Aravind Gopalakrishnan
2015-05-03  9:01       ` Borislav Petkov
2015-05-01 15:09   ` Dave Hansen
2015-05-01 16:20     ` Borislav Petkov
2015-04-30 14:49 ` [PATCH 2/4] x86/mce/amd: Introduce deferred error interrupt handler Aravind Gopalakrishnan
2015-04-30 20:41   ` Andy Lutomirski
2015-05-01  4:16     ` Aravind Gopalakrishnan
2015-05-01  9:36       ` Borislav Petkov
2015-05-01 14:50         ` Aravind Gopalakrishnan
2015-05-03  9:22   ` Borislav Petkov
2015-05-04 15:29     ` Aravind Gopalakrishnan
2015-05-04 15:46       ` Borislav Petkov
2015-05-04 17:08         ` Aravind Gopalakrishnan
2015-05-04 18:46           ` Borislav Petkov
2015-05-04 19:06             ` Aravind Gopalakrishnan
2015-05-04 19:14               ` Borislav Petkov
2015-05-05 18:39             ` Aravind Gopalakrishnan
2015-05-05 20:28               ` Luck, Tony
2015-05-05 20:33                 ` Aravind Gopalakrishnan
2015-04-30 14:49 ` [PATCH 3/4] x86, irq: Cleanup ordering of vector numbers Aravind Gopalakrishnan
2015-04-30 14:49 ` [PATCH 4/4] x86/mce/amd: Rename setup_APIC_mce Aravind Gopalakrishnan
2015-05-01  7:18 ` [PATCH 0/4] Enable deferred error interrupts Ingo Molnar
2015-05-01 14:50   ` Aravind Gopalakrishnan [this message]

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