From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Heinrich Schuchardt" <xypron.glpk@gmx.de>
Cc: u-boot@lists.denx.de, "Simon Glass" <sjg@chromium.org>,
"Tom Rini" <trini@konsulko.com>,
"Ilias Apalodimas" <ilias.apalodimas@linaro.org>
Subject: Re: [PATCH 07/16] LoongArch: lib: General routines
Date: Tue, 18 Jun 2024 15:19:04 +0100 [thread overview]
Message-ID: <561150e8-e856-4993-8026-4872b1a8d55a@app.fastmail.com> (raw)
In-Reply-To: <bed8f4d9-957a-4e18-a9e2-8e52db4a60c8@gmx.de>
在2024年6月16日六月 下午5:00,Heinrich Schuchardt写道:
[...]
> The "LoongArch Reference Manual" is available at:
>
> https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cacop
>
> What irritates me in
> 2.1.7.1. Cache Coherency Maintenance of Instruction Cache
> is the word *can*:
>
> The Cache coherency maintenance between the instruction Cache and the
> data Cache within the processor core *can* be implemented as hardware
> maintenance.
>
> Maybe you have to consult the Chinese version.
>
> 处理器核内部指令 Cache 与数据 Cache 之间的缓存一致性维护可以实现为硬件维护
>
> The cache consistency maintenance between the instruction cache and data
> cache inside the processor core *can* be implemented as hardware
> maintenance.
Hi Heinrich,
Thanks for the investigation! Impressive effort on decrypting Chinese
semantics :-)
I had consulted Loongson folks, and they told me that all current hardware
implementation do have I/D cache coherency maintained by hardware, see
implementation[1] in kernel.
For dcache I'll implement it with cac_op.
Thanks
[1]: https://elixir.bootlin.com/linux/v6.9.5/source/arch/loongarch/mm/cache.c
>
> Best regards
>
> Heinrich
--
- Jiaxun
next prev parent reply other threads:[~2024-06-18 14:20 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-22 15:34 [PATCH 00/16] LoongArch initial support Jiaxun Yang
2024-05-22 15:34 ` [PATCH 01/16] lib: fdtdec: Handle multiple memory nodes Jiaxun Yang
2024-06-11 12:26 ` Heinrich Schuchardt
2024-06-11 13:47 ` Jiaxun Yang
2024-06-11 18:51 ` Simon Glass
2024-06-12 5:55 ` Heinrich Schuchardt
2024-05-22 15:34 ` [PATCH 02/16] linux/io.h: Use map_physmem to implement ioremap Jiaxun Yang
2024-05-22 15:34 ` [PATCH 03/16] image: Take entry point as an output of setup_booti Jiaxun Yang
2024-06-11 13:02 ` Heinrich Schuchardt
2024-06-11 13:29 ` Jiaxun Yang
2024-06-11 13:52 ` Tom Rini
2024-06-11 14:01 ` Jiaxun Yang
2024-06-11 14:09 ` Tom Rini
2024-05-22 15:34 ` [PATCH 04/16] elf.h Define LoongArch bits Jiaxun Yang
2024-06-16 10:34 ` Heinrich Schuchardt
2024-05-22 15:34 ` [PATCH 05/16] image: Define IH_ARCH_LOONGARCH Jiaxun Yang
2024-06-16 10:37 ` Heinrich Schuchardt
2024-05-22 15:34 ` [PATCH 06/16] LoongArch: skeleton and headers Jiaxun Yang
2024-05-23 15:15 ` Heinrich Schuchardt
2024-05-22 15:34 ` [PATCH 07/16] LoongArch: lib: General routines Jiaxun Yang
2024-06-16 11:01 ` Heinrich Schuchardt
2024-06-16 13:06 ` Jiaxun Yang
2024-06-16 16:00 ` Heinrich Schuchardt
2024-06-18 14:19 ` Jiaxun Yang [this message]
2024-05-22 15:34 ` [PATCH 08/16] LoongArch: CPU assembly routines Jiaxun Yang
2024-05-22 15:34 ` [PATCH 09/16] LoongArch: Exception handling Jiaxun Yang
2024-05-22 15:34 ` [PATCH 10/16] LoongArch: Boot Image bits Jiaxun Yang
2024-05-22 15:34 ` [PATCH 11/16] LoongArch: Generic CPU type Jiaxun Yang
2024-05-22 15:34 ` [PATCH 12/16] cpu: Add loongarch_cpu driver Jiaxun Yang
2024-05-22 15:34 ` [PATCH 13/16] timer: Add loongarch_timer driver Jiaxun Yang
2024-05-22 15:34 ` [PATCH 14/16] board: emulation: Add qemu-loongarch Jiaxun Yang
2024-05-22 15:34 ` [PATCH 15/16] efi: LoongArch: Define LoongArch bits everywhere Jiaxun Yang
2024-05-23 16:14 ` Heinrich Schuchardt
2024-05-23 16:25 ` Jiaxun Yang
2024-05-22 15:34 ` [PATCH 16/16] efi: LoongArch: Implement everything Jiaxun Yang
2024-05-23 16:26 ` Heinrich Schuchardt
2024-05-23 16:46 ` Jiaxun Yang
2024-05-23 15:25 ` [PATCH 00/16] LoongArch initial support Tom Rini
2024-05-23 15:38 ` Jiaxun Yang
2024-05-23 15:43 ` Tom Rini
2024-06-04 10:50 ` Jiaxun Yang
2024-06-04 17:09 ` Tom Rini
2024-05-23 15:47 ` Peter Robinson
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