[Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Chen Gang]

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>From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5i5j@gmail.com>
Date: Sun, 4 Oct 2015 17:34:17 +0800
Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

Or it will cause issue by the dest temporary registers.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
 target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
 1 file changed, 46 insertions(+), 39 deletions(-)

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index acb9ec4..2913902 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -496,7 +496,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
     const char *mnemonic;
     TCGMemOp memop;
     TileExcp ret = TILEGX_EXCP_NONE;
-    bool prefetch_nofault = false;
 
     /* Eliminate instructions with no output before doing anything else.  */
     switch (opext) {
@@ -597,6 +596,26 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         }
         qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
         return ret;
+
+    case OE_RR_X1(LD1U):
+        memop = MO_UB;
+        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
+        goto do_load_nofault;
+    case OE_RR_X1(LD2U):
+        memop = MO_TEUW;
+        mnemonic = "ld2u"; /* prefetch_l2 */
+        goto do_load_nofault;
+    case OE_RR_X1(LD4U):
+        memop = MO_TEUL;
+        mnemonic = "ld4u"; /* prefetch_l3 */
+    do_load_nofault:
+        if (dest != TILEGX_R_ZERO) {
+            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), load_gr(dc, srca),
+                               dc->mmuidx, memop);
+        }
+        qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+                      reg_names[dest], reg_names[srca]);
+        return ret;
     }
 
     tdest = dest_gr(dc, dest);
@@ -620,29 +639,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         memop = MO_SB;
         mnemonic = "ld1s"; /* prefetch_l1_fault */
         goto do_load;
-    case OE_RR_X1(LD1U):
-        memop = MO_UB;
-        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LD2S):
         memop = MO_TESW;
         mnemonic = "ld2s"; /* prefetch_l2_fault */
         goto do_load;
-    case OE_RR_X1(LD2U):
-        memop = MO_TEUW;
-        mnemonic = "ld2u"; /* prefetch_l2 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LD4S):
         memop = MO_TESL;
         mnemonic = "ld4s"; /* prefetch_l3_fault */
         goto do_load;
-    case OE_RR_X1(LD4U):
-        memop = MO_TEUL;
-        mnemonic = "ld4u"; /* prefetch_l3 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LDNT1S):
         memop = MO_SB;
         mnemonic = "ldnt1s";
@@ -675,9 +679,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         memop = MO_TEQ;
         mnemonic = "ld";
     do_load:
-        if (!prefetch_nofault) {
-            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
-        }
+        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
         break;
     case OE_RR_X1(LDNA):
         tcg_gen_andi_tl(tdest, tsrca, ~7);
@@ -1472,15 +1474,36 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
                                unsigned dest, unsigned srca, int imm)
 {
-    TCGv tdest = dest_gr(dc, dest);
+    TCGv tdest;
     TCGv tsrca = load_gr(dc, srca);
-    bool prefetch_nofault = false;
     const char *mnemonic;
     TCGMemOp memop;
     int i2, i3;
     TCGv t0;
 
     switch (opext) {
+    case OE_IM(LD1U_ADD, X1):
+        memop = MO_UB;
+        mnemonic = "ld1u_add"; /* prefetch_add_l1 */
+        goto do_load_add_nofault;
+    case OE_IM(LD2U_ADD, X1):
+        memop = MO_TEUW;
+        mnemonic = "ld2u_add"; /* prefetch_add_l2 */
+        goto do_load_add_nofault;
+    case OE_IM(LD4U_ADD, X1):
+        memop = MO_TEUL;
+        mnemonic = "ld4u_add"; /* prefetch_add_l3 */
+    do_load_add_nofault:
+        if (dest != TILEGX_R_ZERO) {
+            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), tsrca, dc->mmuidx, memop);
+        }
+        tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+        goto done2;
+    }
+
+    tdest = dest_gr(dc, dest);
+
+    switch (opext) {
     case OE(ADDI_OPCODE_Y0, 0, Y0):
     case OE(ADDI_OPCODE_Y1, 0, Y1):
     case OE_IM(ADDI, X0):
@@ -1526,29 +1549,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         memop = MO_SB;
         mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
         goto do_load_add;
-    case OE_IM(LD1U_ADD, X1):
-        memop = MO_UB;
-        mnemonic = "ld1u_add"; /* prefetch_add_l1 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LD2S_ADD, X1):
         memop = MO_TESW;
         mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
         goto do_load_add;
-    case OE_IM(LD2U_ADD, X1):
-        memop = MO_TEUW;
-        mnemonic = "ld2u_add"; /* prefetch_add_l2 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LD4S_ADD, X1):
         memop = MO_TESL;
         mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
         goto do_load_add;
-    case OE_IM(LD4U_ADD, X1):
-        memop = MO_TEUL;
-        mnemonic = "ld4u_add"; /* prefetch_add_l3 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LDNT1S_ADD, X1):
         memop = MO_SB;
         mnemonic = "ldnt1s_add";
@@ -1581,9 +1589,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         memop = MO_TEQ;
         mnemonic = "ld_add";
     do_load_add:
-        if (!prefetch_nofault) {
-            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
-        }
+        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
         tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
         break;
     case OE_IM(LDNA_ADD, X1):
@@ -1756,6 +1762,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         return TILEGX_EXCP_OPCODE_UNKNOWN;
     }
 
+done2:
     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
                   reg_names[dest], reg_names[srca], imm);
     return TILEGX_EXCP_NONE;
-- 
1.9.3

 		 	   		  

[-- Attachment #2: 0006-target-tilegx-Let-prefetch-nop-instructions-return-b.patch --]
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From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5i5j@gmail.com>
Date: Sun, 4 Oct 2015 17:34:17 +0800
Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

Or it will cause issue by the dest temporary registers.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
 target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
 1 file changed, 46 insertions(+), 39 deletions(-)

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index acb9ec4..2913902 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -496,7 +496,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
     const char *mnemonic;
     TCGMemOp memop;
     TileExcp ret = TILEGX_EXCP_NONE;
-    bool prefetch_nofault = false;
 
     /* Eliminate instructions with no output before doing anything else.  */
     switch (opext) {
@@ -597,6 +596,26 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         }
         qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
         return ret;
+
+    case OE_RR_X1(LD1U):
+        memop = MO_UB;
+        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
+        goto do_load_nofault;
+    case OE_RR_X1(LD2U):
+        memop = MO_TEUW;
+        mnemonic = "ld2u"; /* prefetch_l2 */
+        goto do_load_nofault;
+    case OE_RR_X1(LD4U):
+        memop = MO_TEUL;
+        mnemonic = "ld4u"; /* prefetch_l3 */
+    do_load_nofault:
+        if (dest != TILEGX_R_ZERO) {
+            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), load_gr(dc, srca),
+                               dc->mmuidx, memop);
+        }
+        qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+                      reg_names[dest], reg_names[srca]);
+        return ret;
     }
 
     tdest = dest_gr(dc, dest);
@@ -620,29 +639,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         memop = MO_SB;
         mnemonic = "ld1s"; /* prefetch_l1_fault */
         goto do_load;
-    case OE_RR_X1(LD1U):
-        memop = MO_UB;
-        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LD2S):
         memop = MO_TESW;
         mnemonic = "ld2s"; /* prefetch_l2_fault */
         goto do_load;
-    case OE_RR_X1(LD2U):
-        memop = MO_TEUW;
-        mnemonic = "ld2u"; /* prefetch_l2 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LD4S):
         memop = MO_TESL;
         mnemonic = "ld4s"; /* prefetch_l3_fault */
         goto do_load;
-    case OE_RR_X1(LD4U):
-        memop = MO_TEUL;
-        mnemonic = "ld4u"; /* prefetch_l3 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load;
     case OE_RR_X1(LDNT1S):
         memop = MO_SB;
         mnemonic = "ldnt1s";
@@ -675,9 +679,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         memop = MO_TEQ;
         mnemonic = "ld";
     do_load:
-        if (!prefetch_nofault) {
-            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
-        }
+        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
         break;
     case OE_RR_X1(LDNA):
         tcg_gen_andi_tl(tdest, tsrca, ~7);
@@ -1472,15 +1474,36 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
                                unsigned dest, unsigned srca, int imm)
 {
-    TCGv tdest = dest_gr(dc, dest);
+    TCGv tdest;
     TCGv tsrca = load_gr(dc, srca);
-    bool prefetch_nofault = false;
     const char *mnemonic;
     TCGMemOp memop;
     int i2, i3;
     TCGv t0;
 
     switch (opext) {
+    case OE_IM(LD1U_ADD, X1):
+        memop = MO_UB;
+        mnemonic = "ld1u_add"; /* prefetch_add_l1 */
+        goto do_load_add_nofault;
+    case OE_IM(LD2U_ADD, X1):
+        memop = MO_TEUW;
+        mnemonic = "ld2u_add"; /* prefetch_add_l2 */
+        goto do_load_add_nofault;
+    case OE_IM(LD4U_ADD, X1):
+        memop = MO_TEUL;
+        mnemonic = "ld4u_add"; /* prefetch_add_l3 */
+    do_load_add_nofault:
+        if (dest != TILEGX_R_ZERO) {
+            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), tsrca, dc->mmuidx, memop);
+        }
+        tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+        goto done2;
+    }
+
+    tdest = dest_gr(dc, dest);
+
+    switch (opext) {
     case OE(ADDI_OPCODE_Y0, 0, Y0):
     case OE(ADDI_OPCODE_Y1, 0, Y1):
     case OE_IM(ADDI, X0):
@@ -1526,29 +1549,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         memop = MO_SB;
         mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
         goto do_load_add;
-    case OE_IM(LD1U_ADD, X1):
-        memop = MO_UB;
-        mnemonic = "ld1u_add"; /* prefetch_add_l1 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LD2S_ADD, X1):
         memop = MO_TESW;
         mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
         goto do_load_add;
-    case OE_IM(LD2U_ADD, X1):
-        memop = MO_TEUW;
-        mnemonic = "ld2u_add"; /* prefetch_add_l2 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LD4S_ADD, X1):
         memop = MO_TESL;
         mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
         goto do_load_add;
-    case OE_IM(LD4U_ADD, X1):
-        memop = MO_TEUL;
-        mnemonic = "ld4u_add"; /* prefetch_add_l3 */
-        prefetch_nofault = (dest == TILEGX_R_ZERO);
-        goto do_load_add;
     case OE_IM(LDNT1S_ADD, X1):
         memop = MO_SB;
         mnemonic = "ldnt1s_add";
@@ -1581,9 +1589,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         memop = MO_TEQ;
         mnemonic = "ld_add";
     do_load_add:
-        if (!prefetch_nofault) {
-            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
-        }
+        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
         tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
         break;
     case OE_IM(LDNA_ADD, X1):
@@ -1756,6 +1762,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
         return TILEGX_EXCP_OPCODE_UNKNOWN;
     }
 
+done2:
     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
                   reg_names[dest], reg_names[srca], imm);
     return TILEGX_EXCP_NONE;
-- 
1.9.3

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Richard Henderson]

On 10/04/2015 10:15 PM, Chen Gang wrote:
>>From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
> From: Chen Gang<gang.chen.5i5j@gmail.com>
> Date: Sun, 4 Oct 2015 17:34:17 +0800
> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>
> Or it will cause issue by the dest temporary registers.
>
> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
> ---
>   target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>   1 file changed, 46 insertions(+), 39 deletions(-)

Isn't my patch 14/14 from the last patch set sufficient?


r~

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Chen Gang]

On 10/7/15 17:19, Richard Henderson wrote:
> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>> From: Chen Gang<gang.chen.5i5j@gmail.com>
>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>>
>> Or it will cause issue by the dest temporary registers.
>>
>> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
>> ---
>>   target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>>   1 file changed, 46 insertions(+), 39 deletions(-)
> 
> Isn't my patch 14/14 from the last patch set sufficient?
> 

It is related with your patch 14/14. If possible, for me, we can merge
them together.

Thanks.
-- 
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Chen Gang]

On 10/7/15 18:17, Chen Gang wrote:
> On 10/7/15 17:19, Richard Henderson wrote:
>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>>> From: Chen Gang<gang.chen.5i5j@gmail.com>
>>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>>>
>>> Or it will cause issue by the dest temporary registers.
>>>
>>> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
>>> ---
>>> target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>>> 1 file changed, 46 insertions(+), 39 deletions(-)
>>
>> Isn't my patch 14/14 from the last patch set sufficient?
>>

At present, all patches (include 14/14) are integrated into master tree,
so I guess, we have to integrate this patch into master tree next, it
fix the dest temporary registers' issue.

>
> It is related with your patch 14/14. If possible, for me, we can merge
> them together.
>

Thanks.
--
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed
 		 	   		  

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Richard Henderson]

On 10/09/2015 09:48 AM, Chen Gang wrote:
> On 10/7/15 18:17, Chen Gang wrote:
>> On 10/7/15 17:19, Richard Henderson wrote:
>>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>>>  From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>>>> From: Chen Gang<gang.chen.5i5j@gmail.com>
>>>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>>>>
>>>> Or it will cause issue by the dest temporary registers.
>>>>
>>>> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
>>>> ---
>>>> target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>>>> 1 file changed, 46 insertions(+), 39 deletions(-)
>>>
>>> Isn't my patch 14/14 from the last patch set sufficient?
>>>
>
> At present, all patches (include 14/14) are integrated into master tree,
> so I guess, we have to integrate this patch into master tree next, it
> fix the dest temporary registers' issue.

What issue?  The prefetch instructions "load" to the zero register,
which is never written back to the register file.


r~

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Chen Gang]

On 10/10/15 06:10, Richard Henderson wrote:
> On 10/09/2015 09:48 AM, Chen Gang wrote:
>> On 10/7/15 18:17, Chen Gang wrote:
>>> On 10/7/15 17:19, Richard Henderson wrote:
>>>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>>>>  From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>>>>> From: Chen Gang<gang.chen.5i5j@gmail.com>
>>>>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>>>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>>>>>
>>>>> Or it will cause issue by the dest temporary registers.
>>>>>
>>>>> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
>>>>> ---
>>>>> target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>>>>> 1 file changed, 46 insertions(+), 39 deletions(-)
>>>>
>>>> Isn't my patch 14/14 from the last patch set sufficient?
>>>>
>>
>> At present, all patches (include 14/14) are integrated into master tree,
>> so I guess, we have to integrate this patch into master tree next, it
>> fix the dest temporary registers' issue.
> 
> What issue?  The prefetch instructions "load" to the zero register,
> which is never written back to the register file.
> 

OK, really. But for me, the code is very easy to lead other members to
make mistakes.

Thanks.
-- 
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed

Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register

[Chen Gang]

Hello all:

It looks I have to spend quite a few free time resources on tilegx gcc
testsuite issues, next (may 2-3 months at least, I guess).

So for tilegx qemu, I guess, I need to start to implement the floating
point, at present. I shall try to finish within this month (although it
seems not quite easy to me).

By the way, excuse me, my English is not quite well, so:

 - I have to try to 'speak' as clearly as I can, so sometimes what I
   said may be not quite polite, please understand.

 - If any members find any issues/bugs which may be related with me,
   please say directly and clearly (or sometimes, I maybe misunderstand,
   then waste our time resources).


Thanks.

On 10/10/15 06:50, Chen Gang wrote:
> 
> On 10/10/15 06:10, Richard Henderson wrote:
>> On 10/09/2015 09:48 AM, Chen Gang wrote:
>>> On 10/7/15 18:17, Chen Gang wrote:
>>>> On 10/7/15 17:19, Richard Henderson wrote:
>>>>> On 10/04/2015 10:15 PM, Chen Gang wrote:
>>>>>>>  From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
>>>>>> From: Chen Gang<gang.chen.5i5j@gmail.com>
>>>>>> Date: Sun, 4 Oct 2015 17:34:17 +0800
>>>>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>>>>>>
>>>>>> Or it will cause issue by the dest temporary registers.
>>>>>>
>>>>>> Signed-off-by: Chen Gang<gang.chen.5i5j@gmail.com>
>>>>>> ---
>>>>>> target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------
>>>>>> 1 file changed, 46 insertions(+), 39 deletions(-)
>>>>>
>>>>> Isn't my patch 14/14 from the last patch set sufficient?
>>>>>
>>>
>>> At present, all patches (include 14/14) are integrated into master tree,
>>> so I guess, we have to integrate this patch into master tree next, it
>>> fix the dest temporary registers' issue.
>>
>> What issue?  The prefetch instructions "load" to the zero register,
>> which is never written back to the register file.
>>
> 
> OK, really. But for me, the code is very easy to lead other members to
> make mistakes.
> 
> Thanks.
> 

-- 
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed