[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02

[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02

[yankejian]

this patchset fixes the bug that eth can't initial successful on hip05-D02
because the dts files doesn't match the source code.

yankejian (3):
  dts: hisi: enables the ethX for D02 board
  dts: hisi: fixes no syscon error when init mdio
  arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts              | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi                 |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi             |  4 ++--
 4 files changed, 38 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02

[yankejian]

this patchset fixes the bug that eth can't initial successful on hip05-D02
because the dts files doesn't match the source code.

yankejian (3):
  dts: hisi: enables the ethX for D02 board
  dts: hisi: fixes no syscon error when init mdio
  arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts              | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi                 |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi             |  4 ++--
 4 files changed, 38 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02

[yankejian]

this patchset fixes the bug that eth can't initial successful on hip05-D02
because the dts files doesn't match the source code.

yankejian (3):
  dts: hisi: enables the ethX for D02 board
  dts: hisi: fixes no syscon error when init mdio
  arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts              | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi                 |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi             |  4 ++--
 4 files changed, 38 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[yankejian]

this patch enables the ethX for D02 board on hip05-d02.dts. otherwise it
cannot find hns ethX by ifconfig -a.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index ae34e25..6aa5cb2 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -34,3 +34,19 @@
 &uart0 {
 	status = "ok";
 };
+
+&eth2 {
+	status = "okay";
+};
+
+&eth3 {
+	status = "okay";
+};
+
+&eth6 {
+	status = "okay";
+};
+
+&eth7 {
+	status = "okay";
+};
-- 
1.9.1

[PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[yankejian]

this patch enables the ethX for D02 board on hip05-d02.dts. otherwise it
cannot find hns ethX by ifconfig -a.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index ae34e25..6aa5cb2 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -34,3 +34,19 @@
 &uart0 {
 	status = "ok";
 };
+
+&eth2 {
+	status = "okay";
+};
+
+&eth3 {
+	status = "okay";
+};
+
+&eth6 {
+	status = "okay";
+};
+
+&eth7 {
+	status = "okay";
+};
-- 
1.9.1

[PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[yankejian]

this patch enables the ethX for D02 board on hip05-d02.dts. otherwise it
cannot find hns ethX by ifconfig -a.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index ae34e25..6aa5cb2 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -34,3 +34,19 @@
 &uart0 {
 	status = "ok";
 };
+
+&eth2 {
+	status = "okay";
+};
+
+&eth3 {
+	status = "okay";
+};
+
+&eth6 {
+	status = "okay";
+};
+
+&eth7 {
+	status = "okay";
+};
-- 
1.9.1

[PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[yankejian]

this patch enables the ethX for D02 board on hip05-d02.dts. otherwise it
cannot find hns ethX by ifconfig -a.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index ae34e25..6aa5cb2 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -34,3 +34,19 @@
 &uart0 {
 	status = "ok";
 };
+
+&eth2 {
+	status = "okay";
+};
+
+&eth3 {
+	status = "okay";
+};
+
+&eth6 {
+	status = "okay";
+};
+
+&eth7 {
+	status = "okay";
+};
-- 
1.9.1

[PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[kbuild test robot]

Hi yankejian,

[auto build test ERROR on net-next/master]

url:    https://github.com/0day-ci/linux/commits/yankejian/dts-hisi-fixes-can-t-find-eth-for-hip05-D02/20151205-155412
config: arm64-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:38.1-6 Label or path eth2 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:42.1-6 Label or path eth3 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:46.1-6 Label or path eth6 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:50.1-6 Label or path eth7 not found
   FATAL ERROR: Syntax error parsing input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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Re: [PATCH RESEND net-next 1/3] dts: hisi: enables the ethX for D02 board

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1086 bytes --]

Hi yankejian,

[auto build test ERROR on net-next/master]

url:    https://github.com/0day-ci/linux/commits/yankejian/dts-hisi-fixes-can-t-find-eth-for-hip05-D02/20151205-155412
config: arm64-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:38.1-6 Label or path eth2 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:42.1-6 Label or path eth3 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:46.1-6 Label or path eth6 not found
>> Error: arch/arm64/boot/dts/hisilicon/hip05-d02.dts:50.1-6 Label or path eth7 not found
   FATAL ERROR: Syntax error parsing input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 46778 bytes --]

[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[yankejian]

when linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
 mdio_bus mdio at 803c0000: mdio sys ctl reg has not maped       "

the source code about the subctrl is dealled with syscon, but dts doesn't.
it cause such fault. so this patch adds the syscon info on dts files to
fixes it.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi     | 4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4ff16d0..daaca63 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -246,6 +246,10 @@
 			clock-frequency = <200000000>;
 		};
 
+		peri_c_subctrl: sub_ctrl_c at 80000000 {
+			compatible = "hisilicon,peri-c-subctrl", "syscon";
+			reg = < 0x0 0x80000000 0x0 0x10000>;
+		};
 		uart0: uart at 80300000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
index 606dd5a..4d4815e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
@@ -10,8 +10,8 @@ soc0: soc at 000000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "hisilicon,hns-mdio";
-		reg = <0x0 0x803c0000 0x0 0x10000
-		       0x0 0x80000000 0x0 0x10000>;
+		reg = <0x0 0x803c0000 0x0 0x10000>;
+		subctrl_vbase = <&peri_c_subctrl>;
 
 		soc0_phy0: ethernet-phy at 0 {
 			reg = <0x0>;
-- 
1.9.1

[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[yankejian]

when linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
 mdio_bus mdio@803c0000: mdio sys ctl reg has not maped       "

the source code about the subctrl is dealled with syscon, but dts doesn't.
it cause such fault. so this patch adds the syscon info on dts files to
fixes it.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi     | 4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4ff16d0..daaca63 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -246,6 +246,10 @@
 			clock-frequency = <200000000>;
 		};
 
+		peri_c_subctrl: sub_ctrl_c@80000000 {
+			compatible = "hisilicon,peri-c-subctrl", "syscon";
+			reg = < 0x0 0x80000000 0x0 0x10000>;
+		};
 		uart0: uart@80300000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
index 606dd5a..4d4815e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
@@ -10,8 +10,8 @@ soc0: soc@000000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "hisilicon,hns-mdio";
-		reg = <0x0 0x803c0000 0x0 0x10000
-		       0x0 0x80000000 0x0 0x10000>;
+		reg = <0x0 0x803c0000 0x0 0x10000>;
+		subctrl_vbase = <&peri_c_subctrl>;
 
 		soc0_phy0: ethernet-phy@0 {
 			reg = <0x0>;
-- 
1.9.1

[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[yankejian]

when linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
 mdio_bus mdio@803c0000: mdio sys ctl reg has not maped       "

the source code about the subctrl is dealled with syscon, but dts doesn't.
it cause such fault. so this patch adds the syscon info on dts files to
fixes it.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi     | 4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4ff16d0..daaca63 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -246,6 +246,10 @@
 			clock-frequency = <200000000>;
 		};
 
+		peri_c_subctrl: sub_ctrl_c@80000000 {
+			compatible = "hisilicon,peri-c-subctrl", "syscon";
+			reg = < 0x0 0x80000000 0x0 0x10000>;
+		};
 		uart0: uart@80300000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
index 606dd5a..4d4815e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
@@ -10,8 +10,8 @@ soc0: soc@000000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "hisilicon,hns-mdio";
-		reg = <0x0 0x803c0000 0x0 0x10000
-		       0x0 0x80000000 0x0 0x10000>;
+		reg = <0x0 0x803c0000 0x0 0x10000>;
+		subctrl_vbase = <&peri_c_subctrl>;
 
 		soc0_phy0: ethernet-phy@0 {
 			reg = <0x0>;
-- 
1.9.1

[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:57 yankejian wrote:
>                 #size-cells = <0>;
>                 compatible = "hisilicon,hns-mdio";
> -               reg = <0x0 0x803c0000 0x0 0x10000
> -                      0x0 0x80000000 0x0 0x10000>;
> +               reg = <0x0 0x803c0000 0x0 0x10000>;
> +               subctrl_vbase = <&peri_c_subctrl>;
>  
>                 soc0_phy0: ethernet-phy at 0 {
>                         reg = <0x0>;

I don't see the subctrl_vbase property documented in the binding. Please
modify the binding as well.

Also, please use the normal naming conventions using '-' instead of '_'
inside of property names.

	Arnd

Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:57 yankejian wrote:
>                 #size-cells = <0>;
>                 compatible = "hisilicon,hns-mdio";
> -               reg = <0x0 0x803c0000 0x0 0x10000
> -                      0x0 0x80000000 0x0 0x10000>;
> +               reg = <0x0 0x803c0000 0x0 0x10000>;
> +               subctrl_vbase = <&peri_c_subctrl>;
>  
>                 soc0_phy0: ethernet-phy@0 {
>                         reg = <0x0>;

I don't see the subctrl_vbase property documented in the binding. Please
modify the binding as well.

Also, please use the normal naming conventions using '-' instead of '_'
inside of property names.

	Arnd

Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:57 yankejian wrote:
>                 #size-cells = <0>;
>                 compatible = "hisilicon,hns-mdio";
> -               reg = <0x0 0x803c0000 0x0 0x10000
> -                      0x0 0x80000000 0x0 0x10000>;
> +               reg = <0x0 0x803c0000 0x0 0x10000>;
> +               subctrl_vbase = <&peri_c_subctrl>;
>  
>                 soc0_phy0: ethernet-phy@0 {
>                         reg = <0x0>;

I don't see the subctrl_vbase property documented in the binding. Please
modify the binding as well.

Also, please use the normal naming conventions using '-' instead of '_'
inside of property names.

	Arnd
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[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Yankejian (Hackim Yim)]

On 2015/12/6 6:15, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:57 yankejian wrote:
>>                 #size-cells = <0>;
>>                 compatible = "hisilicon,hns-mdio";
>> -               reg = <0x0 0x803c0000 0x0 0x10000
>> -                      0x0 0x80000000 0x0 0x10000>;
>> +               reg = <0x0 0x803c0000 0x0 0x10000>;
>> +               subctrl_vbase = <&peri_c_subctrl>;
>>  
>>                 soc0_phy0: ethernet-phy at 0 {
>>                         reg = <0x0>;
> I don't see the subctrl_vbase property documented in the binding. Please
> modify the binding as well.
>
> Also, please use the normal naming conventions using '-' instead of '_'
> inside of property names.
>
> 	Arnd
>
> .

Hi, Arnd
Thanks for your suggestions. i will fixes it later.

Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Yankejian (Hackim Yim)]

On 2015/12/6 6:15, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:57 yankejian wrote:
>>                 #size-cells = <0>;
>>                 compatible = "hisilicon,hns-mdio";
>> -               reg = <0x0 0x803c0000 0x0 0x10000
>> -                      0x0 0x80000000 0x0 0x10000>;
>> +               reg = <0x0 0x803c0000 0x0 0x10000>;
>> +               subctrl_vbase = <&peri_c_subctrl>;
>>  
>>                 soc0_phy0: ethernet-phy@0 {
>>                         reg = <0x0>;
> I don't see the subctrl_vbase property documented in the binding. Please
> modify the binding as well.
>
> Also, please use the normal naming conventions using '-' instead of '_'
> inside of property names.
>
> 	Arnd
>
> .

Hi, Arnd
Thanks for your suggestions. i will fixes it later.

Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Yankejian (Hackim Yim)]

On 2015/12/6 6:15, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:57 yankejian wrote:
>>                 #size-cells = <0>;
>>                 compatible = "hisilicon,hns-mdio";
>> -               reg = <0x0 0x803c0000 0x0 0x10000
>> -                      0x0 0x80000000 0x0 0x10000>;
>> +               reg = <0x0 0x803c0000 0x0 0x10000>;
>> +               subctrl_vbase = <&peri_c_subctrl>;
>>  
>>                 soc0_phy0: ethernet-phy@0 {
>>                         reg = <0x0>;
> I don't see the subctrl_vbase property documented in the binding. Please
> modify the binding as well.
>
> Also, please use the normal naming conventions using '-' instead of '_'
> inside of property names.
>
> 	Arnd
>
> .

Hi, Arnd
Thanks for your suggestions. i will fixes it later.

Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio

[Yankejian (Hackim Yim)]

On 2015/12/6 6:15, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:57 yankejian wrote:
>>                 #size-cells = <0>;
>>                 compatible = "hisilicon,hns-mdio";
>> -               reg = <0x0 0x803c0000 0x0 0x10000
>> -                      0x0 0x80000000 0x0 0x10000>;
>> +               reg = <0x0 0x803c0000 0x0 0x10000>;
>> +               subctrl_vbase = <&peri_c_subctrl>;
>>  
>>                 soc0_phy0: ethernet-phy@0 {
>>                         reg = <0x0>;
> I don't see the subctrl_vbase property documented in the binding. Please
> modify the binding as well.
>
> Also, please use the normal naming conventions using '-' instead of '_'
> inside of property names.
>
> 	Arnd
>
> .

Hi, Arnd
Thanks for your suggestions. i will fixes it later.

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller at 0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:58 yankejian wrote:
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> +       /* for HiP05 PCIe-SAS system */
> +       pcie_sas: system_controller at 0xb0000000 {
> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> +               reg = <0xb0000000 0x10000>;
> +       };
> 

The compatible string in the example does not match the required properties.

	Arnd

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:58 yankejian wrote:
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> +       /* for HiP05 PCIe-SAS system */
> +       pcie_sas: system_controller@0xb0000000 {
> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> +               reg = <0xb0000000 0x10000>;
> +       };
> 

The compatible string in the example does not match the required properties.

	Arnd

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Arnd Bergmann]

On Saturday 05 December 2015 15:56:58 yankejian wrote:
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> +       /* for HiP05 PCIe-SAS system */
> +       pcie_sas: system_controller@0xb0000000 {
> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> +               reg = <0xb0000000 0x10000>;
> +       };
> 

The compatible string in the example does not match the required properties.

	Arnd
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[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/6 6:13, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:58 yankejian wrote:
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +       /* for HiP05 PCIe-SAS system */
>> +       pcie_sas: system_controller at 0xb0000000 {
>> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> +               reg = <0xb0000000 0x10000>;
>> +       };
>>
> The compatible string in the example does not match the required properties.
>
> 	Arnd
>
> .
Hi, Arnd
Thanks for your suggestions. i will fixes it later.

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/6 6:13, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:58 yankejian wrote:
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +       /* for HiP05 PCIe-SAS system */
>> +       pcie_sas: system_controller@0xb0000000 {
>> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> +               reg = <0xb0000000 0x10000>;
>> +       };
>>
> The compatible string in the example does not match the required properties.
>
> 	Arnd
>
> .
Hi, Arnd
Thanks for your suggestions. i will fixes it later.

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/6 6:13, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:58 yankejian wrote:
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +       /* for HiP05 PCIe-SAS system */
>> +       pcie_sas: system_controller@0xb0000000 {
>> +               compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> +               reg = <0xb0000000 0x10000>;
>> +       };
>>
> The compatible string in the example does not match the required properties.
>
> 	Arnd
>
> .
Hi, Arnd
Thanks for your suggestions. i will fixes it later.

[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02

[yankejian]

this patchset fixes the bug that eth can't initial successful on hip05-D02
because the dts files doesn't match the source code.

yankejian (3):
  dts: hisi: enables the ethX for D02 board
  dts: hisi: fixes no syscon error when init mdio
  arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts              | 16 ++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi                 |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi             |  4 ++--
 4 files changed, 38 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller at 0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[yankejian]

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@huawei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@0xb0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Rob Herring]

On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
> This patch adds documentation for the devicetree bindings used by the
> DT files of Hisilicon Hip05-D02 development board.
> 
> Signed-off-by: yankejian <yankejian@huawei.com>
> ---
>  .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 6ac7c00..5318d78 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -187,6 +187,22 @@ Example:
>  		reg = <0xb0000000 0x10000>;
>  	};
>  
> +Hisilicon HiP05 PERISUB system controller
> +
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";

This should be more specific and have the SOC name in it.

> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> +	/* for HiP05 PCIe-SAS system */
> +	pcie_sas: system_controller at 0xb0000000 {
> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";

The example doesn't match.

> +		reg = <0xb0000000 0x10000>;
> +	};
>  -----------------------------------------------------------------------
>  Hisilicon CPU controller
>  
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Rob Herring]

On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
> This patch adds documentation for the devicetree bindings used by the
> DT files of Hisilicon Hip05-D02 development board.
> 
> Signed-off-by: yankejian <yankejian@huawei.com>
> ---
>  .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 6ac7c00..5318d78 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -187,6 +187,22 @@ Example:
>  		reg = <0xb0000000 0x10000>;
>  	};
>  
> +Hisilicon HiP05 PERISUB system controller
> +
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";

This should be more specific and have the SOC name in it.

> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> +	/* for HiP05 PCIe-SAS system */
> +	pcie_sas: system_controller@0xb0000000 {
> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";

The example doesn't match.

> +		reg = <0xb0000000 0x10000>;
> +	};
>  -----------------------------------------------------------------------
>  Hisilicon CPU controller
>  
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Bintian]

On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@huawei.com>
You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)

BR,

Bintian
>> ---
>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>>   		reg = <0xb0000000 0x10000>;
>>   	};
>>   
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
>
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +	/* for HiP05 PCIe-SAS system */
>> +	pcie_sas: system_controller at 0xb0000000 {
>> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.
>
>> +		reg = <0xb0000000 0x10000>;
>> +	};
>>   -----------------------------------------------------------------------
>>   Hisilicon CPU controller
>>   
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
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Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Bintian]

On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@huawei.com>
You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)

BR,

Bintian
>> ---
>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>>   		reg = <0xb0000000 0x10000>;
>>   	};
>>   
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
>
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +	/* for HiP05 PCIe-SAS system */
>> +	pcie_sas: system_controller@0xb0000000 {
>> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.
>
>> +		reg = <0xb0000000 0x10000>;
>> +	};
>>   -----------------------------------------------------------------------
>>   Hisilicon CPU controller
>>   
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
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>
> .
>

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Bintian]

On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@huawei.com>
You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)

BR,

Bintian
>> ---
>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>>   		reg = <0xb0000000 0x10000>;
>>   	};
>>   
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
>
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +	/* for HiP05 PCIe-SAS system */
>> +	pcie_sas: system_controller@0xb0000000 {
>> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.
>
>> +		reg = <0xb0000000 0x10000>;
>> +	};
>>   -----------------------------------------------------------------------
>>   Hisilicon CPU controller
>>   
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
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> the body of a message to majordomo@vger.kernel.org
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>
> .
>

[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/7 21:48, Bintian wrote:
> On 2015/12/7 21:16, Rob Herring wrote:
>> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>>> This patch adds documentation for the devicetree bindings used by the
>>> DT files of Hisilicon Hip05-D02 development board.
>>>
>>> Signed-off-by: yankejian <yankejian@huawei.com>
> You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)
>
> BR,
>
> Bintian

agree, thanks

BR,
Kejian Yan

>>> ---
>>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>>   1 file changed, 16 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> index 6ac7c00..5318d78 100644
>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> @@ -187,6 +187,22 @@ Example:
>>>           reg = <0xb0000000 0x10000>;
>>>       };
>>>   +Hisilicon HiP05 PERISUB system controller
>>> +
>>> +Required properties:
>>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> This should be more specific and have the SOC name in it.
>>
>>> +- reg : Register address and size
>>> +
>>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>>> +HiP05 Soc to implement some basic configurations. the peripheral
>>> + controllers include mdio, ddr, iic, uart, timer and so on.
>>> +
>>> +Example:
>>> +    /* for HiP05 PCIe-SAS system */
>>> +    pcie_sas: system_controller at 0xb0000000 {
>>> +        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> The example doesn't match.
>>
Thanks for this. I have changed this in PATCH V2 already floated.

BR
Kejian Yan
>>> +        reg = <0xb0000000 0x10000>;
>>> +    };
>>>   -----------------------------------------------------------------------
>>>   Hisilicon CPU controller
>>>   -- 
>>> 1.9.1
>>>
>>> -- 
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo at vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> -- 
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at  http://www.tux.org/lkml/
>>
>> .
>>
>
>
>
> .
>

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/7 21:48, Bintian wrote:
> On 2015/12/7 21:16, Rob Herring wrote:
>> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>>> This patch adds documentation for the devicetree bindings used by the
>>> DT files of Hisilicon Hip05-D02 development board.
>>>
>>> Signed-off-by: yankejian <yankejian@huawei.com>
> You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)
>
> BR,
>
> Bintian

agree, thanks

BR,
Kejian Yan

>>> ---
>>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>>   1 file changed, 16 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> index 6ac7c00..5318d78 100644
>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> @@ -187,6 +187,22 @@ Example:
>>>           reg = <0xb0000000 0x10000>;
>>>       };
>>>   +Hisilicon HiP05 PERISUB system controller
>>> +
>>> +Required properties:
>>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> This should be more specific and have the SOC name in it.
>>
>>> +- reg : Register address and size
>>> +
>>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>>> +HiP05 Soc to implement some basic configurations. the peripheral
>>> + controllers include mdio, ddr, iic, uart, timer and so on.
>>> +
>>> +Example:
>>> +    /* for HiP05 PCIe-SAS system */
>>> +    pcie_sas: system_controller@0xb0000000 {
>>> +        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> The example doesn't match.
>>
Thanks for this. I have changed this in PATCH V2 already floated.

BR
Kejian Yan
>>> +        reg = <0xb0000000 0x10000>;
>>> +    };
>>>   -----------------------------------------------------------------------
>>>   Hisilicon CPU controller
>>>   -- 
>>> 1.9.1
>>>
>>> -- 
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> -- 
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at  http://www.tux.org/lkml/
>>
>> .
>>
>
>
>
> .
>

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

On 2015/12/7 21:48, Bintian wrote:
> On 2015/12/7 21:16, Rob Herring wrote:
>> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>>> This patch adds documentation for the devicetree bindings used by the
>>> DT files of Hisilicon Hip05-D02 development board.
>>>
>>> Signed-off-by: yankejian <yankejian@huawei.com>
> You may need to configure as  "Kejian Yan <yankejian@huawei.com>"     :)
>
> BR,
>
> Bintian

agree, thanks

BR,
Kejian Yan

>>> ---
>>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>>   1 file changed, 16 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> index 6ac7c00..5318d78 100644
>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> @@ -187,6 +187,22 @@ Example:
>>>           reg = <0xb0000000 0x10000>;
>>>       };
>>>   +Hisilicon HiP05 PERISUB system controller
>>> +
>>> +Required properties:
>>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> This should be more specific and have the SOC name in it.
>>
>>> +- reg : Register address and size
>>> +
>>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>>> +HiP05 Soc to implement some basic configurations. the peripheral
>>> + controllers include mdio, ddr, iic, uart, timer and so on.
>>> +
>>> +Example:
>>> +    /* for HiP05 PCIe-SAS system */
>>> +    pcie_sas: system_controller@0xb0000000 {
>>> +        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> The example doesn't match.
>>
Thanks for this. I have changed this in PATCH V2 already floated.

BR
Kejian Yan
>>> +        reg = <0xb0000000 0x10000>;
>>> +    };
>>>   -----------------------------------------------------------------------
>>>   Hisilicon CPU controller
>>>   -- 
>>> 1.9.1
>>>
>>> -- 
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> -- 
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>> the body of a message to majordomo@vger.kernel.org
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>> Please read the FAQ at  http://www.tux.org/lkml/
>>
>> .
>>
>
>
>
> .
>

Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

[Yankejian (Hackim Yim)]

[-- Attachment #1: Type: text/plain, Size: 2286 bytes --]



On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@huawei.com>
>> ---
>>  .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>>  		reg = <0xb0000000 0x10000>;
>>  	};
>>  
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
Hi Rob,
the design is recommended to be used for hip05 and later SOCs, so we try to use hisilicon instead.
thanks for your suggestions.

Best Regards,
yankejian


>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +	/* for HiP05 PCIe-SAS system */
>> +	pcie_sas: system_controller@0xb0000000 {
>> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.

Thanks for this. I have changed this in PATCH V2 already floated.

Best Regards
yankejian

>> +		reg = <0xb0000000 0x10000>;
>> +	};
>>  -----------------------------------------------------------------------
>>  Hisilicon CPU controller
>>  
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
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> the body of a message to majordomo@vger.kernel.org
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