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From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
To: Andy Gross <agross@codeaurora.org>,
	Stanimir Varbanov <stanimir.varbanov@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	dmaengine@vger.kernel.org, Vinod Koul <vinod.koul@intel.com>,
	Rob Herring <robh+dt@kernel.org>, Rob Herring <robh@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Pawel Moll <pawel.moll@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Archit Taneja <architt@codeaurora.org>
Subject: Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size
Date: Thu, 10 Dec 2015 15:18:33 +0200	[thread overview]
Message-ID: <56697BA9.5050805@linaro.org> (raw)
In-Reply-To: <20151202172255.GA9599@Agamemnon.attlocal.net>

On 12/02/2015 07:22 PM, Andy Gross wrote:
> On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote:
>> On 12/01/2015 07:23 PM, Andy Gross wrote:
>>> On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote:
>>>> The pipe fifo size register must instruct the bam hw
>>>> how many hw descriptors can be pushed to fifo. Currently
>>>> we isntruct the hw with 32KBytes but wrap the tail in
>>>> bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
>>>> leads to stalled transactions when the tail wraps.
>>>>
>>>> Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
>>>> register i.e. 32K - 8.
>>>>
>>>> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
>>>> ---
>>>>  drivers/dma/qcom_bam_dma.c |    2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
>>>> index 0f06f3b7a72b..6d290de9ab2b 100644
>>>> --- a/drivers/dma/qcom_bam_dma.c
>>>> +++ b/drivers/dma/qcom_bam_dma.c
>>>> @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
>>>>  	 */
>>>>  	writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
>>>>  			bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
>>>> -	writel_relaxed(BAM_DESC_FIFO_SIZE,
>>>> +	writel_relaxed(BAM_MAX_DATA_SIZE,
>>>>  			bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
>>>
>>> This is just using the #define.  That is ok, but if you use this instead of the
>>> BAM_P_FIFO_SIZES then you need to fix your comment.  Or actually use the
>>> register value.... otherwise looks fine.
>>
>> I did not follow your comment, but the intension of the patch is to set
>> the proper FIFO size in BAM_P_FIFO_SIZES register, i.e. 32K - 8.
> 
> Sorry, I mixed up the usage and was thinking there was something you read out
> that told you the size.  That's not how it works, unfortunately.  The
> MAX_DATA_SIZE is fine, but the name is a little misleading.  Perhaps just
> BAM_FIFO_SIZE?

OK I can rename BAM_MAX_DATA_SIZE to BAM_FIFO_SIZE, and use it when
setting BAM_P_FIFO_SIZES register. Is that fine to you?


-- 
regards,
Stan

WARNING: multiple messages have this Message-ID (diff)
From: stanimir.varbanov@linaro.org (Stanimir Varbanov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size
Date: Thu, 10 Dec 2015 15:18:33 +0200	[thread overview]
Message-ID: <56697BA9.5050805@linaro.org> (raw)
In-Reply-To: <20151202172255.GA9599@Agamemnon.attlocal.net>

On 12/02/2015 07:22 PM, Andy Gross wrote:
> On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote:
>> On 12/01/2015 07:23 PM, Andy Gross wrote:
>>> On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote:
>>>> The pipe fifo size register must instruct the bam hw
>>>> how many hw descriptors can be pushed to fifo. Currently
>>>> we isntruct the hw with 32KBytes but wrap the tail in
>>>> bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
>>>> leads to stalled transactions when the tail wraps.
>>>>
>>>> Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
>>>> register i.e. 32K - 8.
>>>>
>>>> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
>>>> ---
>>>>  drivers/dma/qcom_bam_dma.c |    2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
>>>> index 0f06f3b7a72b..6d290de9ab2b 100644
>>>> --- a/drivers/dma/qcom_bam_dma.c
>>>> +++ b/drivers/dma/qcom_bam_dma.c
>>>> @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
>>>>  	 */
>>>>  	writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
>>>>  			bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
>>>> -	writel_relaxed(BAM_DESC_FIFO_SIZE,
>>>> +	writel_relaxed(BAM_MAX_DATA_SIZE,
>>>>  			bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
>>>
>>> This is just using the #define.  That is ok, but if you use this instead of the
>>> BAM_P_FIFO_SIZES then you need to fix your comment.  Or actually use the
>>> register value.... otherwise looks fine.
>>
>> I did not follow your comment, but the intension of the patch is to set
>> the proper FIFO size in BAM_P_FIFO_SIZES register, i.e. 32K - 8.
> 
> Sorry, I mixed up the usage and was thinking there was something you read out
> that told you the size.  That's not how it works, unfortunately.  The
> MAX_DATA_SIZE is fine, but the name is a little misleading.  Perhaps just
> BAM_FIFO_SIZE?

OK I can rename BAM_MAX_DATA_SIZE to BAM_FIFO_SIZE, and use it when
setting BAM_P_FIFO_SIZES register. Is that fine to you?


-- 
regards,
Stan

  reply	other threads:[~2015-12-10 13:18 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-01  9:14 [PATCH 0/4] bam dma fixes and one dt extension Stanimir Varbanov
2015-12-01  9:14 ` Stanimir Varbanov
2015-12-01  9:14 ` [PATCH 1/4] dmaengine: qcom_bam_dma: fix dma free memory on remove Stanimir Varbanov
2015-12-01  9:14   ` Stanimir Varbanov
2015-12-01  9:14 ` [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised Stanimir Varbanov
2015-12-01  9:14   ` Stanimir Varbanov
2015-12-01 10:29   ` Arnd Bergmann
2015-12-01 10:29     ` Arnd Bergmann
2015-12-02 12:56     ` Stanimir Varbanov
2015-12-02 12:56       ` Stanimir Varbanov
2015-12-02 13:05       ` Arnd Bergmann
2015-12-02 13:05         ` Arnd Bergmann
2015-12-02 16:47         ` Stanimir Varbanov
2015-12-02 16:47           ` Stanimir Varbanov
2015-12-01 17:28   ` Andy Gross
2015-12-01 17:28     ` Andy Gross
     [not found] ` <1448961299-15161-1-git-send-email-stanimir.varbanov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-12-01  9:14   ` [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size Stanimir Varbanov
2015-12-01  9:14     ` Stanimir Varbanov
2015-12-01  9:14     ` Stanimir Varbanov
2015-12-01 10:28     ` Arnd Bergmann
2015-12-01 10:28       ` Arnd Bergmann
2015-12-01 17:25       ` Andy Gross
2015-12-01 17:25         ` Andy Gross
2015-12-01 20:22         ` Arnd Bergmann
2015-12-01 20:22           ` Arnd Bergmann
2015-12-01 17:23     ` Andy Gross
2015-12-01 17:23       ` Andy Gross
2015-12-02 16:44       ` Stanimir Varbanov
2015-12-02 16:44         ` Stanimir Varbanov
2015-12-02 17:22         ` Andy Gross
2015-12-02 17:22           ` Andy Gross
2015-12-10 13:18           ` Stanimir Varbanov [this message]
2015-12-10 13:18             ` Stanimir Varbanov
     [not found]             ` <56697BA9.5050805-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-01-29  4:38               ` Andy Gross
2016-01-29  4:38                 ` Andy Gross
2016-01-29  4:38                 ` Andy Gross
2016-04-05 21:33   ` [PATCH 0/4] bam dma fixes and one dt extension Andy Gross
2016-04-05 21:33     ` Andy Gross
2016-04-05 21:33     ` Andy Gross
2016-04-05 23:06     ` Stanimir Varbanov
2016-04-05 23:06       ` Stanimir Varbanov
2015-12-01  9:14 ` [PATCH 4/4] dmaengine: qcom_bam_dma: add controlled remotely dt property Stanimir Varbanov
2015-12-01  9:14   ` Stanimir Varbanov
2015-12-01 17:30   ` Andy Gross
2015-12-01 17:30     ` Andy Gross

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