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From: Dirk Behme <dirk.behme@de.bosch.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
	Simon Horman <horms@verge.net.au>,
	Magnus Damm <magnus.damm@gmail.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	<linux-renesas-soc@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node
Date: Tue, 16 Feb 2016 08:33:41 +0100	[thread overview]
Message-ID: <56C2D0D5.7090705@de.bosch.com> (raw)
In-Reply-To: <CAMuHMdX=Kgb-i+QpP=yNO2e6nw7sXuCutXPoK0U9NwK-OyANFA@mail.gmail.com>

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller@1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk


WARNING: multiple messages have this Message-ID (diff)
From: dirk.behme@de.bosch.com (Dirk Behme)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node
Date: Tue, 16 Feb 2016 08:33:41 +0100	[thread overview]
Message-ID: <56C2D0D5.7090705@de.bosch.com> (raw)
In-Reply-To: <CAMuHMdX=Kgb-i+QpP=yNO2e6nw7sXuCutXPoK0U9NwK-OyANFA@mail.gmail.com>

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller at 1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk

WARNING: multiple messages have this Message-ID (diff)
From: Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org>
To: Geert Uytterhoeven <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: Geert Uytterhoeven
	<geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>,
	Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>,
	Magnus Damm <magnus.damm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node
Date: Tue, 16 Feb 2016 08:33:41 +0100	[thread overview]
Message-ID: <56C2D0D5.7090705@de.bosch.com> (raw)
In-Reply-To: <CAMuHMdX=Kgb-i+QpP=yNO2e6nw7sXuCutXPoK0U9NwK-OyANFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller@1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk

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  reply	other threads:[~2016-02-16  7:33 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-15 20:38 [PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes Geert Uytterhoeven
2016-02-15 20:38 ` Geert Uytterhoeven
2016-02-15 20:38 ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 1/7] ARM: dts: r8a73a4: Add " Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 2/7] ARM: dts: r8a7790: " Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 3/7] ARM: dts: r8a7791: Add L2 cache-controller node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 4/7] ARM: dts: r8a7793: " Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 5/7] ARM: dts: r8a7794: " Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-16  6:40   ` Dirk Behme
2016-02-16  6:40     ` Dirk Behme
2016-02-16  6:40     ` Dirk Behme
2016-02-16  9:43     ` Sudeep Holla
2016-02-16  9:43       ` Sudeep Holla
2016-02-16  9:55       ` Dirk Behme
2016-02-16  9:55         ` Dirk Behme
2016-02-16  9:55         ` Dirk Behme
2016-02-15 20:38 ` [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-16  6:44   ` Dirk Behme
2016-02-16  6:44     ` Dirk Behme
2016-02-16  6:44     ` Dirk Behme
2016-02-16  7:12     ` Geert Uytterhoeven
2016-02-16  7:12       ` Geert Uytterhoeven
2016-02-16  7:33       ` Dirk Behme [this message]
2016-02-16  7:33         ` Dirk Behme
2016-02-16  7:33         ` Dirk Behme
2016-02-16  9:46       ` Sudeep Holla
2016-02-16  9:46         ` Sudeep Holla
2016-02-16  9:46         ` Sudeep Holla
2016-02-17  5:53 ` [PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes Simon Horman
2016-02-17  5:53   ` Simon Horman

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