Re: [Qemu-arm] [PATCH v5 4/9] target-mips: Amend processor definitions in relation to FCR31

[Leon Alrae <leon.alrae@imgtec.com>]

On 18/04/16 17:03, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> 
> Amend definitions of some Mips processors related to FCR31
> (float status control register). Most significantly, FCR31 of
> processors mips32r6-generic, mips64r6-generic, and P5600 will
> be set so that its FCR31_ABS2008 and FCR31_NAN2008 bits are set
> to 1.

Not long before this series was posted I applied a change which sets
these bits for these processors (even though there's no actual support):
https://lists.nongnu.org/archive/html/qemu-devel/2016-02/msg05593.html

By looking at the description I'm guessing this part was subtracted
after you rebased the series. Now this patch does nothing apart from
setting fcr31 to 0 which actually isn't necessary and I think this patch
can be dropped.

Thanks,
Leon

> 
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
>  target-mips/translate_init.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index e81a831..1094baa 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -273,6 +273,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_Status_rw_bitmask = 0x3678FF1F,
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>                      (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 32,
>          .PABITS = 32,
>          .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
> @@ -303,6 +304,7 @@ static const mips_def_t mips_defs[] =
>                      (0xff << CP0TCSt_TASID),
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>                      (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
> +        .CP1_fcr31 = 0,
>          .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
>          .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
>          .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
> @@ -343,6 +345,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_Status_rw_bitmask = 0x3778FF1F,
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>                      (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 32,
>          .PABITS = 32,
>          .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
> @@ -434,7 +437,7 @@ static const mips_def_t mips_defs[] =
>      },
>      {
>          /* A generic CPU supporting MIPS32 Release 6 ISA.
> -           FIXME: Support IEEE 754-2008 FP.
> +           FIXME: Complete support for IEEE 754-2008 FP.
>                    Eventually this should be replaced by a real CPU model. */
>          .name = "mips32r6-generic",
>          .CP0_PRid = 0x00010000,
> @@ -485,6 +488,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_Status_rw_bitmask = 0x3678FFFF,
>          /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
>          .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 40,
>          .PABITS = 36,
>          .insn_flags = CPU_MIPS3,
> @@ -503,6 +507,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_Status_rw_bitmask = 0x3678FFFF,
>          /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
>          .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 40,
>          .PABITS = 32,
>          .insn_flags = CPU_VR54XX,
> @@ -548,6 +553,7 @@ static const mips_def_t mips_defs[] =
>          /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
>          .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
>                      (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 42,
>          .PABITS = 36,
>          .insn_flags = CPU_MIPS64,
> @@ -575,6 +581,7 @@ static const mips_def_t mips_defs[] =
>          .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
>                      (1 << FCR0_D) | (1 << FCR0_S) |
>                      (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 40,
>          .PABITS = 36,
>          .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
> @@ -601,6 +608,7 @@ static const mips_def_t mips_defs[] =
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
>                      (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
>                      (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 42,
>          .PABITS = 36,
>          .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
> @@ -653,7 +661,7 @@ static const mips_def_t mips_defs[] =
>      },
>      {
>          /* A generic CPU supporting MIPS64 Release 6 ISA.
> -           FIXME: Support IEEE 754-2008 FP.
> +           FIXME: Complete support for IEEE 754-2008 FP.
>                    Eventually this should be replaced by a real CPU model. */
>          .name = "MIPS64R6-generic",
>          .CP0_PRid = 0x00010000,
> @@ -704,6 +712,7 @@ static const mips_def_t mips_defs[] =
>          .CCRes = 2,
>          .CP0_Status_rw_bitmask = 0x35D0FFFF,
>          .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 40,
>          .PABITS = 40,
>          .insn_flags = CPU_LOONGSON2E,
> @@ -722,6 +731,7 @@ static const mips_def_t mips_defs[] =
>          .CCRes = 2,
>          .CP0_Status_rw_bitmask = 0xF5D0FF1F,   /* Bits 7:5 not writable.  */
>          .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 40,
>          .PABITS = 40,
>          .insn_flags = CPU_LOONGSON2F,
> @@ -749,6 +759,7 @@ static const mips_def_t mips_defs[] =
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
>                      (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
>                      (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
> +        .CP1_fcr31 = 0,
>          .SEGBITS = 42,
>          .PABITS = 36,
>          .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,