Re: [Qemu-arm] [PATCH v5 7/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

[Leon Alrae <leon.alrae@imgtec.com>]

On 18/04/16 17:03, Aleksandar Markovic wrote:
> @@ -3049,6 +3050,330 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
>      return wt2;
>  }
>  
> +uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
> +{
> +    uint64_t dt2;
> +
> +    dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
> +    if (get_float_exception_flags(&env->active_fpu.fp_status)
> +            & (float_flag_invalid) {

unnecessary parentheses

> @@ -8919,7 +8920,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
>              TCGv_i64 fp64 = tcg_temp_new_i64();
>  
>              gen_load_fpr32(ctx, fp32, fs);
> -            gen_helper_float_roundl_s(fp64, cpu_env, fp32);
> +            if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {

Why testing the version of the architecture? This will generate wrong
helper for P5600 which is R5 and IEEE 754-2008 compliant.

Leon

> +                gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
> +            } else {
> +                gen_helper_float_round_l_s(fp64, cpu_env, fp32);
> +            }
>              tcg_temp_free_i32(fp32);
>              gen_store_fpr64(ctx, fp64, fd);
>              tcg_temp_free_i64(fp64);