* [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:37 ` Christian König
2025-06-27 3:39 ` [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling Alex Deucher
` (32 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Need to reinit the ring before remapping it and all of
the KIQ handling needs to be within the kiq lock.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8c377ecbb8a75..5e099b5dc9a3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9544,7 +9544,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
spin_lock_irqsave(&kiq->ring_lock, flags);
- if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
+ if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {
spin_unlock_irqrestore(&kiq->ring_lock, flags);
return -ENOMEM;
}
@@ -9564,12 +9564,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
0, 1, 0x20);
gfx_v10_0_ring_emit_reg_wait(kiq_ring,
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
- kiq->pmf->kiq_map_queues(kiq_ring, ring);
amdgpu_ring_commit(kiq_ring);
-
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
if (r)
return r;
@@ -9579,6 +9576,19 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
return r;
}
+ spin_lock_irqsave(&kiq->ring_lock, flags);
+
+ if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+ return -ENOMEM;
+ }
+ kiq->pmf->kiq_map_queues(kiq_ring, ring);
+ amdgpu_ring_commit(kiq_ring);
+ r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+ if (r)
+ return r;
+
r = amdgpu_ring_test_ring(ring);
if (r)
return r;
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence
2025-06-27 3:39 ` [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence Alex Deucher
@ 2025-06-30 8:37 ` Christian König
0 siblings, 0 replies; 43+ messages in thread
From: Christian König @ 2025-06-30 8:37 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> Need to reinit the ring before remapping it and all of
> the KIQ handling needs to be within the kiq lock.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +++++++++++++++-----
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 8c377ecbb8a75..5e099b5dc9a3c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9544,7 +9544,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
>
> spin_lock_irqsave(&kiq->ring_lock, flags);
>
> - if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
> + if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {
> spin_unlock_irqrestore(&kiq->ring_lock, flags);
> return -ENOMEM;
> }
> @@ -9564,12 +9564,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
> 0, 1, 0x20);
> gfx_v10_0_ring_emit_reg_wait(kiq_ring,
> SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
> - kiq->pmf->kiq_map_queues(kiq_ring, ring);
> amdgpu_ring_commit(kiq_ring);
> -
> - spin_unlock_irqrestore(&kiq->ring_lock, flags);
> -
> r = amdgpu_ring_test_ring(kiq_ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> if (r)
> return r;
>
> @@ -9579,6 +9576,19 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
> return r;
> }
>
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> +
> + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> + return -ENOMEM;
> + }
> + kiq->pmf->kiq_map_queues(kiq_ring, ring);
> + amdgpu_ring_commit(kiq_ring);
> + r = amdgpu_ring_test_ring(kiq_ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> + if (r)
> + return r;
> +
> r = amdgpu_ring_test_ring(ring);
> if (r)
> return r;
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
2025-06-27 3:39 ` [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:40 ` Christian König
2025-06-27 3:39 ` [PATCH 03/33] drm/amdgpu/sdma: allow caller to handle kernel rings in engine reset Alex Deucher
` (31 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Move the force completion handling into the common
engine reset function. No need to duplicate it for
every IP version.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 5 ++++-
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 17 +----------------
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 6 ++----
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++----
4 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 7e26a44dcc1fd..56939bb1d1a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -590,9 +590,12 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
* to be submitted to the queues after the reset is complete.
*/
if (!ret) {
+ amdgpu_fence_driver_force_completion(gfx_ring);
drm_sched_wqueue_start(&gfx_ring->sched);
- if (adev->sdma.has_page_queue)
+ if (adev->sdma.has_page_queue) {
+ amdgpu_fence_driver_force_completion(page_ring);
drm_sched_wqueue_start(&page_ring->sched);
+ }
}
mutex_unlock(&sdma_instance->engine_reset_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index d3072bca43e3f..572d105420ec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1714,7 +1714,7 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- u32 inst_mask, tmp_mask;
+ u32 inst_mask;
int i, r;
inst_mask = 1 << ring->me;
@@ -1733,21 +1733,6 @@ static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
}
r = sdma_v4_4_2_inst_start(adev, inst_mask, true);
- if (r)
- return r;
-
- tmp_mask = inst_mask;
- for_each_inst(i, tmp_mask) {
- ring = &adev->sdma.instance[i].ring;
-
- amdgpu_fence_driver_force_completion(ring);
-
- if (adev->sdma.has_page_queue) {
- struct amdgpu_ring *page = &adev->sdma.instance[i].page;
-
- amdgpu_fence_driver_force_completion(page);
- }
- }
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 4d72b085b3dd7..ed1706da7deec 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1618,10 +1618,8 @@ static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- return 0;
+
+ return r;
}
static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 42a25150f83ac..b87a4b44fa939 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1534,10 +1534,8 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- return 0;
+
+ return r;
}
static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling
2025-06-27 3:39 ` [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling Alex Deucher
@ 2025-06-30 8:40 ` Christian König
2025-06-30 13:47 ` Alex Deucher
0 siblings, 1 reply; 43+ messages in thread
From: Christian König @ 2025-06-30 8:40 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> Move the force completion handling into the common
> engine reset function. No need to duplicate it for
> every IP version.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 5 ++++-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 17 +----------------
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 6 ++----
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++----
> 4 files changed, 9 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index 7e26a44dcc1fd..56939bb1d1a95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -590,9 +590,12 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
> * to be submitted to the queues after the reset is complete.
> */
> if (!ret) {
> + amdgpu_fence_driver_force_completion(gfx_ring);
> drm_sched_wqueue_start(&gfx_ring->sched);
> - if (adev->sdma.has_page_queue)
> + if (adev->sdma.has_page_queue) {
> + amdgpu_fence_driver_force_completion(page_ring);
Calling amdgpu_fence_driver_force_completion() here sounds like a really bad idea in the first place.
That will mark all fences as completed making it impossible to execute the remaingin work.
Regards,
Christian.
> drm_sched_wqueue_start(&page_ring->sched);
> + }
> }
> mutex_unlock(&sdma_instance->engine_reset_mutex);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index d3072bca43e3f..572d105420ec3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -1714,7 +1714,7 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
> static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 inst_mask, tmp_mask;
> + u32 inst_mask;
> int i, r;
>
> inst_mask = 1 << ring->me;
> @@ -1733,21 +1733,6 @@ static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
> }
>
> r = sdma_v4_4_2_inst_start(adev, inst_mask, true);
> - if (r)
> - return r;
> -
> - tmp_mask = inst_mask;
> - for_each_inst(i, tmp_mask) {
> - ring = &adev->sdma.instance[i].ring;
> -
> - amdgpu_fence_driver_force_completion(ring);
> -
> - if (adev->sdma.has_page_queue) {
> - struct amdgpu_ring *page = &adev->sdma.instance[i].page;
> -
> - amdgpu_fence_driver_force_completion(page);
> - }
> - }
>
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 4d72b085b3dd7..ed1706da7deec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -1618,10 +1618,8 @@ static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
>
> r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> - if (r)
> - return r;
> - amdgpu_fence_driver_force_completion(ring);
> - return 0;
> +
> + return r;
> }
>
> static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 42a25150f83ac..b87a4b44fa939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1534,10 +1534,8 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
> r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
>
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> - if (r)
> - return r;
> - amdgpu_fence_driver_force_completion(ring);
> - return 0;
> +
> + return r;
> }
>
> static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling
2025-06-30 8:40 ` Christian König
@ 2025-06-30 13:47 ` Alex Deucher
0 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-30 13:47 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx, sasundar
On Mon, Jun 30, 2025 at 4:48 AM Christian König
<christian.koenig@amd.com> wrote:
>
> On 27.06.25 05:39, Alex Deucher wrote:
> > Move the force completion handling into the common
> > engine reset function. No need to duplicate it for
> > every IP version.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 5 ++++-
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 17 +----------------
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 6 ++----
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++----
> > 4 files changed, 9 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > index 7e26a44dcc1fd..56939bb1d1a95 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > @@ -590,9 +590,12 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
> > * to be submitted to the queues after the reset is complete.
> > */
> > if (!ret) {
> > + amdgpu_fence_driver_force_completion(gfx_ring);
> > drm_sched_wqueue_start(&gfx_ring->sched);
> > - if (adev->sdma.has_page_queue)
> > + if (adev->sdma.has_page_queue) {
> > + amdgpu_fence_driver_force_completion(page_ring);
>
> Calling amdgpu_fence_driver_force_completion() here sounds like a really bad idea in the first place.
>
> That will mark all fences as completed making it impossible to execute the remaingin work.
That is the current behavior of the ring reset code so this just moves
the existing code around. Also, SDMA 5.x and older is a bit special
because the hardware only supports engine reset (all queues) so when
we reset we lose all the queues. Also SDMA resets can come in via KFD
as well so at this point, we just mark everything as lost when we
reset the engine. This could potentially be optimized in the future.
I've done this for SDMA 5.x later in the series.
Alex
>
> Regards,
> Christian.
>
> > drm_sched_wqueue_start(&page_ring->sched);
> > + }
> > }
> > mutex_unlock(&sdma_instance->engine_reset_mutex);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > index d3072bca43e3f..572d105420ec3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > @@ -1714,7 +1714,7 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
> > static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
> > {
> > struct amdgpu_device *adev = ring->adev;
> > - u32 inst_mask, tmp_mask;
> > + u32 inst_mask;
> > int i, r;
> >
> > inst_mask = 1 << ring->me;
> > @@ -1733,21 +1733,6 @@ static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
> > }
> >
> > r = sdma_v4_4_2_inst_start(adev, inst_mask, true);
> > - if (r)
> > - return r;
> > -
> > - tmp_mask = inst_mask;
> > - for_each_inst(i, tmp_mask) {
> > - ring = &adev->sdma.instance[i].ring;
> > -
> > - amdgpu_fence_driver_force_completion(ring);
> > -
> > - if (adev->sdma.has_page_queue) {
> > - struct amdgpu_ring *page = &adev->sdma.instance[i].page;
> > -
> > - amdgpu_fence_driver_force_completion(page);
> > - }
> > - }
> >
> > return r;
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index 4d72b085b3dd7..ed1706da7deec 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -1618,10 +1618,8 @@ static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
> >
> > r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
> > amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> > - if (r)
> > - return r;
> > - amdgpu_fence_driver_force_completion(ring);
> > - return 0;
> > +
> > + return r;
> > }
> >
> > static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > index 42a25150f83ac..b87a4b44fa939 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > @@ -1534,10 +1534,8 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
> > r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
> >
> > amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> > - if (r)
> > - return r;
> > - amdgpu_fence_driver_force_completion(ring);
> > - return 0;
> > +
> > + return r;
> > }
> >
> > static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 03/33] drm/amdgpu/sdma: allow caller to handle kernel rings in engine reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
2025-06-27 3:39 ` [PATCH 01/33] drm/amdgpu/gfx10: fix KGQ reset sequence Alex Deucher
2025-06-27 3:39 ` [PATCH 02/33] drm/amdgpu/sdma: consolidate engine reset handling Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code Alex Deucher
` (30 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Add a parameter to amdgpu_sdma_reset_engine() to let the
caller handle the kernel rings. This allows the kernel
rings to back up their unprocessed state if the reset comes in
via the drm scheduler rather than KFD.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 44 +++++++++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
6 files changed, 32 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 56939bb1d1a95..8b8a04138711c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -545,10 +545,13 @@ static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)
* amdgpu_sdma_reset_engine - Reset a specific SDMA engine
* @adev: Pointer to the AMDGPU device
* @instance_id: Logical ID of the SDMA engine instance to reset
+ * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
+ * will handle it.
*
* Returns: 0 on success, or a negative error code on failure.
*/
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
+ bool caller_handles_kernel_queues)
{
int ret = 0;
struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id];
@@ -556,14 +559,17 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
struct amdgpu_ring *page_ring = &sdma_instance->page;
mutex_lock(&sdma_instance->engine_reset_mutex);
- /* Stop the scheduler's work queue for the GFX and page rings if they are running.
- * This ensures that no new tasks are submitted to the queues while
- * the reset is in progress.
- */
- drm_sched_wqueue_stop(&gfx_ring->sched);
- if (adev->sdma.has_page_queue)
- drm_sched_wqueue_stop(&page_ring->sched);
+ if (!caller_handles_kernel_queues) {
+ /* Stop the scheduler's work queue for the GFX and page rings if they are running.
+ * This ensures that no new tasks are submitted to the queues while
+ * the reset is in progress.
+ */
+ drm_sched_wqueue_stop(&gfx_ring->sched);
+
+ if (adev->sdma.has_page_queue)
+ drm_sched_wqueue_stop(&page_ring->sched);
+ }
if (sdma_instance->funcs->stop_kernel_queue) {
sdma_instance->funcs->stop_kernel_queue(gfx_ring);
@@ -585,16 +591,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
}
exit:
- /* Restart the scheduler's work queue for the GFX and page rings
- * if they were stopped by this function. This allows new tasks
- * to be submitted to the queues after the reset is complete.
- */
- if (!ret) {
- amdgpu_fence_driver_force_completion(gfx_ring);
- drm_sched_wqueue_start(&gfx_ring->sched);
- if (adev->sdma.has_page_queue) {
- amdgpu_fence_driver_force_completion(page_ring);
- drm_sched_wqueue_start(&page_ring->sched);
+ if (!caller_handles_kernel_queues) {
+ /* Restart the scheduler's work queue for the GFX and page rings
+ * if they were stopped by this function. This allows new tasks
+ * to be submitted to the queues after the reset is complete.
+ */
+ if (!ret) {
+ amdgpu_fence_driver_force_completion(gfx_ring);
+ drm_sched_wqueue_start(&gfx_ring->sched);
+ if (adev->sdma.has_page_queue) {
+ amdgpu_fence_driver_force_completion(page_ring);
+ drm_sched_wqueue_start(&page_ring->sched);
+ }
}
}
mutex_unlock(&sdma_instance->engine_reset_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5f8951bbb6f4..34311f32be4c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -172,7 +172,8 @@ struct amdgpu_buffer_funcs {
uint32_t byte_count);
};
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id);
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
+ bool caller_handles_kernel_queues);
#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 572d105420ec3..c0c418aa2c299 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1668,7 +1668,7 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
return -EOPNOTSUPP;
amdgpu_amdkfd_suspend(adev, true);
- r = amdgpu_sdma_reset_engine(adev, id);
+ r = amdgpu_sdma_reset_engine(adev, id, false);
amdgpu_amdkfd_resume(adev, true);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index ed1706da7deec..5a1098bdd8256 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1548,7 +1548,7 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
int r;
amdgpu_amdkfd_suspend(adev, true);
- r = amdgpu_sdma_reset_engine(adev, inst_id);
+ r = amdgpu_sdma_reset_engine(adev, inst_id, false);
amdgpu_amdkfd_resume(adev, true);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b87a4b44fa939..6843c2c3d71f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1461,7 +1461,7 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,
int r;
amdgpu_amdkfd_suspend(adev, true);
- r = amdgpu_sdma_reset_engine(adev, inst_id);
+ r = amdgpu_sdma_reset_engine(adev, inst_id, false);
amdgpu_amdkfd_resume(adev, true);
return r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 76359c6a3f3a4..f0d19f6ed9ba8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2312,7 +2312,7 @@ static int reset_hung_queues_sdma(struct device_queue_manager *dqm)
continue;
/* Reset engine and check. */
- if (amdgpu_sdma_reset_engine(dqm->dev->adev, i) ||
+ if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) ||
dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
!set_sdma_queue_as_reset(dqm, doorbell_off)) {
r = -ENOTRECOVERABLE;
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (2 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 03/33] drm/amdgpu/sdma: allow caller to handle kernel rings in engine reset Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:52 ` Christian König
2025-06-27 3:39 ` [PATCH 05/33] drm/amdgpu/sdma5.2: " Alex Deucher
` (29 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
There no need to save the ring ptrs. Just reset them.
This cleans up a conditional in the resume code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 5a1098bdd8256..5f4c6a99b06dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -680,12 +680,11 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
*
* @adev: amdgpu_device pointer
* @i: instance
- * @restore: used to restore wptr when restart
*
- * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
+ * Set up the gfx DMA ring buffers and enable them.
* Return 0 for success.
*/
-static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
+static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
@@ -713,17 +712,10 @@ static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- if (restore) {
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
- } else {
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
- }
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
/* setup the wptr shadow polling */
wptr_gpu_addr = ring->wptr_gpu_addr;
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
@@ -751,8 +743,7 @@ static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
ring->gpu_addr >> 40);
- if (!restore)
- ring->wptr = 0;
+ ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
@@ -851,7 +842,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
int i, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
- r = sdma_v5_0_gfx_resume_instance(adev, i, false);
+ r = sdma_v5_0_gfx_resume_instance(adev, i);
if (r)
return r;
}
@@ -1616,7 +1607,7 @@ static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
- r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
+ r = sdma_v5_0_gfx_resume_instance(adev, inst_id);
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
return r;
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code
2025-06-27 3:39 ` [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code Alex Deucher
@ 2025-06-30 8:52 ` Christian König
0 siblings, 0 replies; 43+ messages in thread
From: Christian König @ 2025-06-30 8:52 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> There no need to save the ring ptrs. Just reset them.
> This cleans up a conditional in the resume code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 27 +++++++++-----------------
> 1 file changed, 9 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 5a1098bdd8256..5f4c6a99b06dc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -680,12 +680,11 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
> *
> * @adev: amdgpu_device pointer
> * @i: instance
> - * @restore: used to restore wptr when restart
> *
> - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
> + * Set up the gfx DMA ring buffers and enable them.
> * Return 0 for success.
> */
> -static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
> +static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
> {
> struct amdgpu_ring *ring;
> u32 rb_cntl, ib_cntl;
> @@ -713,17 +712,10 @@ static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
>
> /* Initialize the ring buffer's read and write pointers */
> - if (restore) {
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> - } else {
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
> - }
> + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
> /* setup the wptr shadow polling */
> wptr_gpu_addr = ring->wptr_gpu_addr;
> WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
> @@ -751,8 +743,7 @@ static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
> ring->gpu_addr >> 40);
>
> - if (!restore)
> - ring->wptr = 0;
> + ring->wptr = 0;
>
> /* before programing wptr to a less value, need set minor_ptr_update first */
> WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
> @@ -851,7 +842,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
> int i, r;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - r = sdma_v5_0_gfx_resume_instance(adev, i, false);
> + r = sdma_v5_0_gfx_resume_instance(adev, i);
> if (r)
> return r;
> }
> @@ -1616,7 +1607,7 @@ static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
> freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
> WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
>
> - r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
> + r = sdma_v5_0_gfx_resume_instance(adev, inst_id);
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
>
> return r;
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 05/33] drm/amdgpu/sdma5.2: clean up resume code
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (3 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 04/33] drm/amdgpu/sdma5: clean up resume code Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:53 ` Christian König
2025-06-27 3:39 ` [PATCH 06/33] drm/amdgpu/sdma6: " Alex Deucher
` (28 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
There no need to save the ring ptrs. Just reset them.
This cleans up a conditional in the resume code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 6843c2c3d71f5..b9498697ef41c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -528,13 +528,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
*
* @adev: amdgpu_device pointer
* @i: instance
- * @restore: used to restore wptr when restart
*
- * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
+ * Set up the gfx DMA ring buffers and enable them.
* Return 0 for success.
*/
-static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
+static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
@@ -562,17 +561,10 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- if (restore) {
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
- } else {
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
- }
+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
/* setup the wptr shadow polling */
wptr_gpu_addr = ring->wptr_gpu_addr;
@@ -599,8 +591,7 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
- if (!restore)
- ring->wptr = 0;
+ ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
@@ -698,7 +689,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
int i, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
- r = sdma_v5_2_gfx_resume_instance(adev, i, false);
+ r = sdma_v5_2_gfx_resume_instance(adev, i);
if (r)
return r;
}
@@ -1531,7 +1522,7 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
- r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
+ r = sdma_v5_2_gfx_resume_instance(adev, inst_id);
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 05/33] drm/amdgpu/sdma5.2: clean up resume code
2025-06-27 3:39 ` [PATCH 05/33] drm/amdgpu/sdma5.2: " Alex Deucher
@ 2025-06-30 8:53 ` Christian König
0 siblings, 0 replies; 43+ messages in thread
From: Christian König @ 2025-06-30 8:53 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> There no need to save the ring ptrs. Just reset them.
> This cleans up a conditional in the resume code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 27 +++++++++-----------------
> 1 file changed, 9 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 6843c2c3d71f5..b9498697ef41c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -528,13 +528,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
> *
> * @adev: amdgpu_device pointer
> * @i: instance
> - * @restore: used to restore wptr when restart
> *
> - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
> + * Set up the gfx DMA ring buffers and enable them.
> * Return 0 for success.
> */
>
> -static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
> +static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i)
> {
> struct amdgpu_ring *ring;
> u32 rb_cntl, ib_cntl;
> @@ -562,17 +561,10 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
>
> /* Initialize the ring buffer's read and write pointers */
> - if (restore) {
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> - } else {
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
> - }
> + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
>
> /* setup the wptr shadow polling */
> wptr_gpu_addr = ring->wptr_gpu_addr;
> @@ -599,8 +591,7 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
> WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
>
> - if (!restore)
> - ring->wptr = 0;
> + ring->wptr = 0;
>
> /* before programing wptr to a less value, need set minor_ptr_update first */
> WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
> @@ -698,7 +689,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
> int i, r;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - r = sdma_v5_2_gfx_resume_instance(adev, i, false);
> + r = sdma_v5_2_gfx_resume_instance(adev, i);
> if (r)
> return r;
> }
> @@ -1531,7 +1522,7 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
> freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
> WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
>
> - r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
> + r = sdma_v5_2_gfx_resume_instance(adev, inst_id);
>
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 06/33] drm/amdgpu/sdma6: clean up resume code
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (4 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 05/33] drm/amdgpu/sdma5.2: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:55 ` Christian König
2025-06-27 3:39 ` [PATCH 07/33] drm/amdgpu/sdma7: " Alex Deucher
` (27 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
There no need to save the ring ptrs. Just reset them.
This cleans up a conditional in the resume code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 103e5ec7aa63b..455f1a8a07ad4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -474,12 +474,11 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
*
* @adev: amdgpu_device pointer
* @i: instance
- * @restore: used to restore wptr when restart
*
- * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
+ * Set up the gfx DMA ring buffers and enable them.
* Return 0 for success.
*/
-static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
+static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
@@ -506,17 +505,10 @@ static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- if (restore) {
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
- } else {
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
- }
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
/* setup the wptr shadow polling */
wptr_gpu_addr = ring->wptr_gpu_addr;
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
@@ -537,8 +529,7 @@ static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
- if (!restore)
- ring->wptr = 0;
+ ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
@@ -633,7 +624,7 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
int i, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
- r = sdma_v6_0_gfx_resume_instance(adev, i, false);
+ r = sdma_v6_0_gfx_resume_instance(adev, i);
if (r)
return r;
}
@@ -1592,7 +1583,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring,
if (r)
return r;
- r = sdma_v6_0_gfx_resume_instance(adev, i, true);
+ r = sdma_v6_0_gfx_resume_instance(adev, i);
if (r)
return r;
amdgpu_fence_driver_force_completion(ring);
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 06/33] drm/amdgpu/sdma6: clean up resume code
2025-06-27 3:39 ` [PATCH 06/33] drm/amdgpu/sdma6: " Alex Deucher
@ 2025-06-30 8:55 ` Christian König
0 siblings, 0 replies; 43+ messages in thread
From: Christian König @ 2025-06-30 8:55 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> There no need to save the ring ptrs. Just reset them.
> This cleans up a conditional in the resume code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 27 +++++++++-----------------
> 1 file changed, 9 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index 103e5ec7aa63b..455f1a8a07ad4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -474,12 +474,11 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
> *
> * @adev: amdgpu_device pointer
> * @i: instance
> - * @restore: used to restore wptr when restart
> *
> - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
> + * Set up the gfx DMA ring buffers and enable them.
> * Return 0 for success.
> */
> -static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
> +static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
> {
> struct amdgpu_ring *ring;
> u32 rb_cntl, ib_cntl;
> @@ -506,17 +505,10 @@ static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
>
> /* Initialize the ring buffer's read and write pointers */
> - if (restore) {
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> - } else {
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
> - }
> + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
> + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
> /* setup the wptr shadow polling */
> wptr_gpu_addr = ring->wptr_gpu_addr;
> WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
> @@ -537,8 +529,7 @@ static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
> WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
>
> - if (!restore)
> - ring->wptr = 0;
> + ring->wptr = 0;
>
> /* before programing wptr to a less value, need set minor_ptr_update first */
> WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
> @@ -633,7 +624,7 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
> int i, r;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - r = sdma_v6_0_gfx_resume_instance(adev, i, false);
> + r = sdma_v6_0_gfx_resume_instance(adev, i);
> if (r)
> return r;
> }
> @@ -1592,7 +1583,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring,
> if (r)
> return r;
>
> - r = sdma_v6_0_gfx_resume_instance(adev, i, true);
> + r = sdma_v6_0_gfx_resume_instance(adev, i);
> if (r)
> return r;
> amdgpu_fence_driver_force_completion(ring);
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 07/33] drm/amdgpu/sdma7: clean up resume code
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (5 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 06/33] drm/amdgpu/sdma6: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-30 8:56 ` Christian König
2025-06-27 3:39 ` [PATCH 08/33] drm/amdgpu: track ring state associated with a fence Alex Deucher
` (26 subsequent siblings)
33 siblings, 1 reply; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
There no need to save the ring ptrs. Just reset them.
This cleans up a conditional in the resume code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 28 +++++++++-----------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 99a080bad2a3d..95e54a1180ec6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -467,12 +467,11 @@ static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
*
* @adev: amdgpu_device pointer
* @i: instance
- * @restore: used to restore wptr when restart
*
- * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
+ * Set up the gfx DMA ring buffers and enable them.
* Return 0 for success.
*/
-static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
+static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
@@ -498,17 +497,11 @@ static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- if (restore) {
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
- } else {
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
- }
+ WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
+
/* setup the wptr shadow polling */
wptr_gpu_addr = ring->wptr_gpu_addr;
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
@@ -533,8 +526,7 @@ static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
- if (!restore)
- ring->wptr = 0;
+ ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
@@ -635,7 +627,7 @@ static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)
int i, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
- r = sdma_v7_0_gfx_resume_instance(adev, i, false);
+ r = sdma_v7_0_gfx_resume_instance(adev, i);
if (r)
return r;
}
@@ -828,7 +820,7 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring,
if (r)
return r;
- r = sdma_v7_0_gfx_resume_instance(adev, i, true);
+ r = sdma_v7_0_gfx_resume_instance(adev, i);
if (r)
return r;
amdgpu_fence_driver_force_completion(ring);
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 07/33] drm/amdgpu/sdma7: clean up resume code
2025-06-27 3:39 ` [PATCH 07/33] drm/amdgpu/sdma7: " Alex Deucher
@ 2025-06-30 8:56 ` Christian König
0 siblings, 0 replies; 43+ messages in thread
From: Christian König @ 2025-06-30 8:56 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, sasundar
On 27.06.25 05:39, Alex Deucher wrote:
> There no need to save the ring ptrs. Just reset them.
> This cleans up a conditional in the resume code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 28 +++++++++-----------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 99a080bad2a3d..95e54a1180ec6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -467,12 +467,11 @@ static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
> *
> * @adev: amdgpu_device pointer
> * @i: instance
> - * @restore: used to restore wptr when restart
> *
> - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
> + * Set up the gfx DMA ring buffers and enable them.
> * Return 0 for success.
> */
> -static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
> +static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
> {
> struct amdgpu_ring *ring;
> u32 rb_cntl, ib_cntl;
> @@ -498,17 +497,11 @@ static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
>
> /* Initialize the ring buffer's read and write pointers */
> - if (restore) {
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> - } else {
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
> - WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
> - }
> + WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
> + WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
> + WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
> +
> /* setup the wptr shadow polling */
> wptr_gpu_addr = ring->wptr_gpu_addr;
> WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
> @@ -533,8 +526,7 @@ static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
> WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
> WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
>
> - if (!restore)
> - ring->wptr = 0;
> + ring->wptr = 0;
>
> /* before programing wptr to a less value, need set minor_ptr_update first */
> WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
> @@ -635,7 +627,7 @@ static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)
> int i, r;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - r = sdma_v7_0_gfx_resume_instance(adev, i, false);
> + r = sdma_v7_0_gfx_resume_instance(adev, i);
> if (r)
> return r;
> }
> @@ -828,7 +820,7 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring,
> if (r)
> return r;
>
> - r = sdma_v7_0_gfx_resume_instance(adev, i, true);
> + r = sdma_v7_0_gfx_resume_instance(adev, i);
> if (r)
> return r;
> amdgpu_fence_driver_force_completion(ring);
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 08/33] drm/amdgpu: track ring state associated with a fence
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (6 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 07/33] drm/amdgpu/sdma7: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 09/33] drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset Alex Deucher
` (25 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
We need to know the wptr and sequence number associated
with a fence so that we can re-emit the unprocessed state
after a ring reset. Pre-allocate storage space for
the ring buffer contents and add helpers to save off
and re-emit the unprocessed state so that it can be
re-emitted after the queue is reset.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 90 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 15 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 67 +++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 18 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +
6 files changed, 195 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 2d6b2b486baf7..3f2080aecd5a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -120,6 +120,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
am_fence = kzalloc(sizeof(*am_fence), GFP_KERNEL);
if (!am_fence)
return -ENOMEM;
+ am_fence->context = 0;
} else {
am_fence = af;
}
@@ -127,6 +128,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
am_fence->ring = ring;
seq = ++ring->fence_drv.sync_seq;
+ am_fence->seq = seq;
if (af) {
dma_fence_init(fence, &amdgpu_job_fence_ops,
&ring->fence_drv.lock,
@@ -141,6 +143,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT);
+ amdgpu_fence_save_wptr(fence);
pm_runtime_get_noresume(adev_to_drm(adev)->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
if (unlikely(rcu_dereference_protected(*ptr, 1))) {
@@ -253,6 +256,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
do {
struct dma_fence *fence, **ptr;
+ struct amdgpu_fence *am_fence;
++last_seq;
last_seq &= drv->num_fences_mask;
@@ -265,6 +269,12 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
if (!fence)
continue;
+ /* Save the wptr in the fence driver so we know what the last processed
+ * wptr was. This is required for re-emitting the ring state for
+ * queues that are reset but are not guilty and thus have no guilty fence.
+ */
+ am_fence = container_of(fence, struct amdgpu_fence, base);
+ drv->signalled_wptr = am_fence->wptr;
dma_fence_signal(fence);
dma_fence_put(fence);
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
@@ -727,6 +737,86 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
amdgpu_fence_process(ring);
}
+
+/**
+ * Kernel queue reset handling
+ *
+ * The driver can reset individual queues for most engines, but those queues
+ * may contain work from multiple contexts. Resetting the queue will reset
+ * lose all of that state. In order to minimize the collateral damage, the
+ * driver will save the ring contents which are not associated with the guilty
+ * context prior to resetting the queue. After resetting the queue the queue
+ * contents from the other contexts is re-emitted to the rings so that it can
+ * be processed by the engine. To handle this, we save the queue's write
+ * pointer (wptr) in the fences associated with each context. If we get a
+ * queue timeout, we can then use the wptrs from the fences to determine
+ * which data needs to be saved out of the queue's ring buffer.
+ */
+
+/**
+ * amdgpu_fence_driver_guilty_force_completion - force signal of specified sequence
+ *
+ * @fence: fence of the ring to signal
+ *
+ */
+void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence)
+{
+ dma_fence_set_error(&fence->base, -ETIME);
+ amdgpu_fence_write(fence->ring, fence->seq);
+ amdgpu_fence_process(fence->ring);
+}
+
+void amdgpu_fence_save_wptr(struct dma_fence *fence)
+{
+ struct amdgpu_fence *am_fence = container_of(fence, struct amdgpu_fence, base);
+
+ am_fence->wptr = am_fence->ring->wptr;
+}
+
+static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring,
+ u64 start_wptr, u32 end_wptr)
+{
+ unsigned int first_idx = start_wptr & ring->buf_mask;
+ unsigned int last_idx = end_wptr & ring->buf_mask;
+ unsigned int i;
+
+ /* Backup the contents of the ring buffer. */
+ for (i = first_idx; i != last_idx; ++i, i &= ring->buf_mask)
+ ring->ring_backup[ring->ring_backup_entries_to_copy++] = ring->ring[i];
+}
+
+void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence)
+{
+ struct dma_fence *unprocessed;
+ struct dma_fence __rcu **ptr;
+ struct amdgpu_fence *fence;
+ u64 wptr, i, seqno;
+
+ seqno = amdgpu_fence_read(ring);
+ wptr = ring->fence_drv.signalled_wptr;
+ ring->ring_backup_entries_to_copy = 0;
+
+ for (i = seqno + 1; i <= ring->fence_drv.sync_seq; ++i) {
+ ptr = &ring->fence_drv.fences[i & ring->fence_drv.num_fences_mask];
+ rcu_read_lock();
+ unprocessed = rcu_dereference(*ptr);
+
+ if (unprocessed && !dma_fence_is_signaled(unprocessed)) {
+ fence = container_of(unprocessed, struct amdgpu_fence, base);
+
+ /* save everything if the ring is not guilty, otherwise
+ * just save the content from other contexts.
+ */
+ if (!guilty_fence || (fence->context != guilty_fence->context))
+ amdgpu_ring_backup_unprocessed_command(ring, wptr,
+ fence->wptr);
+ wptr = fence->wptr;
+ }
+ rcu_read_unlock();
+ }
+}
+
/*
* Common fence implementation
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 206b70acb29a0..7d9bcb72e8dd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -139,7 +139,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
int vmid = AMDGPU_JOB_GET_VMID(job);
bool need_pipe_sync = false;
unsigned int cond_exec;
-
unsigned int i;
int r = 0;
@@ -156,6 +155,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
gds_va = job->gds_va;
init_shadow = job->init_shadow;
af = &job->hw_fence;
+ /* Save the context of the job for reset handling.
+ * The driver needs this so it can skip the ring
+ * contents for guilty contexts.
+ */
+ af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0;
} else {
vm = NULL;
fence_ctx = 0;
@@ -307,8 +311,17 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
ring->funcs->emit_wave_limit(ring, false);
+ /* Save the wptr associated with this fence.
+ * This must be last for resets to work properly
+ * as we need to save the wptr associated with this
+ * fence so we know what rings contents to backup
+ * after we reset the queue.
+ */
+ amdgpu_fence_save_wptr(*f);
+
amdgpu_ring_ib_end(ring);
amdgpu_ring_commit(ring);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index f0b7080dccb8d..45febdc2f3493 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -89,8 +89,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
{
struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
struct amdgpu_job *job = to_amdgpu_job(s_job);
- struct amdgpu_task_info *ti;
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_task_info *ti;
int idx, r;
if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
@@ -135,7 +135,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
} else if (amdgpu_gpu_recovery && ring->funcs->reset) {
dev_err(adev->dev, "Starting %s ring reset\n",
s_job->sched->name);
- r = amdgpu_ring_reset(ring, job->vmid, NULL);
+ r = amdgpu_ring_reset(ring, job->vmid, &job->hw_fence);
if (!r) {
atomic_inc(&ring->adev->gpu_reset_counter);
dev_err(adev->dev, "Ring %s reset succeeded\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 426834806fbf2..09d7681b7a754 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -99,6 +99,29 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
return 0;
}
+/**
+ * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit
+ *
+ * @ring: amdgpu_ring structure holding ring information
+ * @ndw: number of dwords to allocate in the ring buffer
+ *
+ * Allocate @ndw dwords in the ring buffer (all asics).
+ * doesn't check the max_dw limit as we may be reemitting
+ * several submissions.
+ */
+static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
+{
+ /* Align requested size with padding so unlock_commit can
+ * pad safely */
+ ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
+
+ ring->count_dw = ndw;
+ ring->wptr_old = ring->wptr;
+
+ if (ring->funcs->begin_use)
+ ring->funcs->begin_use(ring);
+}
+
/** amdgpu_ring_insert_nop - insert NOP packets
*
* @ring: amdgpu_ring structure holding ring information
@@ -333,6 +356,12 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
/* Initialize cached_rptr to 0 */
ring->cached_rptr = 0;
+ if (!ring->ring_backup) {
+ ring->ring_backup = kvzalloc(ring->ring_size, GFP_KERNEL);
+ if (!ring->ring_backup)
+ return -ENOMEM;
+ }
+
/* Allocate ring buffer */
if (ring->ring_obj == NULL) {
r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
@@ -342,6 +371,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
(void **)&ring->ring);
if (r) {
dev_err(adev->dev, "(%d) ring create failed\n", r);
+ kvfree(ring->ring_backup);
return r;
}
amdgpu_ring_clear_ring(ring);
@@ -385,6 +415,8 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
amdgpu_bo_free_kernel(&ring->ring_obj,
&ring->gpu_addr,
(void **)&ring->ring);
+ kvfree(ring->ring_backup);
+ ring->ring_backup = NULL;
dma_fence_put(ring->vmid_wait);
ring->vmid_wait = NULL;
@@ -753,3 +785,38 @@ bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring)
return true;
}
+
+void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence)
+{
+ /* Stop the scheduler to prevent anybody else from touching the ring buffer. */
+ drm_sched_wqueue_stop(&ring->sched);
+ /* back up the non-guilty commands */
+ amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence);
+}
+
+int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence)
+{
+ unsigned int i;
+ int r;
+
+ /* verify that the ring is functional */
+ r = amdgpu_ring_test_ring(ring);
+ if (r)
+ return r;
+
+ /* signal the fence of the bad job */
+ if (guilty_fence)
+ amdgpu_fence_driver_guilty_force_completion(guilty_fence);
+ /* Re-emit the non-guilty commands */
+ if (ring->ring_backup_entries_to_copy) {
+ amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy);
+ for (i = 0; i < ring->ring_backup_entries_to_copy; i++)
+ amdgpu_ring_write(ring, ring->ring_backup[i]);
+ amdgpu_ring_commit(ring);
+ }
+ /* Start the scheduler again */
+ drm_sched_wqueue_start(&ring->sched);
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 784ba2ec354c7..309e7bb6001bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -118,6 +118,7 @@ struct amdgpu_fence_driver {
/* sync_seq is protected by ring emission lock */
uint32_t sync_seq;
atomic_t last_seq;
+ u64 signalled_wptr;
bool initialized;
struct amdgpu_irq_src *irq_src;
unsigned irq_type;
@@ -141,6 +142,12 @@ struct amdgpu_fence {
/* RB, DMA, etc. */
struct amdgpu_ring *ring;
ktime_t start_timestamp;
+
+ /* wptr for the fence for resets */
+ u64 wptr;
+ /* fence context for resets */
+ u64 context;
+ uint32_t seq;
};
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
@@ -148,6 +155,8 @@ extern const struct drm_sched_backend_ops amdgpu_sched_ops;
void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
+void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence);
+void amdgpu_fence_save_wptr(struct dma_fence *fence);
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
@@ -284,6 +293,9 @@ struct amdgpu_ring {
struct amdgpu_bo *ring_obj;
uint32_t *ring;
+ /* backups for resets */
+ uint32_t *ring_backup;
+ unsigned int ring_backup_entries_to_copy;
unsigned rptr_offs;
u64 rptr_gpu_addr;
volatile u32 *rptr_cpu_addr;
@@ -550,4 +562,10 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev);
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
+void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence);
+void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence);
+int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f042372d9f2e6..ea9b0f050f799 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -765,6 +765,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
bool cleaner_shader_needed = false;
bool pasid_mapping_needed = false;
struct dma_fence *fence = NULL;
+ struct amdgpu_fence *af;
unsigned int patch;
int r;
@@ -830,6 +831,9 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
r = amdgpu_fence_emit(ring, &fence, NULL, 0);
if (r)
return r;
+ /* this is part of the job's context */
+ af = container_of(fence, struct amdgpu_fence, base);
+ af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0;
}
if (vm_flush_needed) {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 09/33] drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (7 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 08/33] drm/amdgpu: track ring state associated with a fence Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 10/33] drm/amdgpu/gfx9.4.3: " Alex Deucher
` (24 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76ba664efecb3..30f6b04cf82e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -7187,7 +7187,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
spin_lock_irqsave(&kiq->ring_lock, flags);
@@ -7238,19 +7238,13 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
}
kiq->pmf->kiq_map_queues(kiq_ring, ring);
amdgpu_ring_commit(kiq_ring);
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
if (r) {
DRM_ERROR("fail to remap queue\n");
return r;
}
-
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 10/33] drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (8 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 09/33] drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 11/33] drm/amdgpu/gfx10: re-emit unprocessed state on ring reset Alex Deucher
` (23 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index daed0f187bda5..21bdf9746db7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3567,7 +3567,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
spin_lock_irqsave(&kiq->ring_lock, flags);
@@ -3615,20 +3615,14 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
}
kiq->pmf->kiq_map_queues(kiq_ring, ring);
amdgpu_ring_commit(kiq_ring);
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
if (r) {
dev_err(adev->dev, "fail to remap queue\n");
return r;
}
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
enum amdgpu_gfx_cp_ras_mem_id {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 11/33] drm/amdgpu/gfx10: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (9 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 10/33] drm/amdgpu/gfx9.4.3: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 12/33] drm/amdgpu/gfx11: " Alex Deucher
` (22 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 41 ++++----------------------
1 file changed, 6 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e099b5dc9a3c..65429afb33ec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9046,21 +9046,6 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
ref, mask);
}
-static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
- unsigned int vmid)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t value = 0;
-
- value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
- value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
- value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
- value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
- amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
- WREG32_SOC15(GC, 0, mmSQ_CMD, value);
- amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-}
-
static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
uint32_t me, uint32_t pipe,
@@ -9540,7 +9525,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
spin_lock_irqsave(&kiq->ring_lock, flags);
@@ -9589,12 +9574,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
if (r)
return r;
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
@@ -9613,7 +9593,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
spin_lock_irqsave(&kiq->ring_lock, flags);
@@ -9625,9 +9605,8 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
0, 0);
amdgpu_ring_commit(kiq_ring);
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
if (r)
return r;
@@ -9663,18 +9642,12 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
}
kiq->pmf->kiq_map_queues(kiq_ring, ring);
amdgpu_ring_commit(kiq_ring);
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
r = amdgpu_ring_test_ring(kiq_ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
if (r)
return r;
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
@@ -9909,7 +9882,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
.emit_wreg = gfx_v10_0_ring_emit_wreg,
.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v10_0_ring_soft_recovery,
.emit_mem_sync = gfx_v10_0_emit_mem_sync,
.reset = gfx_v10_0_reset_kgq,
.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
@@ -9950,7 +9922,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
.emit_wreg = gfx_v10_0_ring_emit_wreg,
.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v10_0_ring_soft_recovery,
.emit_mem_sync = gfx_v10_0_emit_mem_sync,
.reset = gfx_v10_0_reset_kcq,
.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 12/33] drm/amdgpu/gfx11: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (10 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 11/33] drm/amdgpu/gfx10: re-emit unprocessed state on ring reset Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 13/33] drm/amdgpu/gfx12: " Alex Deucher
` (21 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35 +++-----------------------
1 file changed, 4 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 37dcec2d07841..04b2e3def5098 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6283,21 +6283,6 @@ static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
ref, mask, 0x20);
}
-static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
- unsigned vmid)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t value = 0;
-
- value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
- value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
- value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
- value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
- amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
- WREG32_SOC15(GC, 0, regSQ_CMD, value);
- amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-}
-
static void
gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
uint32_t me, uint32_t pipe,
@@ -6821,7 +6806,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
if (r) {
@@ -6844,12 +6829,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
return r;
}
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring)
@@ -6992,7 +6972,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
if (r) {
@@ -7013,12 +6993,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
return r;
}
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
@@ -7254,7 +7229,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
.emit_wreg = gfx_v11_0_ring_emit_wreg,
.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v11_0_ring_soft_recovery,
.emit_mem_sync = gfx_v11_0_emit_mem_sync,
.reset = gfx_v11_0_reset_kgq,
.emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,
@@ -7296,7 +7270,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
.emit_wreg = gfx_v11_0_ring_emit_wreg,
.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v11_0_ring_soft_recovery,
.emit_mem_sync = gfx_v11_0_emit_mem_sync,
.reset = gfx_v11_0_reset_kcq,
.emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 13/33] drm/amdgpu/gfx12: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (11 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 12/33] drm/amdgpu/gfx11: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 14/33] drm/amdgpu/sdma5: " Alex Deucher
` (20 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 35 +++-----------------------
1 file changed, 4 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index e4fc42470cf3e..a3be2b46177c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4690,21 +4690,6 @@ static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
ref, mask, 0x20);
}
-static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring,
- unsigned vmid)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t value = 0;
-
- value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
- value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
- value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
- value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
- amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
- WREG32_SOC15(GC, 0, regSQ_CMD, value);
- amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-}
-
static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
uint32_t me, uint32_t pipe,
@@ -5317,7 +5302,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
if (r) {
@@ -5339,12 +5324,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
return r;
}
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)
@@ -5440,7 +5420,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
if (r) {
@@ -5461,12 +5441,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
return r;
}
- r = amdgpu_ring_test_ring(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
@@ -5544,7 +5519,6 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
.emit_wreg = gfx_v12_0_ring_emit_wreg,
.emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v12_0_ring_soft_recovery,
.emit_mem_sync = gfx_v12_0_emit_mem_sync,
.reset = gfx_v12_0_reset_kgq,
.emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
@@ -5583,7 +5557,6 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
.emit_wreg = gfx_v12_0_ring_emit_wreg,
.emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
- .soft_recovery = gfx_v12_0_ring_soft_recovery,
.emit_mem_sync = gfx_v12_0_emit_mem_sync,
.reset = gfx_v12_0_reset_kcq,
.emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 14/33] drm/amdgpu/sdma5: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (12 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 13/33] drm/amdgpu/gfx12: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 15/33] drm/amdgpu/sdma5.2: " Alex Deucher
` (19 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 5f4c6a99b06dc..64210c5a7fba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1535,14 +1535,25 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
- u32 inst_id = ring->me;
int r;
+ if (amdgpu_sriov_vf(adev))
+ return -EINVAL;
+
+ if (ring->me >= adev->sdma.num_instances) {
+ DRM_ERROR("sdma instance not found\n");
+ return -EINVAL;
+ }
+
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
+
amdgpu_amdkfd_suspend(adev, true);
- r = amdgpu_sdma_reset_engine(adev, inst_id, false);
+ r = amdgpu_sdma_reset_engine(adev, ring->me, true);
amdgpu_amdkfd_resume(adev, true);
+ if (r)
+ return r;
- return r;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 15/33] drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (13 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 14/33] drm/amdgpu/sdma5: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 16/33] drm/amdgpu/sdma6: " Alex Deucher
` (18 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b9498697ef41c..58d92225fd5ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1448,14 +1448,25 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,
struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
- u32 inst_id = ring->me;
int r;
+ if (amdgpu_sriov_vf(adev))
+ return -EINVAL;
+
+ if (ring->me >= adev->sdma.num_instances) {
+ DRM_ERROR("sdma instance not found\n");
+ return -EINVAL;
+ }
+
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
+
amdgpu_amdkfd_suspend(adev, true);
- r = amdgpu_sdma_reset_engine(adev, inst_id, false);
+ r = amdgpu_sdma_reset_engine(adev, ring->me, true);
amdgpu_amdkfd_resume(adev, true);
+ if (r)
+ return r;
- return r;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 16/33] drm/amdgpu/sdma6: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (14 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 15/33] drm/amdgpu/sdma5.2: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 17/33] drm/amdgpu/sdma7: " Alex Deucher
` (17 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 455f1a8a07ad4..53cd5511407d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1562,33 +1562,27 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring,
struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
- int i, r;
+ int r;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (ring == &adev->sdma.instance[i].ring)
- break;
- }
-
- if (i == adev->sdma.num_instances) {
+ if (ring->me >= adev->sdma.num_instances) {
DRM_ERROR("sdma instance not found\n");
return -EINVAL;
}
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);
if (r)
return r;
- r = sdma_v6_0_gfx_resume_instance(adev, i);
+ r = sdma_v6_0_gfx_resume_instance(adev, ring->me);
if (r)
return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 17/33] drm/amdgpu/sdma7: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (15 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 16/33] drm/amdgpu/sdma6: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 18/33] drm/amdgpu/jpeg2: " Alex Deucher
` (16 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 95e54a1180ec6..9ed1e00de1760 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -799,33 +799,27 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring,
struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
- int i, r;
+ int r;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (ring == &adev->sdma.instance[i].ring)
- break;
- }
-
- if (i == adev->sdma.num_instances) {
+ if (ring->me >= adev->sdma.num_instances) {
DRM_ERROR("sdma instance not found\n");
return -EINVAL;
}
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);
if (r)
return r;
- r = sdma_v7_0_gfx_resume_instance(adev, i);
+ r = sdma_v7_0_gfx_resume_instance(adev, ring->me);
if (r)
return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
/**
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 18/33] drm/amdgpu/jpeg2: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (16 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 17/33] drm/amdgpu/sdma7: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 19/33] drm/amdgpu/jpeg2.5: " Alex Deucher
` (15 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 781a5a8a83614..cb66eff499662 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -768,17 +768,10 @@ static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v2_0_stop(ring->adev);
jpeg_v2_0_start(ring->adev);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 19/33] drm/amdgpu/jpeg2.5: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (17 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 18/33] drm/amdgpu/jpeg2: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 20/33] drm/amdgpu/jpeg3: " Alex Deucher
` (14 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 5be9cdcae32c1..7432990f77507 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -647,17 +647,10 @@ static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v2_5_stop_inst(ring->adev, ring->me);
jpeg_v2_5_start_inst(ring->adev, ring->me);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 20/33] drm/amdgpu/jpeg3: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (18 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 19/33] drm/amdgpu/jpeg2.5: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 21/33] drm/amdgpu/jpeg4: " Alex Deucher
` (13 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index a24bd833d6442..5598fa40764a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -559,17 +559,10 @@ static int jpeg_v3_0_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v3_0_stop(ring->adev);
jpeg_v3_0_start(ring->adev);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 21/33] drm/amdgpu/jpeg4: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (19 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 20/33] drm/amdgpu/jpeg3: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 22/33] drm/amdgpu/jpeg4.0.3: " Alex Deucher
` (12 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 1d4edd77837d0..e9acbd5afbb7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -724,20 +724,13 @@ static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
if (amdgpu_sriov_vf(ring->adev))
return -EINVAL;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v4_0_stop(ring->adev);
jpeg_v4_0_start(ring->adev);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 22/33] drm/amdgpu/jpeg4.0.3: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (20 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 21/33] drm/amdgpu/jpeg4: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 23/33] drm/amdgpu/jpeg4.0.5: add queue reset Alex Deucher
` (11 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 78441f8fce972..c3f73a2a911b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -1147,20 +1147,13 @@ static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
if (amdgpu_sriov_vf(ring->adev))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v4_0_3_core_stall_reset(ring);
jpeg_v4_0_3_start_jrbc(ring);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 23/33] drm/amdgpu/jpeg4.0.5: add queue reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (21 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 22/33] drm/amdgpu/jpeg4.0.3: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 24/33] drm/amdgpu/jpeg5: " Alex Deucher
` (10 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Add queue reset support for jpeg 4.0.5.
Use the new helpers to re-emit the unprocessed state
after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index 974030a5c03c9..e6e90496135b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -767,6 +767,16 @@ static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static int jpeg_v4_0_5_ring_reset(struct amdgpu_ring *ring,
+ unsigned int vmid,
+ struct amdgpu_fence *timedout_fence)
+{
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
+ jpeg_v4_0_5_stop(ring->adev);
+ jpeg_v4_0_5_start(ring->adev);
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
+}
+
static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
.name = "jpeg_v4_0_5",
.early_init = jpeg_v4_0_5_early_init,
@@ -812,6 +822,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = jpeg_v4_0_5_ring_reset,
};
static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 24/33] drm/amdgpu/jpeg5: add queue reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (22 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 23/33] drm/amdgpu/jpeg4.0.5: add queue reset Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 25/33] drm/amdgpu/jpeg5.0.1: re-emit unprocessed state on ring reset Alex Deucher
` (9 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Add queue reset support for jpeg 5.0.0.
Use the new helpers to re-emit the unprocessed state
after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 31d213ccbe0a8..351e21494365d 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -644,6 +644,19 @@ static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static int jpeg_v5_0_0_ring_reset(struct amdgpu_ring *ring,
+ unsigned int vmid,
+ struct amdgpu_fence *timedout_fence)
+{
+ if (amdgpu_sriov_vf(ring->adev))
+ return -EINVAL;
+
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
+ jpeg_v5_0_0_stop(ring->adev);
+ jpeg_v5_0_0_start(ring->adev);
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
+}
+
static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
.name = "jpeg_v5_0_0",
.early_init = jpeg_v5_0_0_early_init,
@@ -689,6 +702,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
.emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
.emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = jpeg_v5_0_0_ring_reset,
};
static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 25/33] drm/amdgpu/jpeg5.0.1: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (23 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 24/33] drm/amdgpu/jpeg5: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 26/33] drm/amdgpu/vcn4: " Alex Deucher
` (8 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
index 6f8a16da9d608..5473cbaa5c0e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
@@ -838,20 +838,13 @@ static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring,
unsigned int vmid,
struct amdgpu_fence *timedout_fence)
{
- int r;
-
if (amdgpu_sriov_vf(ring->adev))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
jpeg_v5_0_1_core_stall_reset(ring);
jpeg_v5_0_1_init_jrbc(ring);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 26/33] drm/amdgpu/vcn4: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (24 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 25/33] drm/amdgpu/jpeg5.0.1: re-emit unprocessed state on ring reset Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 27/33] drm/amdgpu/vcn4.0.3: " Alex Deucher
` (7 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index eec9133e1b2c4..9bf1a345ac2cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1973,21 +1973,14 @@ static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring,
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
- int r;
if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
vcn_v4_0_stop(vinst);
vcn_v4_0_start(vinst);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 27/33] drm/amdgpu/vcn4.0.3: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (25 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 26/33] drm/amdgpu/vcn4: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 28/33] drm/amdgpu/vcn4.0.5: " Alex Deucher
` (6 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index d8fd32c1e38ec..3bda19b92cde7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1609,7 +1609,7 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring,
if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
vcn_inst = GET_INST(VCN, ring->me);
r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst);
@@ -1624,12 +1624,8 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring,
adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);
vcn_v4_0_3_hw_init_inst(vinst);
vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 28/33] drm/amdgpu/vcn4.0.5: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (26 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 27/33] drm/amdgpu/vcn4.0.3: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 29/33] drm/amdgpu/vcn5: " Alex Deucher
` (5 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 7e37ddea63550..faf2df7ed3fd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1471,21 +1471,14 @@ static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring,
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
- int r;
if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
vcn_v4_0_5_stop(vinst);
vcn_v4_0_5_start(vinst);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 29/33] drm/amdgpu/vcn5: re-emit unprocessed state on ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (27 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 28/33] drm/amdgpu/vcn4.0.5: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:39 ` [PATCH 30/33] drm/amdgpu/vcn: add a helper framework for engine resets Alex Deucher
` (4 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Re-emit the unprocessed state after resetting the queue.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 47c0bcc9e7d80..5997927ac6db1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1198,21 +1198,14 @@ static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring,
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
- int r;
if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
return -EOPNOTSUPP;
- drm_sched_wqueue_stop(&ring->sched);
+ amdgpu_ring_reset_helper_begin(ring, timedout_fence);
vcn_v5_0_0_stop(vinst);
vcn_v5_0_0_start(vinst);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- amdgpu_fence_driver_force_completion(ring);
- drm_sched_wqueue_start(&ring->sched);
- return 0;
+ return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}
static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 30/33] drm/amdgpu/vcn: add a helper framework for engine resets
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (28 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 29/33] drm/amdgpu/vcn5: " Alex Deucher
@ 2025-06-27 3:39 ` Alex Deucher
2025-06-27 3:40 ` [PATCH 31/33] drm/amdgpu/vcn2: implement ring reset Alex Deucher
` (3 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:39 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
With engine resets we reset all queues on the engine rather
than just a single queue. Add a framework to handle this
similar to SDMA.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 76 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +-
2 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index c8885c3d54b33..f1f67521c29ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -134,6 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i)
mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround);
mutex_init(&adev->vcn.inst[i].vcn_pg_lock);
+ mutex_init(&adev->vcn.inst[i].engine_reset_mutex);
atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0);
INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
@@ -1451,3 +1452,78 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,
return ret;
}
+
+/**
+ * amdgpu_vcn_reset_engine - Reset a specific VCN engine
+ * @adev: Pointer to the AMDGPU device
+ * @instance_id: VCN engine instance to reset
+ *
+ * Returns: 0 on success, or a negative error code on failure.
+ */
+static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev,
+ uint32_t instance_id)
+{
+ struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id];
+ int r, i;
+
+ mutex_lock(&vinst->engine_reset_mutex);
+ /* Stop the scheduler's work queue for the dec and enc rings if they are running.
+ * This ensures that no new tasks are submitted to the queues while
+ * the reset is in progress.
+ */
+ drm_sched_wqueue_stop(&vinst->ring_dec.sched);
+ for (i = 0; i < vinst->num_enc_rings; i++)
+ drm_sched_wqueue_stop(&vinst->ring_enc[i].sched);
+
+ /* Perform the VCN reset for the specified instance */
+ r = vinst->reset(vinst);
+ if (r)
+ goto unlock;
+ r = amdgpu_ring_test_ring(&vinst->ring_dec);
+ if (r)
+ goto unlock;
+ for (i = 0; i < vinst->num_enc_rings; i++) {
+ r = amdgpu_ring_test_ring(&vinst->ring_enc[i]);
+ if (r)
+ goto unlock;
+ }
+ amdgpu_fence_driver_force_completion(&vinst->ring_dec);
+ for (i = 0; i < vinst->num_enc_rings; i++)
+ amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]);
+
+ /* Restart the scheduler's work queue for the dec and enc rings
+ * if they were stopped by this function. This allows new tasks
+ * to be submitted to the queues after the reset is complete.
+ */
+ drm_sched_wqueue_start(&vinst->ring_dec.sched);
+ for (i = 0; i < vinst->num_enc_rings; i++)
+ drm_sched_wqueue_start(&vinst->ring_enc[i].sched);
+
+unlock:
+ mutex_unlock(&vinst->engine_reset_mutex);
+
+ return r;
+}
+
+/**
+ * amdgpu_vcn_ring_reset - Reset a VCN ring
+ * @ring: ring to reset
+ * @vmid: vmid of guilty job
+ * @timedout_fence: fence of timed out job
+ *
+ * This helper is for VCN blocks without unified queues because
+ * resetting the engine resets all queues in that case. With
+ * unified queues we have one queue per engine.
+ * Returns: 0 on success, or a negative error code on failure.
+ */
+int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
+ unsigned int vmid,
+ struct amdgpu_fence *timedout_fence)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (adev->vcn.inst[ring->me].using_unified_queue)
+ return -EINVAL;
+
+ return amdgpu_vcn_reset_engine(adev, ring->me);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 83adf81defc71..0bc0a94d7cf0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -330,7 +330,9 @@ struct amdgpu_vcn_inst {
struct dpg_pause_state *new_state);
int (*set_pg_state)(struct amdgpu_vcn_inst *vinst,
enum amd_powergating_state state);
+ int (*reset)(struct amdgpu_vcn_inst *vinst);
bool using_unified_queue;
+ struct mutex engine_reset_mutex;
};
struct amdgpu_vcn_ras {
@@ -552,5 +554,7 @@ void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev);
int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
-
+int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
+ unsigned int vmid,
+ struct amdgpu_fence *guilty_fence);
#endif
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 31/33] drm/amdgpu/vcn2: implement ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (29 preceding siblings ...)
2025-06-27 3:39 ` [PATCH 30/33] drm/amdgpu/vcn: add a helper framework for engine resets Alex Deucher
@ 2025-06-27 3:40 ` Alex Deucher
2025-06-27 3:40 ` [PATCH 32/33] drm/amdgpu/vcn2.5: " Alex Deucher
` (2 subsequent siblings)
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:40 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Use the new helpers to handle engine resets for VCN.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 148b651be7ca7..33d210a61483f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -98,6 +98,8 @@ static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
struct dpg_pause_state *new_state);
static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
+static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst);
+
/**
* vcn_v2_0_early_init - set function pointers and load microcode
*
@@ -213,6 +215,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
}
adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+ adev->vcn.inst[0].reset = vcn_v2_0_reset;
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1355,6 +1358,13 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
return 0;
}
+static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst)
+{
+ vcn_v2_0_stop(vinst);
+ vcn_v2_0_start(vinst);
+ return 0;
+}
+
static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
@@ -2176,6 +2186,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
@@ -2205,6 +2216,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 32/33] drm/amdgpu/vcn2.5: implement ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (30 preceding siblings ...)
2025-06-27 3:40 ` [PATCH 31/33] drm/amdgpu/vcn2: implement ring reset Alex Deucher
@ 2025-06-27 3:40 ` Alex Deucher
2025-06-27 3:40 ` [PATCH 33/33] drm/amdgpu/vcn3: " Alex Deucher
2025-07-01 15:25 ` [PATCH V12 00/33] Reset improvements Krzysztof Łopatowski
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:40 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Use the new helpers to handle engine resets for VCN.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 58b527a6b795f..49ec4a7775f90 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -102,6 +102,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
struct dpg_pause_state *new_state);
static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
+static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst);
static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN,
@@ -404,6 +405,7 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
+ adev->vcn.inst[j].reset = vcn_v2_5_reset;
}
if (amdgpu_sriov_vf(adev)) {
@@ -1816,6 +1818,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
/**
@@ -1914,6 +1917,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
@@ -1942,6 +1946,13 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
}
}
+static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst)
+{
+ vcn_v2_5_stop(vinst);
+ vcn_v2_5_start(vinst);
+ return 0;
+}
+
static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 33/33] drm/amdgpu/vcn3: implement ring reset
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (31 preceding siblings ...)
2025-06-27 3:40 ` [PATCH 32/33] drm/amdgpu/vcn2.5: " Alex Deucher
@ 2025-06-27 3:40 ` Alex Deucher
2025-07-01 15:25 ` [PATCH V12 00/33] Reset improvements Krzysztof Łopatowski
33 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-06-27 3:40 UTC (permalink / raw)
To: amd-gfx, christian.koenig, sasundar; +Cc: Alex Deucher, Sathishkumar S
Use the new helpers to handle engine resets for VCN.
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9fb0d53805892..dd015bc6fd0ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -110,6 +110,7 @@ static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
struct dpg_pause_state *new_state);
+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst);
static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
@@ -289,6 +290,7 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
+ adev->vcn.inst[i].reset = vcn_v3_0_reset;
}
if (amdgpu_sriov_vf(adev)) {
@@ -2033,6 +2035,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
/**
@@ -2131,6 +2134,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
@@ -2164,6 +2168,15 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
}
}
+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst)
+{
+ vcn_v3_0_stop(vinst);
+ vcn_v3_0_enable_clock_gating(vinst);
+ vcn_v3_0_enable_static_power_gating(vinst);
+ vcn_v3_0_start(vinst);
+ return 0;
+}
+
static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
--
2.50.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH V12 00/33] Reset improvements
2025-06-27 3:39 [PATCH V12 00/33] Reset improvements Alex Deucher
` (32 preceding siblings ...)
2025-06-27 3:40 ` [PATCH 33/33] drm/amdgpu/vcn3: " Alex Deucher
@ 2025-07-01 15:25 ` Krzysztof Łopatowski
2025-07-01 15:30 ` Alex Deucher
33 siblings, 1 reply; 43+ messages in thread
From: Krzysztof Łopatowski @ 2025-07-01 15:25 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, christian.koenig, sasundar
[-- Attachment #1: Type: text/plain, Size: 450 bytes --]
Hello Alex, I'm having trouble applying this patchset for testing.
Applying the first patch errors in
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:9579 I tried changing the base to
commit: (6.14) 38fec10eb60d687e30c8c6b5420d86e8149f7557 since it's what
git merge-base gives me between Linus's master and your kq_resets
branch, but no good. Would you please rebase your changes onto whichever
Linus's version tag you see as appropriate? Thanks, Chris
[-- Attachment #2: Type: text/html, Size: 644 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH V12 00/33] Reset improvements
2025-07-01 15:25 ` [PATCH V12 00/33] Reset improvements Krzysztof Łopatowski
@ 2025-07-01 15:30 ` Alex Deucher
0 siblings, 0 replies; 43+ messages in thread
From: Alex Deucher @ 2025-07-01 15:30 UTC (permalink / raw)
To: Krzysztof Łopatowski
Cc: Alex Deucher, amd-gfx, christian.koenig, sasundar
On Tue, Jul 1, 2025 at 11:26 AM Krzysztof Łopatowski
<krzysztof.m.lopatowski@gmail.com> wrote:
>
> Hello Alex, I'm having trouble applying this patchset for testing. Applying the first patch errors in drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:9579 I tried changing the base to commit: (6.14) 38fec10eb60d687e30c8c6b5420d86e8149f7557 since it's what git merge-base gives me between Linus's master and your kq_resets branch, but no good. Would you please rebase your changes onto whichever Linus's version tag you see as appropriate? Thanks, Chris
You'll need to use my drm-next branch or amd-staging-drm-next
(https://gitlab.freedesktop.org/agd5f/linux/-/branches) if you want to
apply the patches. Alternatively, you can use the git branch I
provided in the cover letter:
https://gitlab.freedesktop.org/agd5f/linux/-/commits/kq_resets?ref_type=heads
Alex
^ permalink raw reply [flat|nested] 43+ messages in thread