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From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: "Baptiste Le Duc" <baptiste.le-duc@vates.tech>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Connor Davis" <connojdavis@gmail.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Anthony PERARD" <anthony.perard@vates.tech>,
	"Michal Orzel" <michal.orzel@amd.com>,
	"Jan Beulich" <jbeulich@suse.com>,
	"Julien Grall" <julien@xen.org>,
	"Roger Pau Monné" <roger@xenproject.org>,
	"Stefano Stabellini" <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org, Zheng Zhang <zhangzheng@iscas.ac.cn>
Subject: Re: [PATCH v2 6/6] xen/riscv: fix level_map_mask truncation on load_start
Date: Tue, 22 Sep 2026 16:21:08 +0200	[thread overview]
Message-ID: <6bb95b82-3ef0-4931-aa21-6794360d26b5@gmail.com> (raw)
In-Reply-To: <1789032899.8631fc262581453bbf619ec5b2062170.1a08aaba3b8000c4f3@vates.tech>



On 9/10/26 11:34 AM, Baptiste Le Duc wrote:
> check_pgtbl_mode_support() declares level_map_mask as bare `unsigned`, i.e.
> a 32-bit type while it derives from a paddr_t which is in both RV32/RV64 a
> 64-bit type. Storing that value into a 32-bit local silently drops any set
> bits above bit 31.
> 
> The mask is then used as:
> 
>      aligned_load_start = load_start & level_map_mask;
> 
> load_start is `unsigned long` (64-bit on riscv64) and if it requires more
> than 32 bits to represent, because load_start zero-extend to 64 bits, we
> would drop some load_start's bits during the AND.
> 
> Widen level_map_mask to `unsigned long`, matching the width of the physical
> address.
> 
> Fixes: e66003e7be19 ("xen/riscv: introduce setup_initial_pages")
> Reported-by: Zheng Zhang <zhangzheng@iscas.ac.cn>
> Signed-off-by: Baptiste Le Duc <baptiste.le-duc@vates.tech>
> ---
> Changes since v1:
> - new patch
> ---
> Question:
> I would think replacing unsigned long by paddr_t would be better in this
> case but for consistency with other variables in the function I just kept
> unsigned long.
> 
> However, there are many variables in mm.c which are unsigned long while
> they are, in reality, physical addresses and could technically be paddr_t.
> Using paddr_t would also let us bypass the compiler's decision on what
> unsigned long extends to (u32 or u64, depending on the target), and
> therefore be more generic. I've seen similar code in Arm using this
> convention, and found nothing on the mailing list explaining the original
> choice of unsigned long over paddr_t.
> 
> Replacing every such field would be a fairly large change, so I'm asking
> for your opinion on whether it's worth doing.
> ---

I think if to do that it will better to do step by step where real use 
cases which lead to some problem will happen.

Specifically here it looks like `unsigned long` should be enough ...

>   xen/arch/riscv/mm.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c
> index 53bebbcabf..e7f2491257 100644
> --- a/xen/arch/riscv/mm.c
> +++ b/xen/arch/riscv/mm.c
> @@ -180,7 +180,7 @@ static bool __init check_pgtbl_mode_support(struct mmu_desc *mmu_desc,
>       bool is_mode_supported = false;
>       unsigned int index;
>       unsigned int page_table_level = (mmu_desc->num_levels - 1);
> -    unsigned level_map_mask = XEN_PT_LEVEL_MAP_MASK(page_table_level);
> +    unsigned long level_map_mask = XEN_PT_LEVEL_MAP_MASK(page_table_level);
>   
>       unsigned long aligned_load_start = load_start & level_map_mask;
>       unsigned long aligned_page_size = XEN_PT_LEVEL_SIZE(page_table_level);
>
... what you actually did.

LGTM: Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks for the fix!

~ Oleksii





  parent reply	other threads:[~2026-09-22 14:21 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-10  9:30 [PATCH v2 0/6] xen/riscv: fix boot on missing extensions and MMU setup bugs Baptiste Le Duc
2026-09-10  9:34 ` [PATCH v2 1/6] xen/riscv: fix Svade/Svadu A/D bit handling Baptiste Le Duc
2026-09-21 15:26   ` Jan Beulich
2026-09-21 17:03     ` Baptiste Le Duc
2026-09-22  6:24       ` Jan Beulich
2026-09-22  9:17         ` Baptiste Le Duc
2026-09-22 15:14           ` Oleksii Kurochko
2026-09-22 15:18             ` Baptiste Le Duc
2026-09-23  7:31           ` Oleksii Kurochko
2026-09-22 15:29   ` Oleksii Kurochko
2026-09-23 10:06     ` Baptiste Le Duc
2026-09-23 10:41       ` Oleksii Kurochko
2026-09-10  9:34 ` [PATCH v2 2/6] xen/riscv: set A/D bits in Xen's page-table mappings under Svade Baptiste Le Duc
2026-09-16  8:54   ` Zhang Zheng
2026-09-21 15:35   ` Jan Beulich
2026-09-22 15:05   ` Oleksii Kurochko
2026-09-10  9:34 ` [PATCH v2 3/6] xen/riscv: make Svpbmt no longer a required extension Baptiste Le Duc
2026-09-21 15:57   ` Jan Beulich
2026-09-22 14:38     ` Oleksii Kurochko
2026-09-28 13:21     ` Baptiste Le Duc
2026-09-22 14:48   ` Oleksii Kurochko
2026-09-10  9:34 ` [PATCH v2 4/6] xen/riscv: make Zihintpause " Baptiste Le Duc
2026-09-22 12:27   ` Jan Beulich
2026-09-22 14:26     ` Oleksii Kurochko
2026-09-22 15:10       ` Jan Beulich
2026-09-22 14:50   ` Oleksii Kurochko
2026-09-10  9:34 ` [PATCH v2 5/6] xen/riscv: flush speculatively cached Bare-mode TLB entries in turn_on_mmu() Baptiste Le Duc
2026-09-22 12:31   ` Jan Beulich
2026-09-22 14:21   ` Oleksii Kurochko
2026-09-10  9:34 ` [PATCH v2 6/6] xen/riscv: fix level_map_mask truncation on load_start Baptiste Le Duc
2026-09-16  8:54   ` Zhang Zheng
2026-09-22 12:43   ` Jan Beulich
2026-09-22 14:21   ` Oleksii Kurochko [this message]
2026-09-10  9:47 ` [PATCH v2 0/6] xen/riscv: fix boot on missing extensions and MMU setup bugs Jan Beulich
2026-09-10  9:56   ` Baptiste Le Duc

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