From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH 1/3] drm/i915: extract gmbus_wait_hw_status
Date: Wed, 05 Sep 2012 22:25:03 +0100 [thread overview]
Message-ID: <6c3329$5sb1j3@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch>
On Wed, 5 Sep 2012 21:24:39 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> The gmbus interrupt generation is rather fiddly: We can only ever
> enable one interrupt source (but we always want to check for NAK
> in addition to the real bit). And the bits in the gmbus status
> register don't map at all to the bis in the irq register.
>
> To prepare for this mess, start by extracting the hw status wait
> loop into it's own function, consolidate the NAK error handling a
> bit. To keep things flexible, pass in the status bit we care about
> (in addition to any NAK signalling).
There are some subtle changes in that we introduce new error detection
which is promptly ignored with a different wait period, but the changes
look good.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-09-05 21:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-05 19:24 [PATCH 1/3] drm/i915: extract gmbus_wait_hw_status Daniel Vetter
2012-09-05 19:24 ` [PATCH 2/3] drm/i915: wire up gmbus irq handler Daniel Vetter
2012-09-05 21:29 ` Chris Wilson
2012-09-05 21:36 ` Daniel Vetter
2012-09-05 21:52 ` Chris Wilson
2012-09-05 19:24 ` [PATCH 3/3] drm/i915: use the gmbus irq for waits Daniel Vetter
2012-09-05 21:34 ` Chris Wilson
2012-09-05 21:25 ` Chris Wilson [this message]
2012-09-05 21:30 ` [PATCH 1/3] drm/i915: extract gmbus_wait_hw_status Daniel Vetter
2012-09-05 22:12 ` Chris Wilson
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