From: Damien Le Moal <dlemoal@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Niklas Cassel" <cassel@kernel.org>
Subject: Re: [PATCH v5 12/14] PCI: rockchip-ep: Improve link training
Date: Sun, 17 Nov 2024 17:00:42 +0900 [thread overview]
Message-ID: <8393e56d-8ba1-436d-ad97-ec44893d2f6f@kernel.org> (raw)
In-Reply-To: <20241115230319.GA2065576@bhelgaas>
On 11/16/24 08:03, Bjorn Helgaas wrote:
> On Thu, Oct 17, 2024 at 10:58:47AM +0900, Damien Le Moal wrote:
>> The Rockchip RK3399 TRM V1.3 Part2, Section 17.5.8.1.2, step 7,
>> describes the endpoint mode link training process clearly and states
>> that:
>> Insure link training completion and success by observing link_st field
>> in PCIe Client BASIC_STATUS1 register change to 2'b11. If both side
>> support PCIe Gen2 speed, re-train can be Initiated by asserting the
>> Retrain Link field in Link Control and Status Register. The software
>> should insure the BASIC_STATUS0[negotiated_speed] changes to "1", that
>> indicates re-train to Gen2 successfully.
>
> Since this only adds code and doesn't change existing code, I assume
> this hardware doesn't automatically train to gen2 without this new
> software assistance?
>
> So the effect of this change is to use gen2 speed when supported by
> both partners, when previously we only got gen1?
Yes. The host side has something similar as well.
--
Damien Le Moal
Western Digital Research
WARNING: multiple messages have this Message-ID (diff)
From: Damien Le Moal <dlemoal@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Niklas Cassel" <cassel@kernel.org>
Subject: Re: [PATCH v5 12/14] PCI: rockchip-ep: Improve link training
Date: Sun, 17 Nov 2024 17:00:42 +0900 [thread overview]
Message-ID: <8393e56d-8ba1-436d-ad97-ec44893d2f6f@kernel.org> (raw)
In-Reply-To: <20241115230319.GA2065576@bhelgaas>
On 11/16/24 08:03, Bjorn Helgaas wrote:
> On Thu, Oct 17, 2024 at 10:58:47AM +0900, Damien Le Moal wrote:
>> The Rockchip RK3399 TRM V1.3 Part2, Section 17.5.8.1.2, step 7,
>> describes the endpoint mode link training process clearly and states
>> that:
>> Insure link training completion and success by observing link_st field
>> in PCIe Client BASIC_STATUS1 register change to 2'b11. If both side
>> support PCIe Gen2 speed, re-train can be Initiated by asserting the
>> Retrain Link field in Link Control and Status Register. The software
>> should insure the BASIC_STATUS0[negotiated_speed] changes to "1", that
>> indicates re-train to Gen2 successfully.
>
> Since this only adds code and doesn't change existing code, I assume
> this hardware doesn't automatically train to gen2 without this new
> software assistance?
>
> So the effect of this change is to use gen2 speed when supported by
> both partners, when previously we only got gen1?
Yes. The host side has something similar as well.
--
Damien Le Moal
Western Digital Research
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2024-11-17 8:00 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 1:58 [PATCH v5 00/14] Fix and improve the Rockchip endpoint driver Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 01/14] PCI: rockchip-ep: Fix address translation unit programming Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-11-15 22:41 ` Bjorn Helgaas
2024-11-15 22:41 ` Bjorn Helgaas
2024-11-17 8:04 ` Damien Le Moal
2024-11-17 8:04 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 02/14] PCI: rockchip-ep: Use a macro to define EP controller .align feature Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 03/14] PCI: rockchip-ep: Improve rockchip_pcie_ep_unmap_addr() Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 04/14] PCI: rockchip-ep: Improve rockchip_pcie_ep_map_addr() Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 05/14] PCI: rockchip-ep: Implement the pci_epc_ops::align_addr() operation Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 06/14] PCI: rockchip-ep: Fix MSI IRQ data mapping Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 9:52 ` Niklas Cassel
2024-10-17 9:52 ` Niklas Cassel
2024-10-17 1:58 ` [PATCH v5 07/14] PCI: rockchip-ep: Rename rockchip_pcie_parse_ep_dt() Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 08/14] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() memory allocations Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 09/14] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 10/14] PCI: rockchip-ep: Refactor endpoint link training enable Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 11/14] PCI: rockship-ep: Implement the pci_epc_ops::stop_link() operation Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 12/14] PCI: rockchip-ep: Improve link training Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-11-15 23:03 ` Bjorn Helgaas
2024-11-15 23:03 ` Bjorn Helgaas
2024-11-17 8:00 ` Damien Le Moal [this message]
2024-11-17 8:00 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 13/14] PCI: rockchip-ep: Handle PERST# signal in endpoint mode Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-12-15 0:13 ` Bjorn Helgaas
2024-12-15 0:13 ` Bjorn Helgaas
2024-12-15 2:09 ` Damien Le Moal
2024-12-15 2:09 ` Damien Le Moal
2024-10-17 1:58 ` [PATCH v5 14/14] arm64: dts: rockchip: Add rockpro64 overlay for PCIe " Damien Le Moal
2024-10-17 1:58 ` Damien Le Moal
2024-10-29 10:35 ` [PATCH v5 00/14] Fix and improve the Rockchip endpoint driver Damien Le Moal
2024-10-29 10:35 ` Damien Le Moal
2024-11-13 14:29 ` Damien Le Moal
2024-11-13 14:29 ` Damien Le Moal
2024-11-13 17:52 ` Manivannan Sadhasivam
2024-11-13 17:52 ` Manivannan Sadhasivam
2024-11-13 20:59 ` Krzysztof Wilczyński
2024-11-13 20:59 ` Krzysztof Wilczyński
2024-11-14 4:14 ` Damien Le Moal
2024-11-14 4:14 ` Damien Le Moal
2024-11-14 17:24 ` Krzysztof Wilczyński
2024-11-14 17:24 ` Krzysztof Wilczyński
2024-11-13 20:49 ` Krzysztof Wilczyński
2024-11-13 20:49 ` Krzysztof Wilczyński
2024-12-16 5:49 ` Manivannan Sadhasivam
2024-12-16 5:49 ` Manivannan Sadhasivam
2024-12-16 6:00 ` Niklas Cassel
2024-12-16 6:00 ` Niklas Cassel
2024-12-16 6:05 ` Manivannan Sadhasivam
2024-12-16 6:05 ` Manivannan Sadhasivam
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